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Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

Browse Source 
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, 

which are for MinnowBoard MAX open source project.


Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
2015-01-12 09:37:20 +00:00
committed by zwei4
parent 6f785cfcc3
commit 3cbfba02fe
518 changed files with 118538 additions and 0 deletions
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56
Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h Normal file
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/**
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchRegsHda.h
@brief
Register names for PCH High Definition Audio device.
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
**/
#ifndef _PCH_REGS_HDA_H_
#define _PCH_REGS_HDA_H_
///
/// Azalia Controller Registers (D27:F0)
///
#define PCI_DEVICE_NUMBER_PCH_AZALIA 27
#define PCI_FUNCTION_NUMBER_PCH_AZALIA 0
#define R_PCH_HDA_PCS 0x54 // Power Management Control and Status
#define B_PCH_HDA_PCS_DATA 0xFF000000 // Data, does not apply
#define B_PCH_HDA_PCS_CCE BIT23 // Bus Power Control Enable, does not apply
#define B_PCH_HDA_PCS_PMES BIT15 // PME Status
#define B_PCH_HDA_PCS_PMEE BIT8 // PME Enable
#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) // Power State - D0/D3 Hot
#define V_PCH_HDA_PCS_PS0 0x00
#define V_PCH_HDA_PCS_PS3 0x03
#endif

492
Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h Normal file
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/*++
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PchRegsLpss.h
Abstract:
Register names for VLV Low Input Output (LPSS) module.
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
--*/
#ifndef _PCH_REGS_LPSS_H_
#define _PCH_REGS_LPSS_H_
//
// Low Power Input Output (LPSS) Module Registers
//
//
// LPSS DMAC Modules
// PCI Config Space Registers
//
#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30
#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24
#define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0
#define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID
#define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID
#define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID
#define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command
#define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA
#define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA
#define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List
#define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
#define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable
#define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable
#define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable
#define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable
#define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code
#define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code
#define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID
#define R_PCH_LPSS_DMAC_CLHB 0x0C
#define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23
#define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type
#define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer
#define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size
#define R_PCH_LPSS_DMAC_BAR 0x10 // BAR
#define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address
#define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000
#define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14
#define B_PCH_LPSS_DMAC_BAR_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable
#define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space
#define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1
#define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address
#define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable
#define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space
#define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID
#define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID
#define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID
#define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR
#define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
#define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer
#define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power
#define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt
#define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency
#define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000
#define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin
#define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line
#define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID
#define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support
#define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version
#define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability
#define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability
#define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status
#define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status
#define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable
#define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset
#define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State
#define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID
#define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID
//
// LPSS I2C Module
// PCI Config Space Registers
//
#define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7
#define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID
#define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID
#define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID
#define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command
#define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
#define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
#define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
#define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
#define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable
#define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
#define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
#define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
#define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code
#define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code
#define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID
#define R_PCH_LPSS_I2C_CLHB 0x0C
#define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23
#define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type
#define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer
#define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size
#define R_PCH_LPSS_I2C_BAR 0x10 // BAR
#define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address
#define V_PCH_LPSS_I2C_BAR_SIZE 0x1000
#define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12
#define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
#define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1
#define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address
#define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
#define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID
#define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID
#define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID
#define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR
#define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
#define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer
#define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power
#define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt
#define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency
#define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000
#define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin
#define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line
#define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID
#define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support
#define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version
#define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability
#define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability
#define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status
#define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status
#define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable
#define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset
#define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State
#define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID
#define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID
//
// LPSS I2C Module
// Memory Space Registers
//
#define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset
#define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
#define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
//
// LPSS PWM Modules
// PCI Config Space Registers
//
#define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30
#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1
#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2
#define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID
#define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID
#define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID
#define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command
#define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA
#define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA
#define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List
#define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
#define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable
#define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable
#define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable
#define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable
#define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code
#define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code
#define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID
#define R_PCH_LPSS_PWM_CLHB 0x0C
#define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23
#define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type
#define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer
#define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size
#define R_PCH_LPSS_PWM_BAR 0x10 // BAR
#define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address
#define V_PCH_LPSS_PWM_BAR_SIZE 0x1000
#define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12
#define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable
#define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space
#define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1
#define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address
#define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable
#define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space
#define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID
#define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID
#define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID
#define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR
#define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
#define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer
#define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power
#define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt
#define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency
#define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000
#define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin
#define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line
#define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID
#define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support
#define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version
#define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability
#define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability
#define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status
#define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status
#define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable
#define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset
#define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State
#define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID
#define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID
//
// LPSS PWM Module
// Memory Space Registers
//
#define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset
#define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
#define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset
//
// LPSS HSUART Modules
// PCI Config Space Registers
//
#define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30
#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3
#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4
#define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID
#define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID
#define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID
#define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command
#define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA
#define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA
#define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List
#define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
#define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable
#define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable
#define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable
#define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable
#define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code
#define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code
#define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID
#define R_PCH_LPSS_HSUART_CLHB 0x0C
#define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23
#define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type
#define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer
#define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size
#define R_PCH_LPSS_HSUART_BAR 0x10 // BAR
#define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address
#define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000
#define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12
#define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable
#define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space
#define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1
#define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address
#define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable
#define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space
#define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID
#define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID
#define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID
#define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR
#define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
#define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer
#define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power
#define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt
#define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency
#define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000
#define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin
#define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line
#define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID
#define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support
#define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version
#define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability
#define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability
#define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status
#define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status
#define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable
#define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset
#define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State
#define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID
#define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID
//
// LPSS HSUART Module
// Memory Space Registers
//
#define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters
#define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
#define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
#define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
#define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable
#define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset
#define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
#define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset
//
// LPSS SPI Module
// PCI Config Space Registers
//
#define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30
#define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5
#define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID
#define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID
#define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID
#define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command
#define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA
#define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA
#define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List
#define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
#define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable
#define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable
#define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable
#define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable
#define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code
#define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code
#define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID
#define R_PCH_LPSS_SPI_CLHB 0x0C
#define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23
#define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type
#define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer
#define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size
#define R_PCH_LPSS_SPI_BAR 0x10 // BAR
#define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address
#define V_PCH_LPSS_SPI_BAR_SIZE 0x1000
#define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12
#define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable
#define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space
#define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1
#define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address
#define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator
#define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable
#define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type
#define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space
#define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID
#define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID
#define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID
#define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR
#define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
#define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer
#define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power
#define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt
#define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency
#define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000
#define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin
#define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line
#define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID
#define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support
#define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version
#define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability
#define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability
#define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status
#define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status
#define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
#define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset
#define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State
#define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID
#define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID
//
// LPSS SPI Module
// Memory Space Registers
//
#define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters
#define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
#define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
#define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
#define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable
#define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset
#define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
#define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset
#endif

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/**
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchRegsPcie.h
@brief
Register names for VLV PCI-E root port devices
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
--*/
#ifndef _PCH_REGS_PCIE_H_
#define _PCH_REGS_PCIE_H_
#define PCH_PCIE_MAX_ROOT_PORTS 4
///
/// VLV PCI Express Root Ports (D28:F0~F3)
///
#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28
#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
#define R_PCH_PCIE_ID 0x00 // Identifiers
#define B_PCH_PCIE_ID_DID 0xFFFF0000 // Device ID
#define V_PCH_PCIE_DEVICE_ID_0 0x0F48 // PCIE Root Port #1
#define V_PCH_PCIE_DEVICE_ID_1 0x0F4A // PCIE Root Port #2
#define V_PCH_PCIE_DEVICE_ID_2 0x0F4C // PCIE Root Port #3
#define V_PCH_PCIE_DEVICE_ID_3 0x0F4E // PCIE Root Port #4
#define B_PCH_PCIE_ID_VID 0x0000FFFF // Vendor ID
#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID
#define R_PCH_PCIE_BNUM_SLT 0x18 // Bus Numbers; Secondary Latency Timer
#define B_PCH_PCIE_BNUM_SLT_SLT 0xFF000000 // Secondary Latency Timer
#define B_PCH_PCIE_BNUM_SLT_SBBN 0x00FF0000 // Subordinate Bus Number
#define B_PCH_PCIE_BNUM_SLT_SCBN 0x0000FF00 // Secondary Bus Number
#define B_PCH_PCIE_BNUM_SLT_PBN 0x000000FF // Primary Bus Number
#define R_PCH_PCIE_CAPP 0x34 // Capabilities List Pointer
#define B_PCH_PCIE_CAPP 0xFF // Capabilities Pointer
#define R_PCH_PCIE_SLCTL_SLSTS 0x58 // Slot Control; Slot Status
#define S_PCH_PCIE_SLCTL_SLSTS 4
#define B_PCH_PCIE_SLCTL_SLSTS_DLLSC BIT24 // Data Link Layer State Changed
#define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State
#define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State
#define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed
#define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed
#define B_PCH_PCIE_SLCTL_SLSTS_PFD BIT17 // Power Fault Detected
#define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE BIT12 // Data Link Layer State Changed Enable
#define B_PCH_PCIE_SLCTL_SLSTS_PCC BIT10 // Power Controller Control
#define B_PCH_PCIE_SLCTL_SLSTS_HPE BIT5 // Hot Plug Interrupt Enable
#define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable
#define B_PCH_PCIE_SLCTL_SLSTS_PDE BIT3 // Presence Detect Changed Enable
#define R_PCH_PCIE_SVID 0x94 // Subsystem Vendor IDs
#define S_PCH_PCIE_SVID 4
#define B_PCH_PCIE_SVID_SID 0xFFFF0000 // Subsystem Identifier
#define B_PCH_PCIE_SVID_SVID 0x0000FFFF // Subsystem Vendor Identifier
#endif

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/**
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchRegsRcrb.h
@brief
Register names for VLV Chipset Configuration Registers
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
**/
#ifndef _PCH_REGS_RCRB_H_
#define _PCH_REGS_RCRB_H_
///
/// Chipset Configuration Registers (Memory space)
/// RCBA
///
#define R_PCH_RCRB_GCS 0x00 // General Control and Status
#define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size
#define B_PCH_RCRB_GCS_BBS (BIT11 | BIT10) // Boot BIOS Straps
#define V_PCH_RCRB_GCS_BBS_SPI (3 << 10) // Boot BIOS strapped to SPI
#define V_PCH_RCRB_GCS_BBS_LPC (0 << 10) // Boot BIOS strapped to LPC
#define B_PCH_RCRB_GCS_TS BIT1 // Top Swap
#define B_PCH_RCRB_GCS_BILD BIT0 // BIOS Interface Lock-Down
#endif

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/**
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchRegsSata.h
@brief
Register names for VLV SATA controllers
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
**/
#ifndef _PCH_REGS_SATA_H_
#define _PCH_REGS_SATA_H_
///
/// VLV SATA Message Bus
///
#define PCH_SATA_PHY_PORT_ID 0xA3 // SATA PHY Port ID
#define PCH_SATA_PHY_MMIO_READ_OPCODE 0x00 // CUnit to SATA PHY MMIO Read Opcode
#define PCH_SATA_PHY_MMIO_WRITE_OPCODE 0x01 // CUnit to SATA PHY MMIO Write Opcode
///
/// SATA Controller Registers (D19:F0)
///
#define PCI_DEVICE_NUMBER_PCH_SATA 19
#define PCI_FUNCTION_NUMBER_PCH_SATA 0
#define R_PCH_SATA_ID 0x00 // Identifiers
#define B_PCH_SATA_ID_DID 0xFFFF0000 // Device ID
#define B_PCH_SATA_ID_VID 0x0000FFFF // Vendor ID
#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID
#define V_PCH_SATA_DEVICE_ID_D_IDE 0x0F20 // Desktop IDE Mode (Ports 0 and 1)
#define V_PCH_SATA_DEVICE_ID_D_AHCI 0x0F22 // Desktop AHCI Mode (Ports 0 and 1)
#define V_PCH_SATA_DEVICE_ID_D_RAID 0x2822 // Desktop RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]
#define V_PCH_SATA_DEVICE_ID_M_IDE 0x0F21 // Mobile IDE Mode (Ports 0 and 1)
#define V_PCH_SATA_DEVICE_ID_M_AHCI 0x0F23 // Mobile AHCI Mode (Ports 0 and 1)
#define V_PCH_SATA_DEVICE_ID_M_RAID 0x282A // Mobile RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]
#define R_PCH_SATA_COMMAND 0x04 // Command
#define B_PCH_SATA_COMMAND_INT_DIS BIT10 // Interrupt Disable
#define B_PCH_SATA_COMMAND_FBE BIT9 // Fast Back-to-back Enable
#define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable
#define B_PCH_SATA_COMMAND_WCC BIT7 // Wait Cycle Enable
#define B_PCH_SATA_COMMAND_PER BIT6 // Parity Error Response Enable
#define B_PCH_SATA_COMMAND_VPS BIT5 // VGA Palette Snooping Enable
#define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable
#define B_PCH_SATA_COMMAND_SCE BIT3 // Special Cycle Enable
#define B_PCH_SATA_COMMAND_BME BIT2 // Bus Master Enable
#define B_PCH_SATA_COMMAND_MSE BIT1 // Memory Space Enable
#define B_PCH_SATA_COMMAND_IOSE BIT0 // I/O Space Enable
#define R_PCH_SATA_PCISTS 0x06 // Device Status
#define B_PCH_SATA_PCISTS_DPE BIT15 // Detected Parity Error
#define B_PCH_SATA_PCISTS_SSE BIT14 // Signaled System Error
#define B_PCH_SATA_PCISTS_RMA BIT13 // Received Master-Abort Status
#define B_PCH_SATA_PCISTS_RTA BIT12 // Received Target-Abort Status
#define B_PCH_SATA_PCISTS_STA BIT11 // Signaled Target-Abort Status
#define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 | BIT9) // DEVSEL# Timing Status
#define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected
#define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List
#define B_PCH_SATA_PCISTS_ITNS BIT3 // Interrupt Status
#define R_PCH_SATA_RID 0x08 // Revision ID (8 bits)
#define R_PCH_SATA_PI_REGISTER 0x09 // Programming Interface (8 bits)
#define B_PCH_SATA_PI_REGISTER_SNC BIT3 // Secondary Mode Native Capable
#define B_PCH_SATA_PI_REGISTER_SNE BIT2 // Secondary Mode Native Enable
#define B_PCH_SATA_PI_REGISTER_PNC BIT1 // Primary Mode Native Capable
#define B_PCH_SATA_PI_REGISTER_PNE BIT0 // Primary Mode Native Enable
#define R_PCH_SATA_CC 0x0A // Class Code
#define B_PCH_SATA_CC_BCC 0xFF00 // Base Class Code
#define B_PCH_SATA_CC_SCC 0x00FF // Sub Class Code
#define V_PCH_SATA_CC_SCC_IDE 0x01
#define V_PCH_SATA_CC_SCC_AHCI 0x06
#define V_PCH_SATA_CC_SCC_RAID 0x04
#define R_PCH_SATA_CLS 0x0C // Cache Line Size (8 bits)
#define B_PCH_SATA_CLS 0xFF
#define R_PCH_SATA_MLT 0x0D // Master Latency Timer (8 bits)
#define B_PCH_SATA_MLT 0xFF
#define R_PCH_SATA_HTYPE 0x0E // Header Type
#define B_PCH_SATA_HTYPE_MFD BIT7 // Multi-function Device
#define B_PCH_SATA_HTYPE_HL 0x7F // Header Layout
#define R_PCH_SATA_PCMD_BAR 0x10 // Primary Command Block Base Address
#define B_PCH_SATA_PCMD_BAR_BA 0x0000FFF8 // Base Address
#define B_PCH_SATA_PCMD_BAR_RTE BIT0 // Resource Type Indicator
#define R_PCH_SATA_PCTL_BAR 0x14 // Primary Control Block Base Address
#define B_PCH_SATA_PCTL_BAR_BA 0x0000FFFC // Base Address
#define B_PCH_SATA_PCTL_BAR_RTE BIT0 // Resource Type Indicator
#define R_PCH_SATA_SCMD_BAR 0x18 // Secondary Command Block Base Address
#define B_PCH_SATA_SCMD_BAR_BA 0x0000FFF8 // Base Address
#define B_PCH_SATA_SCMD_BAR_RTE BIT0 // Resource Type Indicator
#define R_PCH_SATA_SCTL_BAR 0x1C // Secondary Control Block Base Address
#define B_PCH_SATA_SCTL_BAR_BA 0x0000FFFC // Base Address
#define B_PCH_SATA_SCTL_BAR_RTE BIT0 // Resource Type Indicator
#define R_PCH_SATA_LBAR 0x20 // Legacy IDE Base Address / AHCI Index Data Pair Base Address
#define B_PCH_SATA_LBAR_BA 0x0000FFE0 // Base Address
#define B_PCH_SATA_LBAR_BA4 BIT4 // Base Address 4
#define B_PCH_SATA_LBAR_RTE BIT0 // Resource Type Indicator
#define R_PCH_SATA_SIDPBA 0x24 // Serial ATA Index Data Pair Base Address
#define R_PCH_SATA_ABAR 0x24 // AHCI Base Address
#define B_PCH_SATA_ABAR_BA 0xFFFFF800 // AHCI Memory Base Address (When CC.SCC not equal 0x01)
#define V_PCH_SATA_ABAR_LENGTH 0x800 // AHCI Memory Length (When CC.SCC not equal 0x01)
#define N_PCH_SATA_ABAR_ALIGNMENT 11 // AHCI Base Address Alignment (When CC.SCC not equal 0x01)
#define B_PCH_SATA_SIDPBA_BA 0x0000FFF0 // Serial ATA Index Data Pair IO Base Address (When CC.SCC equal 0x01)
#define V_PCH_SATA_SIDPBA_LENGTH 0x10 // Serial ATA Index Data Pair IO Length (When CC.SCC equal 0x01)
#define N_PCH_SATA_SIDPBA_ALIGNMENT 4 // Serial ATA Index Data Pair Base Address Alignment (When CC.SCC not equal 0x01)
#define B_PCH_SATA_ABAR_PF BIT3 // Prefetchable
#define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type
#define B_PCH_SATA_ABAR_RTE BIT0 // Resource Type Indicator
#define R_PCH_SATA_SS 0x2C // Sub System Identifiers
#define B_PCH_SATA_SS_SSID 0xFFFF0000 // Subsystem ID
#define B_PCH_SATA_SS_SSVID 0x0000FFFF // Subsystem Vendor ID
#define R_PCH_SATA_AHCI_CAP_PTR 0x34 // Capabilities Pointer (8 bits)
#define B_PCH_SATA_AHCI_CAP_PTR 0xFF
#define R_PCH_SATA_INTR 0x3C // Interrupt Information
#define B_PCH_SATA_INTR_IPIN 0xFFFF0000 // Interrupt Pin
#define B_PCH_SATA_INTR_ILINE 0x0000FFFF // Interrupt Line
#define R_PCH_SATA_PMCS 0x74 // PCI Power Management Control and Status
#define B_PCH_SATA_PMCS_PMES BIT15 // PME Status
#define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable
#define B_PCH_SATA_PMCS_NSFRST BIT3 // No Soft Reset
#define V_PCH_SATA_PMCS_NSFRST_1 0x01
#define V_PCH_SATA_PMCS_NSFRST_0 0x00
#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State
#define V_PCH_SATA_PMCS_PS_3 0x03
#define V_PCH_SATA_PMCS_PS_0 0x00
#define R_PCH_SATA_MAP 0x90 // Port Mapping Register
#define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable
#define B_PCH_SATA_PORT6_DISABLED BIT14
#define B_PCH_SATA_PORT5_DISABLED BIT13
#define B_PCH_SATA_PORT4_DISABLED BIT12
#define B_PCH_SATA_PORT3_DISABLED BIT11
#define B_PCH_SATA_PORT2_DISABLED BIT10
#define B_PCH_SATA_PORT1_DISABLED BIT9
#define B_PCH_SATA_PORT0_DISABLED BIT8
#define B_PCH_SATA_MAP_SMS_MASK (BIT7 | BIT6) // SATA Mode Select
#define V_PCH_SATA_MAP_SMS_IDE 0x00
#define V_PCH_SATA_MAP_SMS_AHCI 0x40
#define V_PCH_SATA_MAP_SMS_RAID 0x80
#define B_PCH_SATA_PORT_TO_CONTROLLER_CFG BIT5 // SATA Port-to-Controller Configuration
#define R_PCH_SATA_PCS 0x92 // Port Control and Status
#define S_PCH_SATA_PCS 0x2
#define B_PCH_SATA_PCS_OOB_RETRY BIT15 // OOB Retry Mode
#define B_PCH_SATA_PCS_PORT6_DET BIT14 // Port 6 Present
#define B_PCH_SATA_PCS_PORT5_DET BIT13 // Port 5 Present
#define B_PCH_SATA_PCS_PORT4_DET BIT12 // Port 4 Present
#define B_PCH_SATA_PCS_PORT3_DET BIT11 // Port 3 Present
#define B_PCH_SATA_PCS_PORT2_DET BIT10 // Port 2 Present
#define B_PCH_SATA_PCS_PORT1_DET BIT9 // Port 1 Present
#define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present
#define B_PCH_SATA_PCS_PORT5_EN BIT5 // Port 5 Enabled
#define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled
#define B_PCH_SATA_PCS_PORT3_EN BIT3 // Port 3 Enabled
#define B_PCH_SATA_PCS_PORT2_EN BIT2 // Port 2 Enabled
#define B_PCH_SATA_PCS_PORT1_EN BIT1 // Port 1 Enabled
#define B_PCH_SATA_PCS_PORT0_EN BIT0 // Port 0 Enabled
#define R_PCH_SATA_AHCI_PI 0x0C // Ports Implemented
#define B_PCH_SATA_PORT_MASK 0x3F
#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 // Port 5 Implemented
#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented
#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 // Port 3 Implemented
#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 // Port 2 Implemented
#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 // Port 1 Implemented
#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 // Port 0 Implemented
#define R_PCH_SATA_AHCI_P0SSTS 0x128 // Port 0 Serial ATA Status
#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 // Port 1 Serial ATA Status
#define B_PCH_SATA_AHCI_PXSSTS_IPM 0x00000F00 // Interface Power Management
#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000
#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100
#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200
#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600
#define B_PCH_SATA_AHCI_PXSSTS_SPD 0x000000F0 // Current Interface Speed
#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000
#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010
#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020
#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030
#define B_PCH_SATA_AHCI_PXSSTS_DET 0x0000000F // Device Detection
#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000
#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001
#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003
#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004
//
// Macros of VLV capabilities for SATA controller which are used by SATA controller driver
//
//
//
// Define the individual capabilities of each SATA controller
//
#define PCH_SATA_MAX_CONTROLLERS 1 // Max SATA controllers number supported
#define PCH_SATA_MAX_DEVICES 2 // Max SATA devices number of single SATA channel
#define PCH_IDE_MAX_CHANNELS 2 // Max IDE channels number of single SATA controller
#define PCH_IDE_MAX_DEVICES 2 // Max IDE devices number of single SATA channel
#define PCH_AHCI_MAX_PORTS 2 // Max number of SATA ports in VLV
#define PCH_IDE_MAX_PORTS 2 // Max number of IDE ports in VLV
//
// GPIOS_14 SATA0GP is the SATA port 0 reset pin.
//
#define PCH_GPIO_SATA_PORT0_RESET 14
//
// GPIOS_15 SATA1GP is the SATA port 1 reset pin.
//
#define PCH_GPIO_SATA_PORT1_RESET 15
#endif

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/*++
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PchRegsScc.h
Abstract:
Register names for VLV SCC module.
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
--*/
#ifndef _PCH_REGS_SCC_H_
#define _PCH_REGS_SCC_H_
//
// SCC Modules Registers
//
//
// SCC SDIO Modules
// PCI Config Space Registers
//
#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_0 16
#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_1 17
#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_2 18
#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_3 23
#define PCI_FUNCTION_NUMBER_PCH_SCC_SDIO 0
#endif

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/**
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchRegsSmbus.h
@brief
Register names for VLV Smbus Device.
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
**/
#ifndef _PCH_REGS_SMBUS_H_
#define _PCH_REGS_SMBUS_H_
///
/// SMBus Controller Registers (D31:F3)
///
#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
#define PCI_FUNCTION_NUMBER_PCH_SMBUS 3
#define R_PCH_SMBUS_VENDOR_ID 0x00 // Vendor ID
#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
#define R_PCH_SMBUS_DEVICE_ID 0x02 // Device ID
#define V_PCH_SMBUS_DEVICE_ID 0x0F12
#define R_PCH_SMBUS_PCICMD 0x04 // CMD register enables/disables, Memory/IO space access and interrupt
#define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 // Interrupt Disable
#define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0'
#define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 // SERR Enable - reserved as '0'
#define B_PCH_SMBUS_PCICMD_WCC BIT7 // Wait Cycle Control - reserved as '0'
#define B_PCH_SMBUS_PCICMD_PER BIT6 // Parity Error - reserved as '0'
#define B_PCH_SMBUS_PCICMD_VPS BIT5 // VGA Palette Snoop - reserved as '0'
#define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'
#define B_PCH_SMBUS_PCICMD_SCE BIT3 // Special Cycle Enable - reserved as '0'
#define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0'
#define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable
#define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable
#define R_PCH_SMBUS_BASE 0x20 // The I/O memory bar
#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 // Base Address
#define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator
#define R_PCH_SMBUS_SVID 0x2C // Subsystem Vendor ID
#define B_PCH_SMBUS_SVID 0xFFFF // Subsystem Vendor ID
//
// SMBus I/O Registers
//
#define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W
#define B_PCH_SMBUS_HSTS_ALL 0xFF
#define B_PCH_SMBUS_BYTE_DONE_STS BIT7 // Byte Done Status
#define B_PCH_SMBUS_IUS BIT6 // In Use Status
#define B_PCH_SMBUS_SMBALERT_STS BIT5 // SMBUS Alert
#define B_PCH_SMBUS_FAIL BIT4 // Failed
#define B_PCH_SMBUS_BERR BIT3 // Bus Error
#define B_PCH_SMBUS_DERR BIT2 // Device Error
#define B_PCH_SMBUS_ERRORS (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)
#define B_PCH_SMBUS_INTR BIT1 // Interrupt
#define B_PCH_SMBUS_HBSY BIT0 // Host Busy
#define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W
#define B_PCH_SMBUS_PEC_EN BIT7 // Packet Error Checking Enable
#define B_PCH_SMBUS_START BIT6 // Start
#define B_PCH_SMBUS_LAST_BYTE BIT5 // Last Byte
#define B_PCH_SMBUS_SMB_CMD 0x1C // SMB Command
#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C // Block Process
#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 // I2C Read
#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block
#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 // Process Call
#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C // Word Data
#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data
#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 // Byte
#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 // Quick
#define B_PCH_SMBUS_KILL BIT1 // Kill
#define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable
#define R_PCH_SMBUS_HCMD 0x03 // Host Command Register R/W
#define B_PCH_SMBUS_HCMD 0xFF // Command to be transmitted
#define R_PCH_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W
#define B_PCH_SMBUS_ADDRESS 0xFE // 7-bit address of the targeted slave
#define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = write
#define B_PCH_SMBUS_RW_SEL_READ 0x01 // Read
#define B_PCH_SMBUS_RW_SEL_WRITE 0x00 // Write
//
#define R_PCH_SMBUS_HD0 0x05 // Data 0 Register R/W
#define R_PCH_SMBUS_HD1 0x06 // Data 1 Register R/W
#define R_PCH_SMBUS_HBD 0x07 // Host Block Data Register R/W
#define R_PCH_SMBUS_PEC 0x08 // Packet Error Check Data Register R/W
#define R_PCH_SMBUS_RSA 0x09 // Receive Slave Address Register R/W
#define B_PCH_SMBUS_SLAVE_ADDR 0x7F // TCO slave address (Not used, reserved)
#define R_PCH_SMBUS_SD 0x0A // Receive Slave Data Register R/W
#define R_PCH_SMBUS_AUXS 0x0C // Auxiliary Status Register R/WC
#define B_PCH_SMBUS_CRCE BIT0 // CRC Error
//
#define R_PCH_SMBUS_AUXC 0x0D // Auxiliary Control Register R/W
#define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer
#define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC
#define R_PCH_SMBUS_SMLC 0x0E // SMLINK Pin Control Register R/W
#define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported
#define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported
#define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported
#define R_PCH_SMBUS_SMBC 0x0F // SMBus Pin Control Register R/W
#define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control
#define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status
#define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status
#define R_PCH_SMBUS_SSTS 0x10 // Slave Status Register R/WC
#define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status
#define R_PCH_SMBUS_SCMD 0x11 // Slave Command Register R/W
#define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported
#define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable
#define B_PCH_SMBUS_HOST_NOTIFY_INTREN BIT0 // Host Notify Interrupt Enable
#define R_PCH_SMBUS_NDA 0x14 // Notify Device Address Register RO
#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE // Device Address
#define R_PCH_SMBUS_NDLB 0x16 // Notify Data Low Byte Register RO
#define R_PCH_SMBUS_NDHB 0x17 // Notify Data High Byte Register RO
#endif

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/**
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchRegsSpi.h
@brief
Register names for PCH SPI device.
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
**/
#ifndef _PCH_REGS_SPI_H_
#define _PCH_REGS_SPI_H_
///
/// SPI Host Interface Registers
///
#define R_PCH_SPI_HSFS 0x04 // Hardware Sequencing Flash Status Register (16bits)
#define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down
#define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid
#define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status
#define B_PCH_SPI_HSFS_SCIP BIT5 // SPI Cycle in Progress
#define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) // Block / Sector Erase Size
#define V_PCH_SPI_HSFS_BERASE_256B 0x00 // Block/Sector = 256 Bytes
#define V_PCH_SPI_HSFS_BERASE_4K 0x01 // Block/Sector = 4K Bytes
#define V_PCH_SPI_HSFS_BERASE_8K 0x10 // Block/Sector = 8K Bytes
#define V_PCH_SPI_HSFS_BERASE_64K 0x11 // Block/Sector = 64K Bytes
#define B_PCH_SPI_HSFS_AEL BIT2 // Access Error Log
#define B_PCH_SPI_HSFS_FCERR BIT1 // Flash Cycle Error
#define B_PCH_SPI_HSFS_FDONE BIT0 // Flash Cycle Done
#define R_PCH_SPI_PR0 0x74 // Protected Region 0 Register
#define B_PCH_SPI_PR0_WPE BIT31 // Write Protection Enable
#define B_PCH_SPI_PR0_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]
#define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
#define B_PCH_SPI_PR0_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]
#define R_PCH_SPI_PREOP 0x94 // Prefix Opcode Configuration Register (16 bits)
#define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask
#define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask
#define R_PCH_SPI_OPTYPE 0x96 // Opcode Type Configuration
#define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
#define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) // Opcode Type 6 Mask
#define B_PCH_SPI_OPTYPE5_MASK (BIT11 | BIT10) // Opcode Type 5 Mask
#define B_PCH_SPI_OPTYPE4_MASK (BIT9 | BIT8) // Opcode Type 4 Mask
#define B_PCH_SPI_OPTYPE3_MASK (BIT7 | BIT6) // Opcode Type 3 Mask
#define B_PCH_SPI_OPTYPE2_MASK (BIT5 | BIT4) // Opcode Type 2 Mask
#define B_PCH_SPI_OPTYPE1_MASK (BIT3 | BIT2) // Opcode Type 1 Mask
#define B_PCH_SPI_OPTYPE0_MASK (BIT1 | BIT0) // Opcode Type 0 Mask
#define V_PCH_SPI_OPTYPE_RDNOADDR 0x00 // Read cycle type without address
#define V_PCH_SPI_OPTYPE_WRNOADDR 0x01 // Write cycle type without address
#define V_PCH_SPI_OPTYPE_RDADDR 0x02 // Address required; Read cycle type
#define V_PCH_SPI_OPTYPE_WRADDR 0x03 // Address required; Write cycle type
#define R_PCH_SPI_OPMENU0 0x98 // Opcode Menu Configuration 0 (32bits)
#define R_PCH_SPI_OPMENU1 0x9C // Opcode Menu Configuration 1 (32bits)
#define R_PCH_SPI_IND_LOCK 0xA4 // Indvidual Lock
#define B_PCH_SPI_IND_LOCK_PR0 BIT2 // PR0 LockDown
#define R_PCH_SPI_FDOC 0xB0 // Flash Descriptor Observability Control Register (32 bits)
#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select
#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 // Flash Signature and Descriptor Map
#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 // Component
#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 // Region
#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 // Master
#define V_PCH_SPI_FDOC_FDSS_VLVS 0x4000 // Soft Straps
#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC // Flash Descriptor Section Index
#define R_PCH_SPI_FDOD 0xB4 // Flash Descriptor Observability Data Register (32 bits)
#define R_PCH_SPI_BCR 0xFC // BIOS Control Register
#define S_PCH_SPI_BCR 1
#define B_PCH_SPI_BCR_SMM_BWP BIT5 // SMM BIOS Write Protect Disable
#define B_PCH_SPI_BCR_SRC (BIT3 | BIT2) // SPI Read Configuration (SRC)
#define V_PCH_SPI_BCR_SRC_PREF_EN_CACHE_EN 0x08 // Prefetch Enable, Cache Enable
#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 // Prefetch Disable, Cache Disable
#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_EN 0x00 // Prefetch Disable, Cache Enable
#define B_PCH_SPI_BCR_BLE BIT1 // Lock Enable (LE)
#define B_PCH_SPI_BCR_BIOSWE BIT0 // Write Protect Disable (WPD)
#define N_PCH_SPI_BCR_BLE 1
#define N_PCH_SPI_BCR_BIOSWE 0
//
// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
//
#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 // Flash Valid Signature
#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A
#endif

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/**
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchRegsUsb.h
@brief
Register names for PCH USB devices.
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values of bits within the registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
- In general, PCH registers are denoted by "_PCH_" in register names
- Registers / bits that are different between PCH generations are denoted by
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
at the end of the register/bit names
- Registers / bits of new devices introduced in a PCH generation will be just named
as "_PCH_" without <generation_name> inserted.
**/
#ifndef _PCH_REGS_USB_H_
#define _PCH_REGS_USB_H_
///
/// USB Definitions
///
typedef enum {
PchEhci1 = 0,
PchEhciControllerMax
} PCH_USB20_CONTROLLER_TYPE;
#define PCH_USB_MAX_PHYSICAL_PORTS 4 /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.
#define PCH_EHCI_MAX_PORTS 4 /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.
#define PCH_HSIC_MAX_PORTS 2
#define PCH_XHCI_MAX_USB3_PORTS 1
#define PCI_DEVICE_NUMBER_PCH_USB 29
#define PCI_FUNCTION_NUMBER_PCH_EHCI 0
#define R_PCH_USB_VENDOR_ID 0x00 // Vendor ID
#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
#define R_PCH_USB_DEVICE_ID 0x02 // Device ID
#define V_PCH_USB_DEVICE_ID_0 0x0F34 // EHCI#1
#define R_PCH_EHCI_SVID 0x2C // USB2 Subsystem Vendor ID
#define B_PCH_EHCI_SVID 0xFFFF // USB2 Subsystem Vendor ID Mask
#define R_PCH_EHCI_PWR_CNTL_STS 0x54 // Power Management Control / Status
#define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 // PME Status
#define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) // Data Scale
#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) // Data Select
#define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 // Power Enable
#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State
#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0 0 // D0 State
#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) // D3 Hot State
///
/// USB3 (XHCI) related definitions
///
#define PCI_DEVICE_NUMBER_PCH_XHCI 20
#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
//
/////
///// XHCI PCI Config Space registers
/////
#define R_PCH_XHCI_SVID 0x2C
#define B_PCH_XHCI_SVID 0xFFFF
#define R_PCH_XHCI_PWR_CNTL_STS 0x74
#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)
#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
#endif