Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
@@ -0,0 +1,81 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchInit.h
|
||||
|
||||
@brief
|
||||
This file defines the PCH Init PPI
|
||||
|
||||
**/
|
||||
#ifndef _PCH_INIT_H_
|
||||
#define _PCH_INIT_H_
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||||
|
||||
//
|
||||
// Define the PCH Init PPI GUID
|
||||
//
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||||
|
||||
|
||||
#include <Protocol/PchPlatformPolicy.h>
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||||
#define PCH_INIT_PPI_GUID \
|
||||
{ \
|
||||
0x9ea894a, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x95 \
|
||||
}
|
||||
extern EFI_GUID gPchInitPpiGuid;
|
||||
|
||||
///
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/// Forward reference for ANSI C compatibility
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||||
///
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typedef struct _PCH_INIT_PPI PCH_INIT_PPI;
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||||
|
||||
///
|
||||
/// Data structure definitions
|
||||
///
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||||
typedef enum _CPU_STRAP_OPERATION {
|
||||
GetCpuStrapSetData,
|
||||
SetCpuStrapSetData,
|
||||
LockCpuStrapSetData
|
||||
} CPU_STRAP_OPERATION;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PCH_USB_INIT) (
|
||||
IN EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
The function performing USB init in PEI phase. This could be used by USB recovery
|
||||
or debug features that need USB initialization during PEI phase.
|
||||
Note: Before executing this function, please be sure that PCH_INIT_PPI.Initialize
|
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has been done and PchUsbPolicyPpi has been installed.
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||||
|
||||
@param[in] PeiServices General purpose services available to every PEIM
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||||
|
||||
@retval EFI_SUCCESS The function completed successfully
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@retval Others All other error conditions encountered result in an ASSERT.
|
||||
|
||||
**/
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||||
;
|
||||
|
||||
///
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/// PCH_INIT_PPI Structure Definition
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||||
///
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struct _PCH_INIT_PPI {
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PCH_USB_INIT UsbInit;
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};
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|
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#endif
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@@ -0,0 +1,40 @@
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|
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/*++
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PchPeiInit.h
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||||
|
||||
Abstract:
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||||
|
||||
|
||||
--*/
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||||
|
||||
#ifndef _PCH_PEI_INIT_H_
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#define _PCH_PEI_INIT_H_
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|
||||
//
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// Define the PCH PEI Init PPI GUID
|
||||
//
|
||||
#define PCH_PEI_INIT_PPI_GUID \
|
||||
{ \
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||||
0xACB93B08, 0x5CDC, 0x4A8F, 0x93, 0xD4, 0x6, 0xE3, 0x42, 0xDF, 0x18, 0x2E \
|
||||
}
|
||||
|
||||
//
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// Extern the GUID for PPI users.
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||||
//
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||||
extern EFI_GUID gPchPeiInitPpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,167 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchPlatformPolicy.h
|
||||
|
||||
@brief
|
||||
PCH policy PPI produced by a platform driver specifying various
|
||||
expected PCH settings. This PPI is consumed by the PCH PEI modules.
|
||||
|
||||
**/
|
||||
#ifndef PCH_PLATFORM_POLICY_H_
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||||
#define PCH_PLATFORM_POLICY_H_
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||||
//
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||||
// External include files do NOT need to be explicitly specified in real EDKII
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||||
// environment
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||||
//
|
||||
|
||||
|
||||
#include "PchRegs.h"
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||||
|
||||
//
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||||
#define PCH_PLATFORM_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \
|
||||
}
|
||||
|
||||
extern EFI_GUID gPchPlatformPolicyPpiGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;
|
||||
|
||||
///
|
||||
/// PPI revision number
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||||
/// Any backwards compatible changes to this PPI will result in an update in the revision number
|
||||
/// Major changes will require publication of a new PPI
|
||||
///
|
||||
/// Revision 1: Original version
|
||||
///
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_1 1
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_2 2
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_3 3
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_4 4
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_5 5
|
||||
//
|
||||
// Generic definitions for device enabling/disabling used by PCH code.
|
||||
//
|
||||
#define PCH_DEVICE_ENABLE 1
|
||||
#define PCH_DEVICE_DISABLE 0
|
||||
|
||||
typedef struct {
|
||||
UINT8 ThermalDataReportEnable : 1; // OBSOLETE from Revision 5 !!! DO NOT USE !!!
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||||
UINT8 MchTempReadEnable : 1;
|
||||
UINT8 PchTempReadEnable : 1;
|
||||
UINT8 CpuEnergyReadEnable : 1;
|
||||
UINT8 CpuTempReadEnable : 1;
|
||||
UINT8 Cpu2TempReadEnable : 1;
|
||||
UINT8 TsOnDimmEnable : 1;
|
||||
UINT8 Dimm1TempReadEnable : 1;
|
||||
|
||||
UINT8 Dimm2TempReadEnable : 1;
|
||||
UINT8 Dimm3TempReadEnable : 1;
|
||||
UINT8 Dimm4TempReadEnable : 1;
|
||||
UINT8 Rsvdbits : 5;
|
||||
} PCH_THERMAL_REPORT_CONTROL;
|
||||
//
|
||||
// ---------------------------- HPET Config -----------------------------
|
||||
//
|
||||
typedef struct {
|
||||
BOOLEAN Enable; /// Determines if enable HPET function
|
||||
UINT32 Base; /// The HPET base address
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||||
} PCH_HPET_CONFIG;
|
||||
|
||||
|
||||
///
|
||||
/// ---------------------------- SATA Config -----------------------------
|
||||
///
|
||||
typedef enum {
|
||||
PchSataModeIde,
|
||||
PchSataModeAhci,
|
||||
PchSataModeRaid,
|
||||
PchSataModeMax
|
||||
} PCH_SATA_MODE;
|
||||
|
||||
///
|
||||
/// ---------------------------- PCI Express Config -----------------------------
|
||||
///
|
||||
typedef enum {
|
||||
PchPcieAuto,
|
||||
PchPcieGen1,
|
||||
PchPcieGen2
|
||||
} PCH_PCIE_SPEED;
|
||||
|
||||
typedef struct {
|
||||
PCH_PCIE_SPEED PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];
|
||||
} PCH_PCIE_CONFIG;
|
||||
|
||||
///
|
||||
/// ---------------------------- IO APIC Config -----------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 IoApicId;
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||||
} PCH_IOAPIC_CONFIG;
|
||||
|
||||
///
|
||||
/// --------------------- Low Power Input Output Config ------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled
|
||||
UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled
|
||||
UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled
|
||||
UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled
|
||||
UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled
|
||||
UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled
|
||||
UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled
|
||||
UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled
|
||||
UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled
|
||||
UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled
|
||||
UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled
|
||||
UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled
|
||||
UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled
|
||||
UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled
|
||||
UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled
|
||||
UINT8 Rsvdbits : 2;
|
||||
} PEI_PCH_LPSS_CONFIG;
|
||||
|
||||
///
|
||||
/// ------------ General PCH Platform Policy PPI definition ------------
|
||||
///
|
||||
struct _PCH_PLATFORM_POLICY_PPI {
|
||||
UINT8 Revision;
|
||||
UINT8 BusNumber; // Bus Number of the PCH device
|
||||
UINT32 SpiBase; // SPI Base Address.
|
||||
UINT32 PmcBase; // PMC Base Address.
|
||||
UINT32 SmbmBase; // SMB Memory Base Address.
|
||||
UINT32 IoBase; // IO Base Address.
|
||||
UINT32 IlbBase; // Intel Legacy Block Base Address.
|
||||
UINT32 PUnitBase; // PUnit Base Address.
|
||||
UINT32 Rcba; // Root Complex Base Address.
|
||||
UINT32 MphyBase; // MPHY Base Address.
|
||||
UINT16 AcpiBase; // ACPI I/O Base address.
|
||||
UINT16 GpioBase; // GPIO Base address
|
||||
PCH_HPET_CONFIG *HpetConfig;
|
||||
PCH_SATA_MODE SataMode;
|
||||
PCH_PCIE_CONFIG *PcieConfig;
|
||||
PCH_IOAPIC_CONFIG *IoApicConfig;
|
||||
PEI_PCH_LPSS_CONFIG *LpssConfig;
|
||||
BOOLEAN EnableRmh; // Determines if enable USB RMH function
|
||||
BOOLEAN EhciPllCfgEnable;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,75 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchUsbPolicy.h
|
||||
|
||||
@brief
|
||||
PCH Usb policy PPI produced by a platform driver specifying
|
||||
various expected PCH Usb settings. This PPI is consumed by the
|
||||
PCH PEI drivers.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_USB_POLICY_H_
|
||||
#define _PCH_USB_POLICY_H_
|
||||
|
||||
//
|
||||
// PCH Usb policy provided by platform for PEI phase
|
||||
//
|
||||
|
||||
#ifndef ECP_FLAG
|
||||
#include <PiPei.h>
|
||||
#endif
|
||||
|
||||
#include "PchRegs.h"
|
||||
#include <Protocol/PchPlatformPolicy.h>
|
||||
|
||||
#define PCH_USB_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0xc02b0573, 0x2b4e, 0x4a31, 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c \
|
||||
}
|
||||
|
||||
extern EFI_GUID gPchUsbPolicyPpiGuid;
|
||||
|
||||
typedef struct _PCH_USB_POLICY_PPI PCH_USB_POLICY_PPI;
|
||||
|
||||
///
|
||||
/// PPI revision number
|
||||
/// Any backwards compatible changes to this PPI will result in an update in the revision number
|
||||
/// Major changes will require publication of a new PPI
|
||||
///
|
||||
/// Revision 1: Original version
|
||||
///
|
||||
#define PCH_USB_POLICY_PPI_REVISION_1 1
|
||||
|
||||
///
|
||||
/// Generic definitions for device enabling/disabling used by PCH code.
|
||||
///
|
||||
#define PCH_DEVICE_ENABLE 1
|
||||
#define PCH_DEVICE_DISABLE 0
|
||||
|
||||
#define EHCI_MODE 1
|
||||
|
||||
struct _PCH_USB_POLICY_PPI {
|
||||
UINT8 Revision;
|
||||
PCH_USB_CONFIG *UsbConfig;
|
||||
UINT8 Mode;
|
||||
UINTN EhciMemBaseAddr;
|
||||
UINT32 EhciMemLength;
|
||||
UINTN XhciMemBaseAddr;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,236 @@
|
||||
/** @file
|
||||
Block IO protocol as defined in the UEFI 2.0 specification.
|
||||
|
||||
The Block IO protocol is used to abstract block devices like hard drives,
|
||||
DVD-ROMs and floppy drives.
|
||||
|
||||
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __PEI_BLOCK_IO_H__
|
||||
#define __PEI_BLOCK_IO_H__
|
||||
// {BC5FA650-EDBB-4d0d-B3A3-D98907F847DF}
|
||||
#ifndef ECP_FLAG
|
||||
#define PEI_BLOCK_IO_PPI_GUID \
|
||||
{ \
|
||||
0xbc5fa650, 0xedbb, 0x4d0d, { 0xb3, 0xa3, 0xd9, 0x89, 0x7, 0xf8, 0x47, 0xdf } \
|
||||
}
|
||||
#endif
|
||||
typedef struct _PEI_BLOCK_IO_PPI PEI_BLOCK_IO_PPI;
|
||||
|
||||
|
||||
/**
|
||||
Reset the Block Device.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
@param ExtendedVerification Driver may perform diagnostics on reset.
|
||||
|
||||
@retval EFI_SUCCESS The device was reset.
|
||||
@retval EFI_DEVICE_ERROR The device is not functioning properly and could
|
||||
not be reset.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_BLOCK_RESET)(
|
||||
IN PEI_BLOCK_IO_PPI *This,
|
||||
IN BOOLEAN ExtendedVerification
|
||||
);
|
||||
|
||||
/**
|
||||
Read BufferSize bytes from Lba into Buffer.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
@param MediaId Id of the media, changes every time the media is replaced.
|
||||
@param Lba The starting Logical Block Address to read from
|
||||
@param BufferSize Size of Buffer, must be a multiple of device block size.
|
||||
@param Buffer A pointer to the destination buffer for the data. The caller is
|
||||
responsible for either having implicit or explicit ownership of the buffer.
|
||||
|
||||
@retval EFI_SUCCESS The data was read correctly from the device.
|
||||
@retval EFI_DEVICE_ERROR The device reported an error while performing the read.
|
||||
@retval EFI_NO_MEDIA There is no media in the device.
|
||||
@retval EFI_MEDIA_CHANGED The MediaId does not matched the current device.
|
||||
@retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
|
||||
@retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
|
||||
or the buffer is not on proper alignment.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_BLOCK_READ)(
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_BLOCK_IO_PPI *This,
|
||||
IN UINT32 MediaId,
|
||||
IN EFI_LBA Lba,
|
||||
IN UINTN BufferSize,
|
||||
OUT VOID *Buffer
|
||||
);
|
||||
|
||||
/**
|
||||
Write BufferSize bytes from Lba into Buffer.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
@param MediaId The media ID that the write request is for.
|
||||
@param Lba The starting logical block address to be written. The caller is
|
||||
responsible for writing to only legitimate locations.
|
||||
@param BufferSize Size of Buffer, must be a multiple of device block size.
|
||||
@param Buffer A pointer to the source buffer for the data.
|
||||
|
||||
@retval EFI_SUCCESS The data was written correctly to the device.
|
||||
@retval EFI_WRITE_PROTECTED The device can not be written to.
|
||||
@retval EFI_DEVICE_ERROR The device reported an error while performing the write.
|
||||
@retval EFI_NO_MEDIA There is no media in the device.
|
||||
@retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
|
||||
@retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
|
||||
@retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
|
||||
or the buffer is not on proper alignment.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_BLOCK_WRITE)(
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_BLOCK_IO_PPI *This,
|
||||
IN UINT32 MediaId,
|
||||
IN EFI_LBA Lba,
|
||||
IN UINTN BufferSize,
|
||||
IN VOID *Buffer
|
||||
);
|
||||
|
||||
/**
|
||||
Flush the Block Device.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
|
||||
@retval EFI_SUCCESS All outstanding data was written to the device
|
||||
@retval EFI_DEVICE_ERROR The device reported an error while writting back the data
|
||||
@retval EFI_NO_MEDIA There is no media in the device.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_BLOCK_FLUSH)(
|
||||
IN PEI_BLOCK_IO_PPI *This
|
||||
);
|
||||
|
||||
/**
|
||||
Block IO read only mode data and updated only via members of BlockIO
|
||||
**/
|
||||
typedef struct {
|
||||
///
|
||||
/// The curent media Id. If the media changes, this value is changed.
|
||||
///
|
||||
UINT32 MediaId;
|
||||
|
||||
///
|
||||
/// TRUE if the media is removable; otherwise, FALSE.
|
||||
///
|
||||
BOOLEAN RemovableMedia;
|
||||
|
||||
///
|
||||
/// TRUE if there is a media currently present in the device;
|
||||
/// othersise, FALSE. THis field shows the media present status
|
||||
/// as of the most recent ReadBlocks() or WriteBlocks() call.
|
||||
///
|
||||
BOOLEAN MediaPresent;
|
||||
|
||||
///
|
||||
/// TRUE if LBA 0 is the first block of a partition; otherwise
|
||||
/// FALSE. For media with only one partition this would be TRUE.
|
||||
///
|
||||
BOOLEAN LogicalPartition;
|
||||
|
||||
///
|
||||
/// TRUE if the media is marked read-only otherwise, FALSE.
|
||||
/// This field shows the read-only status as of the most recent WriteBlocks () call.
|
||||
///
|
||||
BOOLEAN ReadOnly;
|
||||
|
||||
///
|
||||
/// TRUE if the WriteBlock () function caches write data.
|
||||
///
|
||||
BOOLEAN WriteCaching;
|
||||
|
||||
///
|
||||
/// The intrinsic block size of the device. If the media changes, then
|
||||
/// this field is updated.
|
||||
///
|
||||
UINT32 BlockSize;
|
||||
|
||||
///
|
||||
/// Supplies the alignment requirement for any buffer to read or write block(s).
|
||||
///
|
||||
UINT32 IoAlign;
|
||||
|
||||
///
|
||||
/// The last logical block address on the device.
|
||||
/// If the media changes, then this field is updated.
|
||||
///
|
||||
EFI_LBA LastBlock;
|
||||
|
||||
///
|
||||
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
|
||||
/// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to
|
||||
/// a physical block boundary.
|
||||
///
|
||||
EFI_LBA LowestAlignedLba;
|
||||
|
||||
///
|
||||
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
|
||||
/// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks
|
||||
/// per physical block.
|
||||
///
|
||||
UINT32 LogicalBlocksPerPhysicalBlock;
|
||||
|
||||
///
|
||||
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
|
||||
/// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length
|
||||
/// granularity as a number of logical blocks.
|
||||
///
|
||||
UINT32 OptimalTransferLengthGranularity;
|
||||
#ifdef ECP_FLAG
|
||||
} PEI_BLOCK_IO_MEDIA2;
|
||||
#else
|
||||
} PEI_BLOCK_IO_MEDIA;
|
||||
#endif
|
||||
#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000
|
||||
#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
|
||||
#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x00020031
|
||||
|
||||
///
|
||||
/// Revision defined in EFI1.1.
|
||||
///
|
||||
#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION
|
||||
|
||||
///
|
||||
/// This protocol provides control over block devices.
|
||||
///
|
||||
struct _PEI_BLOCK_IO_PPI {
|
||||
///
|
||||
/// The revision to which the block IO interface adheres. All future
|
||||
/// revisions must be backwards compatible. If a future version is not
|
||||
/// back wards compatible, it is not the same GUID.
|
||||
///
|
||||
UINT64 Revision;
|
||||
///
|
||||
/// Pointer to the EFI_BLOCK_IO_MEDIA data for this device.
|
||||
///
|
||||
PEI_BLOCK_IO_MEDIA *Media;
|
||||
PEI_BLOCK_RESET Reset;
|
||||
PEI_BLOCK_READ ReadBlocks;
|
||||
PEI_BLOCK_WRITE WriteBlocks;
|
||||
PEI_BLOCK_FLUSH FlushBlocks;
|
||||
};
|
||||
|
||||
//extern EFI_GUID gEfiBlockIoProtocolGuid;
|
||||
extern EFI_GUID gPeiBlockIoPpiGuid;
|
||||
#endif
|
||||
@@ -0,0 +1,365 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
Spi.h
|
||||
|
||||
@brief
|
||||
This file defines the EFI SPI PPI which implements the
|
||||
Intel(R) PCH SPI Host Controller Compatibility Interface.
|
||||
|
||||
**/
|
||||
#ifndef _PEI_SDHC_H_
|
||||
#define _PEI_SDHC_H_
|
||||
|
||||
|
||||
|
||||
//
|
||||
#define PEI_SDHC_PPI_GUID \
|
||||
{ \
|
||||
0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \
|
||||
}
|
||||
typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;
|
||||
|
||||
#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01
|
||||
|
||||
typedef enum {
|
||||
ResponseNo = 0,
|
||||
ResponseR1,
|
||||
ResponseR1b,
|
||||
ResponseR2,
|
||||
ResponseR3,
|
||||
ResponseR4,
|
||||
ResponseR5,
|
||||
ResponseR5b,
|
||||
ResponseR6,
|
||||
ResponseR7
|
||||
} RESPONSE_TYPE;
|
||||
|
||||
typedef enum {
|
||||
NoData = 0,
|
||||
InData,
|
||||
OutData
|
||||
} TRANSFER_TYPE;
|
||||
|
||||
typedef enum {
|
||||
Reset_Auto = 0,
|
||||
Reset_DAT,
|
||||
Reset_CMD,
|
||||
Reset_DAT_CMD,
|
||||
Reset_All
|
||||
} RESET_TYPE;
|
||||
|
||||
|
||||
|
||||
typedef enum {
|
||||
SDMA = 0,
|
||||
ADMA2,
|
||||
PIO
|
||||
} DMA_MOD;
|
||||
|
||||
typedef struct {
|
||||
UINT32 HighSpeedSupport: 1; //High speed supported
|
||||
UINT32 V18Support: 1; //1.8V supported
|
||||
UINT32 V30Support: 1; //3.0V supported
|
||||
UINT32 V33Support: 1; //3.3V supported
|
||||
UINT32 Reserved0: 4;
|
||||
UINT32 BusWidth4: 1; // 4 bit width
|
||||
UINT32 BusWidth8: 1; // 8 bit width
|
||||
UINT32 Reserved1: 6;
|
||||
UINT32 SDMASupport: 1;
|
||||
UINT32 ADMA2Support: 1;
|
||||
UINT32 DmaMode: 2;
|
||||
UINT32 Reserved2: 12;
|
||||
UINT32 BoundarySize;
|
||||
}HOST_CAPABILITY;
|
||||
|
||||
|
||||
#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
|
||||
#define PCI_IF_STANDARD_HOST_NO_DMA 0x00
|
||||
#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01
|
||||
|
||||
//
|
||||
//MMIO Registers definition for MMC/SDIO controller
|
||||
//
|
||||
#define MMIO_DMAADR 0x00
|
||||
#define MMIO_BLKSZ 0x04
|
||||
#define MMIO_BLKCNT 0x06
|
||||
#define MMIO_CMDARG 0x08
|
||||
#define MMIO_XFRMODE 0x0C
|
||||
#define MMIO_SDCMD 0x0E
|
||||
#define MMIO_RESP 0x10
|
||||
#define MMIO_BUFDATA 0x20
|
||||
#define MMIO_PSTATE 0x24
|
||||
#define MMIO_HOSTCTL 0x28
|
||||
#define MMIO_PWRCTL 0x29
|
||||
#define MMIO_BLKGAPCTL 0x2A
|
||||
#define MMIO_WAKECTL 0x2B
|
||||
#define MMIO_CLKCTL 0x2C
|
||||
#define MMIO_TOCTL 0x2E
|
||||
#define MMIO_SWRST 0x2F
|
||||
#define MMIO_NINTSTS 0x30
|
||||
#define MMIO_ERINTSTS 0x32
|
||||
#define MMIO_NINTEN 0x34
|
||||
#define MMIO_ERINTEN 0x36
|
||||
#define MMIO_NINTSIGEN 0x38
|
||||
#define MMIO_ERINTSIGEN 0x3A
|
||||
#define MMIO_AC12ERRSTS 0x3C
|
||||
#define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2
|
||||
#define MMIO_CAP 0x40
|
||||
#define MMIO_CAP2 0x44 //hphang <- New in VLV2
|
||||
#define MMIO_MCCAP 0x48
|
||||
#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2
|
||||
#define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2
|
||||
#define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2
|
||||
#define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2
|
||||
#define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2
|
||||
#define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2
|
||||
#define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2
|
||||
#define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2
|
||||
#define MMIO_SLTINTSTS 0xFC
|
||||
#define MMIO_CTRLRVER 0xFE
|
||||
#define MMIO_SRST 0x1FC
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT16 CommandIndex,
|
||||
IN UINT32 Argument,
|
||||
IN TRANSFER_TYPE DataType,
|
||||
IN UINT8 *Buffer, OPTIONAL
|
||||
IN UINT32 BufferSize,
|
||||
IN RESPONSE_TYPE ResponseType,
|
||||
IN UINT32 TimeOut,
|
||||
OUT UINT32 *ResponseData OPTIONAL
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set max clock frequency of the host, the actual frequency
|
||||
may not be the same as MaxFrequency. It depends on
|
||||
the max frequency the host can support, divider, and host
|
||||
speed mode.
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
MaxFrequency - Max frequency in HZ
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 MaxFrequency
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set bus width of the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
BusWidth - Bus width in 1, 4, 8 bits
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 BusWidth
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set Host mode in DDR
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
SetHostDdrMode - True for DDR Mode set, false for normal mode
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 DdrMode
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set voltage which could supported by the host.
|
||||
Support 0(Power off the host), 1.8V, 3.0V, 3.3V
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
Voltage - Units in 0.1 V
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 Voltage
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Reset the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
ResetAll - TRUE to reset all
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN RESET_TYPE ResetType
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Reset the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
Enable - TRUE to enable, FALSE to disable
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN BOOLEAN Enable
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Find whether these is a card inserted into the slot. If so
|
||||
init the host. If not, return EFI_NOT_FOUND.
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_NOT_FOUND
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set the Block length
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
BlockLength - card supportes block length
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 BlockLength
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set the Block length
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
BlockLength - card supportes block length
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
|
||||
typedef EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(
|
||||
IN PEI_SD_CONTROLLER_PPI *This
|
||||
);
|
||||
|
||||
//
|
||||
// Interface structure for the EFI SD Host I/O Protocol
|
||||
//
|
||||
struct _PEI_SD_CONTROLLER_PPI {
|
||||
UINT32 Revision;
|
||||
HOST_CAPABILITY HostCapability;
|
||||
EFI_SD_CONTROLLER_PPI_SEND_COMMAND SendCommand;
|
||||
EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY SetClockFrequency;
|
||||
EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH SetBusWidth;
|
||||
EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE SetHostVoltage;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode;
|
||||
EFI_SD_CONTROLLER_PPI_RESET_SD_HOST ResetSdHost;
|
||||
EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;
|
||||
EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;
|
||||
EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH SetBlockLength;
|
||||
EFI_SD_CONTROLLER_PPI_SETUP_DEVICE SetupDevice;
|
||||
};
|
||||
// Extern the GUID for PPI users.
|
||||
//
|
||||
extern EFI_GUID gPeiSdhcPpiGuid;
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
//
|
||||
//
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
SmbusPolicy.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Smbus Policy PPI as defined in EFI 2.0
|
||||
|
||||
--*/
|
||||
#ifndef _PEI_SMBUS_POLICY_PPI_H
|
||||
#define _PEI_SMBUS_POLICY_PPI_H
|
||||
|
||||
#define PEI_SMBUS_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0x63b6e435, 0x32bc, 0x49c6, 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c \
|
||||
}
|
||||
|
||||
typedef struct _PEI_SMBUS_POLICY_PPI PEI_SMBUS_POLICY_PPI;
|
||||
|
||||
typedef struct _PEI_SMBUS_POLICY_PPI {
|
||||
UINTN BaseAddress;
|
||||
UINT32 PciAddress;
|
||||
UINT8 NumRsvdAddress;
|
||||
UINT8 *RsvdAddress;
|
||||
} PEI_SMBUS_POLICY_PPI;
|
||||
|
||||
extern EFI_GUID gPeiSmbusPolicyPpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,48 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
Spi.h
|
||||
|
||||
@brief
|
||||
This file defines the EFI SPI PPI which implements the
|
||||
Intel(R) PCH SPI Host Controller Compatibility Interface.
|
||||
|
||||
**/
|
||||
#ifndef _PEI_SPI_H_
|
||||
#define _PEI_SPI_H_
|
||||
|
||||
|
||||
#include <Protocol/Spi.h>
|
||||
|
||||
|
||||
//
|
||||
#define PEI_SPI_PPI_GUID \
|
||||
{ \
|
||||
0xa38c6898, 0x2b5c, 0x4ff6, 0x93, 0x26, 0x2e, 0x63, 0x21, 0x2e, 0x56, 0xc2 \
|
||||
}
|
||||
// Extern the GUID for PPI users.
|
||||
//
|
||||
extern EFI_GUID gPeiSpiPpiGuid;
|
||||
|
||||
///
|
||||
/// Reuse the EFI_SPI_PROTOCOL definitions
|
||||
/// This is possible becaues the PPI implementation does not rely on a PeiService pointer,
|
||||
/// as it uses EDKII Glue Lib to do IO accesses
|
||||
///
|
||||
typedef EFI_SPI_PROTOCOL PEI_SPI_PPI;
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user