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Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

Browse Source 
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, 

which are for MinnowBoard MAX open source project.


Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
2015-01-12 09:37:20 +00:00
committed by zwei4
parent 6f785cfcc3
commit 3cbfba02fe
518 changed files with 118538 additions and 0 deletions
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109
Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
BiosIdLib.h
Abstract:
BIOS ID library definitions.
This library provides functions to get BIOS ID, VERSION, DATE and TIME
--*/
#ifndef _BIOS_ID_LIB_H_
#define _BIOS_ID_LIB_H_
//
// BIOS ID string format:
//
// $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE)$(VERSION_MINOR).YYMMDDHHMM
//
// Example: "TRFTCRB1.86C.0008.D03.0506081529"
//
#pragma pack(1)
typedef struct {
CHAR16 BoardId[7]; // "TRFTCRB"
CHAR16 BoardRev; // "1"
CHAR16 Dot1; // "."
CHAR16 OemId[3]; // "86C"
CHAR16 Dot2; // "."
CHAR16 VersionMajor[4]; // "0008"
CHAR16 Dot3; // "."
CHAR16 BuildType; // "D"
CHAR16 VersionMinor[2]; // "03"
CHAR16 Dot4; // "."
CHAR16 TimeStamp[10]; // "YYMMDDHHMM"
CHAR16 NullTerminator; // 0x0000
} BIOS_ID_STRING;
#define MEM_IFWIVER_START 0x7E0000
#define MEM_IFWIVER_LENGTH 0x1000
typedef struct _MANIFEST_OEM_DATA{
UINT32 Signature;
unsigned char FillNull[0x39];
UINT32 IFWIVersionLen;
unsigned char IFWIVersion[32];
}MANIFEST_OEM_DATA;
//
// A signature precedes the BIOS ID string in the FV to enable search by external tools.
//
typedef struct {
UINT8 Signature[8]; // "$IBIOSI$"
BIOS_ID_STRING BiosIdString; // "TRFTCRB1.86C.0008.D03.0506081529"
} BIOS_ID_IMAGE;
#pragma pack()
/**
This function returns BIOS ID by searching HOB or FV.
@param[in] BiosIdImage The BIOS ID got from HOB or FV
@retval EFI_SUCCESS All parameters were valid and BIOS ID has been got.
@retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified.
@retval EFI_INVALID_PARAMETER The parameter is NULL.
**/
EFI_STATUS
GetBiosId (
OUT BIOS_ID_IMAGE *BiosIdImage
);
/**
This function returns the Version & Release Date and Time by getting and converting
BIOS ID.
@param[in] BiosVersion The Bios Version out of the conversion.
@param[in] BiosReleaseDate The Bios Release Date out of the conversion.
@param[in] BiosReleaseTime The Bios Release Time out of the conversion.
@retval EFI_SUCCESS BIOS Version & Release Date and Time have been got successfully.
@retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified.
@retval EFI_INVALID_PARAMETER All the parameters are NULL.

350
Vlv2TbltDevicePkg/Include/Library/CpuIA32.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
CpuIA32.h
Abstract:
--*/
#ifndef _CPU_IA32_H
#define _CPU_IA32_H
typedef struct {
UINT32 RegEax;
UINT32 RegEbx;
UINT32 RegEcx;
UINT32 RegEdx;
} EFI_CPUID_REGISTER;
typedef struct {
UINT32 HeaderVersion;
UINT32 UpdateRevision;
UINT32 Date;
UINT32 ProcessorId;
UINT32 Checksum;
UINT32 LoaderRevision;
UINT32 ProcessorFlags;
UINT32 DataSize;
UINT32 TotalSize;
UINT8 Reserved[12];
} EFI_CPU_MICROCODE_HEADER;
typedef struct {
UINT32 ExtendedSignatureCount;
UINT32 ExtendedTableChecksum;
UINT8 Reserved[12];
} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
typedef struct {
UINT32 ProcessorSignature;
UINT32 ProcessorFlag;
UINT32 ProcessorChecksum;
} EFI_CPU_MICROCODE_EXTENDED_TABLE;
typedef struct {
UINT32 Stepping : 4;
UINT32 Model : 4;
UINT32 Family : 4;
UINT32 Type : 2;
UINT32 Reserved1 : 2;
UINT32 ExtendedModel : 4;
UINT32 ExtendedFamily : 8;
UINT32 Reserved2 : 4;
} EFI_CPU_VERSION;
#define EFI_CPUID_SIGNATURE 0x0
#define EFI_CPUID_VERSION_INFO 0x1
#define EFI_CPUID_CACHE_INFO 0x2
#define EFI_CPUID_SERIAL_NUMBER 0x3
#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
#define EFI_CPUID_BRAND_STRING1 0x80000002
#define EFI_CPUID_BRAND_STRING2 0x80000003
#define EFI_CPUID_BRAND_STRING3 0x80000004
#define EFI_MSR_IA32_PLATFORM_ID 0x17
#define EFI_MSR_IA32_APIC_BASE 0x1B
#define EFI_MSR_EBC_HARD_POWERON 0x2A
#define EFI_MSR_EBC_SOFT_POWERON 0x2B
#define BINIT_DRIVER_DISABLE 0x40
#define INTERNAL_MCERR_DISABLE 0x20
#define INITIATOR_MCERR_DISABLE 0x10
#define EFI_MSR_EBC_FREQUENCY_ID 0x2C
#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
#define EFI_MSR_PSB_CLOCK_STATUS 0xCD
#define EFI_APIC_GLOBAL_ENABLE 0x800
#define EFI_MSR_IA32_MISC_ENABLE 0x1A0
#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000
#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008
#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004
#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002
#define FAST_STRING_ENABLE_BIT 0x00000001
#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
#define EFI_CACHE_VARIABLE_MTRR_END 0x20F
#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
#define EFI_CACHE_MTRR_VALID 0x800
#define EFI_CACHE_FIXED_MTRR_VALID 0x400
#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
#define EFI_MSR_VALID_MASK 0xFFFFFFFFF
#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF
#define EFI_IA32_MTRR_FIX64K_00000 0x250
#define EFI_IA32_MTRR_FIX16K_80000 0x258
#define EFI_IA32_MTRR_FIX16K_A0000 0x259
#define EFI_IA32_MTRR_FIX4K_C0000 0x268
#define EFI_IA32_MTRR_FIX4K_C8000 0x269
#define EFI_IA32_MTRR_FIX4K_D0000 0x26A
#define EFI_IA32_MTRR_FIX4K_D8000 0x26B
#define EFI_IA32_MTRR_FIX4K_E0000 0x26C
#define EFI_IA32_MTRR_FIX4K_E8000 0x26D
#define EFI_IA32_MTRR_FIX4K_F0000 0x26E
#define EFI_IA32_MTRR_FIX4K_F8000 0x26F
#define EFI_IA32_MCG_CAP 0x179
#define EFI_IA32_MCG_CTL 0x17B
#define EFI_IA32_MC0_CTL 0x400
#define EFI_IA32_MC0_STATUS 0x401
#define EFI_IA32_PERF_STATUS 0x198
#define EFI_IA32_PERF_CTL 0x199
#define EFI_CACHE_UNCACHEABLE 0
#define EFI_CACHE_WRITECOMBINING 1
#define EFI_CACHE_WRITETHROUGH 4
#define EFI_CACHE_WRITEPROTECTED 5
#define EFI_CACHE_WRITEBACK 6
//
// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
//
#define EfiMakeCpuVersion(f, m, s) \
(((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
/**
Halt the Cpu
@param[in] None
@retval None
**/
VOID
EFIAPI
EfiHalt (
VOID
);
/**
Write back and invalidate the Cpu cache
@param[in] None
@retval None
**/
VOID
EFIAPI
EfiWbinvd (
VOID
);
/**
Invalidate the Cpu cache
@param[in] None
@retval None
**/
VOID
EFIAPI
EfiInvd (
VOID
);
/**
Get the Cpu info by excute the CPUID instruction
@param[in] RegisterInEax The input value to put into register EAX
@param[in] Regs The Output value
@retval None
**/
VOID
EFIAPI
EfiCpuid (
IN UINT32 RegisterInEax,
OUT EFI_CPUID_REGISTER *Regs
);
/**
When RegisterInEax != 4, the functionality is the same as EfiCpuid.
When RegisterInEax == 4, the function return the deterministic cache
parameters by excuting the CPUID instruction.
@param[in] RegisterInEax The input value to put into register EAX.
@param[in] CacheLevel The deterministic cache level.
@param[in] Regs The Output value.
@retval None
**/
VOID
EFIAPI
EfiCpuidExt (
IN UINT32 RegisterInEax,
IN UINT32 CacheLevel,
OUT EFI_CPUID_REGISTER *Regs
);
/**
Read Cpu MSR
@param[in] Index The index value to select the register
@retval Return the read data
**/
UINT64
EFIAPI
EfiReadMsr (
IN UINT32 Index
);
/**
Write Cpu MSR
@param[in] Index The index value to select the register
@param[in] Value The value to write to the selected register
@retval None
**/
VOID
EFIAPI
EfiWriteMsr (
IN UINT32 Index,
IN UINT64 Value
);
/**
Read Time stamp
@param[in] None
@retval Return the read data
**/
UINT64
EFIAPI
EfiReadTsc (
VOID
);
/**
Writing back and invalidate the cache,then diable it
@param[in] None
@retval None
**/
VOID
EFIAPI
EfiDisableCache (
VOID
);
/**
Invalidate the cache,then Enable it
@param[in] None
@retval None
**/
VOID
EFIAPI
EfiEnableCache (
VOID
);
/**
Get Eflags
@param[in] None
@retval Return the Eflags value
**/
UINT32
EFIAPI
EfiGetEflags (
VOID
);
/**
Disable Interrupts
@param[in] None
@retval None
**/
VOID
EFIAPI
EfiDisableInterrupts (
VOID
);
/**
Enable Interrupts
@param[in] None
@retval None
**/
VOID
EFIAPI
EfiEnableInterrupts (
VOID
);
/**
Extract CPU detail version infomation
@param[in] FamilyId FamilyId, including ExtendedFamilyId
@param[in] Model Model, including ExtendedModel
@param[in] SteppingId SteppingId
@param[in] Processor Processor
**/
VOID

201
Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
EfiRegTableLib.h
Abstract:
Definitions and macros for building register tables for chipset
initialization..
Components linking this lib must include CpuIo, PciRootBridgeIo, and
BootScriptSave protocols in their DPX.
--*/
#ifndef EFI_REG_TABLE_H
#define EFI_REG_TABLE_H
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Protocol/CpuIo.h>
#include <Protocol/BootScriptSave.h>
#include <Framework/BootScript.h>
#include <Protocol/PciRootBridgeIo.h>
#define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF))
#define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF))
#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))
//
// RegTable Base OpCodes
//
#define OP_TERMINATE_TABLE 0
#define OP_MEM_WRITE 1
#define OP_MEM_READ_MODIFY_WRITE 2
#define OP_IO_WRITE 3
#define OP_IO_READ_MODIFY_WRITE 4
#define OP_PCI_WRITE 5
#define OP_PCI_READ_MODIFY_WRITE 6
#define OP_STALL 7
//
// RegTable OpCode Flags
//
#define OPCODE_FLAG_S3SAVE 1
#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }
//
// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode
// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values
//
typedef struct {
UINT32 OpCode;
UINT32 PciAddress;
UINT32 Data;
} EFI_REG_TABLE_PCI_WRITE;
#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \
{ \
(UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
(UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
(UINT32) (Data), \
(UINT32) (0) \
}
typedef struct {
UINT32 OpCode;
UINT32 MemAddress;
UINT32 Data;
} EFI_REG_TABLE_MEM_WRITE;
typedef struct {
UINT32 OpCode;
UINT32 PciAddress;
UINT32 OrMask;
UINT32 AndMask;
} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;
#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \
{ \
(UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
(UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
(UINT32) (OrMask), \
(UINT32) (AndMask) \
}
typedef struct {
UINT32 OpCode;
UINT32 MemAddress;
UINT32 OrMask;
UINT32 AndMask;
} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;
#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag) \
{ \
(UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
(UINT32) (Address), \
(UINT32) (OrMask), \
(UINT32) (AndMask) \
}
typedef struct {
UINT32 OpCode;
UINT32 Field2;
UINT32 Field3;
UINT32 Field4;
} EFI_REG_TABLE_GENERIC;
typedef union {
EFI_REG_TABLE_GENERIC Generic;
EFI_REG_TABLE_PCI_WRITE PciWrite;
EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite;
EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite;
} EFI_REG_TABLE;
/**
Processes register table assuming which may contain PCI, IO, MEM, and STALL
entries.
No parameter checking is done so the caller must be careful about omitting
values for PciRootBridgeIo or CpuIo parameters. If the regtable does
not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
NULL). If the regtable does not contain any IO or Mem entries, it is safe to
omit the CpuIo (supply NULL).
The RegTableEntry parameter is not checked, but is required.
gBS is assumed to have been defined and is used when processing stalls.
The function processes each entry sequentially until an OP_TERMINATE_TABLE
entry is encountered.
@param[in] RegTableEntry A pointer to the register table to process
@param[in] PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
when processing PCI table entries
@param[in] CpuIo A pointer to the instance of CpuIo that is used when processing IO and
MEM table entries
@retval Nothing.
**/
VOID
ProcessRegTablePci (
EFI_REG_TABLE * RegTableEntry,
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,
EFI_CPU_IO_PROTOCOL * CpuIo
);
/**
Processes register table assuming which may contain IO, MEM, and STALL
entries, but must NOT contain any PCI entries. Any PCI entries cause an
ASSERT in a DEBUG build and are skipped in a free build.
No parameter checking is done. Both RegTableEntry and CpuIo parameters are
required.
gBS is assumed to have been defined and is used when processing stalls.
The function processes each entry sequentially until an OP_TERMINATE_TABLE
entry is encountered.
@param[in] RegTableEntry - A pointer to the register table to process
@param[in] CpuIo - A pointer to the instance of CpuIo that is used when processing IO and
MEM table entries
@retval Nothing.

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Vlv2TbltDevicePkg/Include/Library/Esrt.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
Esrt.h
Abstract:
--*/
#ifndef _DFU_ESRT_H_
#define _DFU_ESRT_H_
typedef struct {
EFI_GUID FwClass;
UINT32 FwType;
UINT32 FwVersion;
UINT32 FwLstCompatVersion;
UINT32 CapsuleFlags;
UINT32 LastAttemptVersion;
UINT32 LastAttemptStatus;
} FW_RES_ENTRY;
typedef struct {
UINT32 NumEntries;
FW_RES_ENTRY FwEntries[256];
} FW_RES_ENTRY_LIST;
typedef struct {
UINT32 FwResourceCount;
UINT32 FwResourceMax;
UINT64 FwResourceVersion;
} EFI_SYSTEM_RESOURCE_TABLE;
typedef
EFI_STATUS
(EFIAPI *ESRT_POPULATE_TABLE) (
);
typedef
EFI_STATUS
(EFIAPI *ESRT_UPDATE_TABLE_ENTRY_BY_GUID) (
IN EFI_GUID FwEntryGuid,
IN FW_RES_ENTRY *FwEntry
);
typedef
EFI_STATUS
(EFIAPI *ESRT_GET_FW_ENTRY_BY_GUID) (
IN EFI_GUID FwEntryGuid,
OUT FW_RES_ENTRY *FwEntry
);
#pragma pack()

269
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
Fd.h
Abstract:
EFI Intel82802AB/82802AC Firmware Hub.
--*/
//
// Supported SPI devices
//
//
// MFG and Device code
//
#define SST_25LF040A 0x0044BF
#define SST_25LF040 0x0040BF
#define SST_25LF080A 0x0080BF
#define SST_25VF080B 0x008EBF
#define SST_25VF016B 0x0041BF
#define SST_25VF032B 0x004ABF
#define PMC_25LV040 0x007E9D
#define ATMEL_26DF041 0x00441F
#define Atmel_AT26F004 0x00041F
#define Atmel_AT26DF081A 0x01451F
#define Atmel_AT25DF161 0x02461F
#define Atmel_AT26DF161 0x00461F
#define Atmel_AT25DF641 0x00481F
#define Atmel_AT26DF321 0x00471F
#define Macronix_MX25L8005 0x1420C2
#define Macronix_MX25L1605A 0x1520C2
#define Macronix_MX25L3205D 0x1620C2
#define STMicro_M25PE80 0x148020
#define Winbond_W25X40 0x1330EF
#define Winbond_W25X80 0x1430EF
#define Winbond_W25Q80 0x1440EF
#define Winbond_W25X16 0x1540EF // W25Q16
#define Winbond_W25X32 0x1630EF
//
// NOTE: Assuming that 8Mbit flash will only contain a 4Mbit binary.
// Treating 4Mbit and 8Mbit devices the same.
//
//
// BIOS Base Address
//
#define BIOS_BASE_ADDRESS_4M 0xFFF80000
#define BIOS_BASE_ADDRESS_8M 0xFFF00000
#define BIOS_BASE_ADDRESS_16M 0xFFE00000
//
// block and sector sizes
//
#define SECTOR_SIZE_256BYTE 0x100 // 256byte page size
#define SECTOR_SIZE_4KB 0x1000 // 4kBytes sector size
#define BLOCK_SIZE_32KB 0x00008000 // 32Kbytes block size
#define MAX_FLASH_SIZE 0x00400000 // 32Mbit (Note that this can also be used for the 4Mbit & 8Mbit)
//
// Flash commands
//
#define SPI_SST25LF_COMMAND_WRITE 0x02
#define SPI_SST25LF_COMMAND_READ 0x03
#define SPI_SST25LF_COMMAND_ERASE 0x20
#define SPI_SST25LF_COMMAND_WRITE_DISABLE 0x04
#define SPI_SST25LF_COMMAND_READ_STATUS 0x05
#define SPI_SST25LF_COMMAND_WRITE_ENABLE 0x06
#define SPI_SST25LF_COMMAND_READ_ID 0xAB
#define SPI_SST25LF_COMMAND_WRITE_S_EN 0x50
#define SPI_SST25LF_COMMAND_WRITE_S 0x01
#define SPI_PMC25LV_COMMAND_WRITE 0x02
#define SPI_PMC25LV_COMMAND_READ 0x03
#define SPI_PMC25LV_COMMAND_ERASE 0xD7
#define SPI_PMC25LV_COMMAND_WRITE_DISABLE 0x04
#define SPI_PMC25LV_COMMAND_READ_STATUS 0x05
#define SPI_PMC25LV_COMMAND_WRITE_ENABLE 0x06
#define SPI_PMC25LV_COMMAND_READ_ID 0xAB
#define SPI_PMC25LV_COMMAND_WRITE_S_EN 0x06
#define SPI_PMC25LV_COMMAND_WRITE_S 0x01
#define SPI_AT26DF_COMMAND_WRITE 0x02
#define SPI_AT26DF_COMMAND_READ 0x03
#define SPI_AT26DF_COMMAND_ERASE 0x20
#define SPI_AT26DF_COMMAND_WRITE_DISABLE 0x00
#define SPI_AT26DF_COMMAND_READ_STATUS 0x05
#define SPI_AT26DF_COMMAND_WRITE_ENABLE 0x00
#define SPI_AT26DF_COMMAND_READ_ID 0x9F
#define SPI_AT26DF_COMMAND_WRITE_S_EN 0x00
#define SPI_AT26DF_COMMAND_WRITE_S 0x00
#define SPI_AT26F_COMMAND_WRITE 0x02
#define SPI_AT26F_COMMAND_READ 0x03
#define SPI_AT26F_COMMAND_ERASE 0x20
#define SPI_AT26F_COMMAND_WRITE_DISABLE 0x04
#define SPI_AT26F_COMMAND_READ_STATUS 0x05
#define SPI_AT26F_COMMAND_WRITE_ENABLE 0x06
#define SPI_AT26F_COMMAND_JEDEC_ID 0x9F
#define SPI_AT26F_COMMAND_WRITE_S_EN 0x00
#define SPI_AT26F_COMMAND_WRITE_S 0x01
#define SPI_AT26F_COMMAND_WRITE_UNPROTECT 0x39
#define SPI_SST25VF_COMMAND_WRITE 0x02
#define SPI_SST25VF_COMMAND_READ 0x03
#define SPI_SST25VF_COMMAND_ERASE 0x20
#define SPI_SST25VF_COMMAND_WRITE_DISABLE 0x04
#define SPI_SST25VF_COMMAND_READ_STATUS 0x05
#define SPI_SST25VF_COMMAND_WRITE_ENABLE 0x06
#define SPI_SST25VF_COMMAND_READ_ID 0xAB
#define SPI_SST25VF_COMMAND_JEDEC_ID 0x9F
#define SPI_SST25VF_COMMAND_WRITE_S_EN 0x50
#define SPI_SST25VF_COMMAND_WRITE_S 0x01
#define SPI_STM25PE_COMMAND_WRITE 0x02
#define SPI_STM25PE_COMMAND_READ 0x03
#define SPI_STM25PE_COMMAND_ERASE 0xDB
#define SPI_STM25PE_COMMAND_WRITE_DISABLE 0x04
#define SPI_STM25PE_COMMAND_READ_STATUS 0x05
#define SPI_STM25PE_COMMAND_WRITE_ENABLE 0x06
#define SPI_STM25PE_COMMAND_JEDEC_ID 0x9F
#define SPI_WinbondW25X_COMMAND_WRITE_S 0x01
#define SPI_WinbondW25X_COMMAND_WRITE 0x02
#define SPI_WinbondW25X_COMMAND_READ 0x03
#define SPI_WinbondW25X_COMMAND_READ_STATUS 0x05
#define SPI_WinbondW25X_COMMAND_ERASE_S 0x20
#define SPI_WinbondW25X_COMMAND_WRITE_ENABLE 0x06
#define SPI_WinbondW25X_COMMAND_JEDEC_ID 0x9F
//
// SPI default opcode slots
//
#define SPI_OPCODE_WRITE_INDEX 0
#define SPI_OPCODE_READ_INDEX 1
#define SPI_OPCODE_ERASE_INDEX 2
#define SPI_OPCODE_READ_S_INDEX 3
#define SPI_OPCODE_READ_ID_INDEX 4
#define SPI_OPCODE_WRITE_S_INDEX 6
#define SPI_OPCODE_WRITE_UNPROTECT_INDEX 7
#define SPI_PREFIX_WRITE_S_EN 1
#define SPI_PREFIX_WRITE_EN 0
//
// Atmel AT26F00x
//
#define B_AT26F_STS_REG_SPRL 0x80
#define B_AT26F_STS_REG_SWP 0x0C
//
// Block lock bit definitions:
//
#define READ_LOCK 0x04
#define LOCK_DOWN 0x02
#define WRITE_LOCK 0x01
#define FULL_ACCESS 0x00
//
// Function Prototypes
//
EFI_STATUS
FlashGetNextBlock (
IN UINTN* Key,
OUT EFI_PHYSICAL_ADDRESS* BlockAddress,
OUT UINTN* BlockSize
);
EFI_STATUS
FlashGetSize (
OUT UINTN* Size
);
EFI_STATUS
FlashGetUniformBlockSize (
OUT UINTN* Size
);
EFI_STATUS
FlashEraseWithNoTopSwapping (
IN UINT8 *BaseAddress,
IN UINTN NumBytes
);
EFI_STATUS
FlashErase (
IN UINT8 *BaseAddress,
IN UINTN NumBytes
);
EFI_STATUS
FlashWriteWithNoTopSwapping (
IN UINT8* DstBufferPtr,
IN UINT8* SrcBufferPtr,
IN UINTN NumBytes
);
EFI_STATUS
FlashWrite (
IN UINT8 *DstBufferPtr,
IN UINT8 *SrcBufferPtr,
IN UINTN NumBytes
);
EFI_STATUS
FlashReadWithNoTopSwapping (
IN UINT8 *BaseAddress,
IN UINT8 *DstBufferPtr,
IN UINTN NumBytes
);
EFI_STATUS
FlashRead (
IN UINT8 *BaseAddress,
IN UINT8 *DstBufferPtr,
IN UINTN NumBytes
);
EFI_STATUS
FlashLockWithNoTopSwapping (
IN UINT8* BaseAddress,
IN UINTN NumBytes,
IN UINT8 LockState
);
EFI_STATUS
FlashLock(
IN UINT8 *BaseAddress,
IN UINTN NumBytes,
IN UINT8 LockState
);
EFI_STATUS
CheckIfErased(
IN UINT8 *DstBufferPtr,

127
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Flash device library class header file.
Flash Device Library common type, MACRO and API definition. The basic idea for
this library is to provide API to abstract the different between flash
technology (SPI, FWH etc..), flash controller (SPI host controller on
ICH, MMIO type access for FWH), flash chip (programming command, method
of status checking). This library class can be consumed by drivers or applications
such as Firmware Volume Block driver, Flash Update application. These driver
can be written in a generic manner so that they are more easy to be
ported to other platforms.
This library can be build on a set of APIs which can touch flash controller, flash
chip directly for a platform with simple flash device configuration.
For a platform with complex flash device configuration, this library can be built
on the Flash Device Operate Library. Please see the header file for that library
class for detailed usage.
**/
#ifndef __FLASHDEVICE_LIB_H__
#define __FLASHDEVICE_LIB_H__
/**
Read NumBytes bytes of data from the address specified by
PAddress into Buffer.
@param[in] PAddress The starting physical address of the read.
@param[in,out] NumBytes On input, the number of bytes to read. On output, the number
of bytes actually read.
@param[out] Buffer The destination data buffer for the read.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceRead (
IN UINTN PAddress,
IN OUT UINTN *NumBytes,
OUT UINT8 *Buffer
);
/**
Write NumBytes bytes of data from Buffer to the address specified by
PAddresss.
@param[in] PAddress The starting physical address of the write.
@param[in,out] NumBytes On input, the number of bytes to write. On output,
the actual number of bytes written.
@param[in] Buffer The source data buffer for the write.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceWrite (
IN UINTN PAddress,
IN OUT UINTN *NumBytes,
IN UINT8 *Buffer
);
/**
Erase the block staring at PAddress.
@param[in] PAddress The starting physical address of the region to be erased.
@param[in] LbaLength The length of the region to be erased. This parameter is necessary
as the physical block size on a flash device could be different than
the logical block size of Firmware Volume Block protocol. Erase on
flash chip is always performed block by block. Therefore, the ERASE
operation to a logical block is converted a number of ERASE operation
(or a partial erase) on the hardware.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceBlockErase (
IN UINTN PAddress,
IN UINTN LbaLength
);
/**
Lock or unlock the block staring at PAddress.
@param[in] PAddress The starting physical address of region to be (un)locked.
@param[in] LbaLength The length of the region to be (un)locked. This parameter is necessary
as the physical block size on a flash device could be different than
the logical block size of Firmware Volume Block protocol. (Un)Lock on
flash chip is always performed block by block. Therefore, the (Un)Lock
operation to a logical block is converted a number of (Un)Lock operation
(or a partial erase) on the hardware.
@param[in] Lock TRUE to lock. FALSE to unlock.
@retval EFI_SUCCESS. Opertion is successful.
**/
EFI_STATUS
EFIAPI

28
Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __MMIO_CONFIG_LIB_H__
#define __MMIO_CONFIG_LIB_H__
#include <Protocol/MmioDevice.h>

31
Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _I2C_PORT_H
#define _I2C_PORT_H
//
// Types
//

55
Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
--*/
#ifndef _FSA_LIB_H
#define _FSA_LIB_H
#include <Uefi.h>
#include <Uefi/UefiSpec.h>
#define FSA_REG_DEVID 0x1
#define FSA_REG_CTRL 0x2
#define FSA_REG_INTR 0x3
#define FSA_REG_INTR_MSK 0x5
#define FSA_REG_RESISTOR_CODE 0x7
#define FSA_REG_TIMING_SET 0x8
#define FSA_REG_STATUS 0x9
#define FSA_REG_DEV_TYPE 0xA
#define FSA_REG_DAC_SAR 0xB
#define FSA_REG_MANUAL_SW 0x13
#define FSA_REG_MANUAL_CHG_CTRL 0x14
extern
EFI_STATUS
EFIAPI
FsaUsbDeviceMode (
VOID
);
extern
EFI_STATUS
EFIAPI
DisableFsaTimerHandler (
VOID
);

28
Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
--*/
#ifndef _PLATFORM_FSP_LIB_H
#define _PLATFORM_FSP_LIB_H
#include <Base.h>
#include <Uefi.h>

244
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SPIFlash_H_
#define _SPIFlash_H_
#include <Protocol/Spi.h>
//EFI_STATUS SpiFlashLock(BOOLEAN Lock);
//EFI_STATUS SpiFlashInit(void);
typedef enum {
EnumSpiFlashW25Q64,
EnumSpiFlashAT25DF321A,
EnumSpiFlashAT26DF321,
EnumSpiFlashAT25DF641,
EnumSpiFlashW25Q16,
EnumSpiFlashW25Q32,
EnumSpiFlashW25X32,
EnumSpiFlashW25X64,
EnumSpiFlashW25Q128,
EnumSpiFlashMX25L16,
EnumSpiFlashMX25L32,
EnumSpiFlashMX25L64,
EnumSpiFlashMX25L128,
EnumSpiFlashMX25U6435F,
EnumSpiFlashSST25VF016B,
EnumSpiFlashSST25VF064C,
EnumSpiFlashN25Q064,
EnumSpiFlashM25PX16,
EnumSpiFlashN25Q032,
EnumSpiFlashM25PX32,
EnumSpiFlashM25PX64,
EnumSpiFlashN25Q128,
EnumSpiFlashEN25Q16,
EnumSpiFlashEN25Q32,
EnumSpiFlashEN25Q64,
EnumSpiFlashEN25Q128,
EnumSpiFlashA25L016,
EnumSpiFlashMax
} SPI_FLASH_TYPES_SUPPORTED;
//
// Serial Flash VendorId and DeviceId
//
#define SF_VENDOR_ID_ATMEL 0x1F
#define SF_DEVICE_ID0_AT26DF321 0x47
#define SF_DEVICE_ID1_AT26DF321 0x00
#define SF_DEVICE_ID0_AT25DF321A 0x47
#define SF_DEVICE_ID1_AT25DF321A 0x01
#define SF_DEVICE_ID0_AT25DF641 0x48
#define SF_DEVICE_ID1_AT25DF641 0x00
#define SF_VENDOR_ID_WINBOND 0xEF
#define SF_DEVICE_ID0_W25XXX 0x30
#define SF_DEVICE_ID1_W25X32 0x16
#define SF_DEVICE_ID1_W25X64 0x17
#define SF_DEVICE_ID0_W25QXX 0x60
#define SF_DEVICE_ID1_W25Q16 0x15
#define SF_DEVICE_ID1_W25Q32 0x16
#define SF_DEVICE_ID1_W25Q64 0x17
#define SF_DEVICE_ID1_W25Q128 0x18
#define SF_VENDOR_ID_MACRONIX 0xC2
#define SF_DEVICE_ID0_MX25LXX 0x20
#define SF_DEVICE_ID1_MX25L16 0x15
#define SF_DEVICE_ID1_MX25L32 0x16
#define SF_DEVICE_ID1_MX25L64 0x17
#define SF_DEVICE_ID1_MX25L128 0x18
#define SF_DEVICE_ID0_MX25UXX 0x25
#define SF_DEVICE_ID1_MX25U6435F 0x37
#define SF_VENDOR_ID_NUMONYX 0x20
#define SF_DEVICE_ID0_N25Q064 0xBB
#define SF_DEVICE_ID1_N25Q064 0x17
#define SF_DEVICE_ID0_M25PXXX 0x71
#define SF_DEVICE_ID0_N25QXXX 0xBA
#define SF_DEVICE_ID1_M25PX16 0x15
#define SF_DEVICE_ID1_N25Q032 0x16
#define SF_DEVICE_ID1_M25PX32 0x16
#define SF_DEVICE_ID1_M25PX64 0x17
#define SF_DEVICE_ID1_N25Q128 0x18
#define SF_VENDOR_ID_SST 0xBF
#define SF_DEVICE_ID0_SST25VF0XXX 0x25
#define SF_DEVICE_ID1_SST25VF016B 0x41
#define SF_DEVICE_ID1_SST25VF064C 0x4B
#define SF_VENDOR_ID_EON 0x1C
#define SF_DEVICE_ID0_EN25QXX 0x30
#define SF_DEVICE_ID1_EN25Q16 0x15
#define SF_DEVICE_ID1_EN25Q32 0x16
#define SF_DEVICE_ID1_EN25Q64 0x17
#define SF_DEVICE_ID1_EN25Q128 0x18
#define SF_VENDOR_ID_AMIC 0x37
#define SF_DEVICE_ID0_A25L016 0x30
#define SF_DEVICE_ID1_A25L016 0x15
#define ATMEL_AT26DF321_SIZE 0x00400000
#define ATMEL_AT25DF321A_SIZE 0x00400000
#define ATMEL_AT25DF641_SIZE 0x00800000
#define WINBOND_W25X32_SIZE 0x00400000
#define WINBOND_W25X64_SIZE 0x00800000
#define WINBOND_W25Q16_SIZE 0x00200000
#define WINBOND_W25Q32_SIZE 0x00400000
#define WINBOND_W25Q64_SIZE 0x00800000
#define WINBOND_W25Q128_SIZE 0x01000000
#define SST_SST25VF016B_SIZE 0x00200000
#define SST_SST25VF064C_SIZE 0x00800000
#define MACRONIX_MX25L16_SIZE 0x00200000
#define MACRONIX_MX25L32_SIZE 0x00400000
#define MACRONIX_MX25L64_SIZE 0x00800000
#define MACRONIX_MX25U64_SIZE 0x00800000
#define MACRONIX_MX25L128_SIZE 0x01000000
#define NUMONYX_M25PX16_SIZE 0x00400000
#define NUMONYX_N25Q032_SIZE 0x00400000
#define NUMONYX_M25PX32_SIZE 0x00400000
#define NUMONYX_M25PX64_SIZE 0x00800000
#define NUMONYX_N25Q064_SIZE 0x00800000
#define NUMONYX_N25Q128_SIZE 0x01000000
#define EON_EN25Q16_SIZE 0x00200000
#define EON_EN25Q32_SIZE 0x00400000
#define EON_EN25Q64_SIZE 0x00800000
#define EON_EN25Q128_SIZE 0x01000000
#define AMIC_A25L16_SIZE 0x00200000
#define SF_VENDOR_ID_SST 0xBF
#define SF_DEVICE_ID0_25LF080A 0x25
#define SF_DEVICE_ID1_25LF080A 0x8E
#define SF_DEVICE_ID0_25VF016B 0x25
#define SF_DEVICE_ID1_25VF016B 0x41
#define SF_VENDOR_ID_ATMEL 0x1F
#define SF_DEVICE_ID0_AT26DF321 0x47
#define SF_DEVICE_ID1_AT26DF321 0x00
#define SF_VENDOR_ID_STM 0x20
#define SF_DEVICE_ID0_M25P32 0x20
#define SF_DEVICE_ID1_M25P32 0x16
#define SF_VENDOR_ID_WINBOND 0xEF
#define SF_DEVICE_ID0_W25XXX 0x30
#define SF_DEVICE_ID0_W25QXX 0x60
#define SF_DEVICE_ID1_W25X80 0x14
#define SF_DEVICE_ID1_W25X16 0x15
#define SF_DEVICE_ID1_W25X32 0x16
#define SF_DEVICE_ID1_W25X64 0x17
#define SF_VENDOR_ID_MX 0xC2
#define SF_DEVICE_ID0_25L1605A 0x20
#define SF_DEVICE_ID1_25L1605A 0x15
#define SF_VENDOR_ID_NUMONYX 0x20
#define SF_DEVICE_ID0_M25PX16 0x71
#define SF_DEVICE_ID1_M25PX16 0x15
#define SST_25LF080A_SIZE 0x00100000
#define SST_25LF016B_SIZE 0x00200000
#define ATMEL_AT26DF321_SIZE 0x00400000
#define STM_M25P32_SIZE 0x00400000
#define WINBOND_W25X80_SIZE 0x00100000
#define WINBOND_W25X16_SIZE 0x00200000
#define WINBOND_W25X32_SIZE 0x00400000
#define WINBOND_W25X64_SIZE 0x00800000
#define MX_25L1605A_SIZE 0x00200000
//
// Physical Sector Size on the Serial Flash device
//
#define SF_SECTOR_SIZE 0x1000
#define SF_BLOCK_SIZE 0x8000
//
// Serial Flash Status Register definitions
//
#define SF_SR_BUSY 0x01 // Indicates if internal write operation is in progress
#define SF_SR_WEL 0x02 // Indicates if device is memory write enabled
#define SF_SR_BP0 0x04 // Block protection bit 0
#define SF_SR_BP1 0x08 // Block protection bit 1
#define SF_SR_BP2 0x10 // Block protection bit 2
#define SF_SR_BP3 0x20 // Block protection bit 3
#define SF_SR_WPE 0x3C // Enable write protection on all blocks
#define SF_SR_AAI 0x40 // Auto Address Increment Programming status
#define SF_SR_BPL 0x80 // Block protection lock-down
//
// Operation Instruction definitions for the Serial Flash Device
//
#define SF_INST_WRSR 0x01 // Write Status Register
#define SF_INST_PROG 0x02 // Byte Program
#define SF_INST_READ 0x03 // Read
#define SF_INST_WRDI 0x04 // Write Disable
#define SF_INST_RDSR 0x05 // Read Status Register
#define SF_INST_WREN 0x06 // Write Enable
#define SF_INST_HS_READ 0x0B // High-speed Read
#define SF_INST_SERASE 0x20 // Sector Erase (4KB)
#define SF_INST_BERASE 0x52 // Block Erase (32KB)
#define SF_INST_64KB_ERASE 0xD8 // Block Erase (64KB)
#define SF_INST_EWSR 0x50 // Enable Write Status Register
#define SF_INST_READ_ID 0xAB // Read ID
#define SF_INST_JEDEC_READ_ID 0x9F // JEDEC Read ID
#define SF_INST_DOFR 0x3B // Dual Output Fast Read
#define SF_INST_SFDP 0x5A // Serial Flash Discovery Parameters
#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
#define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size
#define BLOCK_SIZE_64KB 0x00010000 // Common 64kBytes block size
#define MAX_FWH_SIZE 0x00100000 // 8Mbit (Note that this can also be used for the 4Mbit )
//
// Prefix Opcode Index on the host SPI controller
//
typedef enum {
SPI_WREN, // Prefix Opcode 0: Write Enable
SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register
} PREFIX_OPCODE_INDEX;
//
// Opcode Menu Index on the host SPI controller
//
typedef enum {
SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address
SPI_READ, // Opcode 1: READ, Read cycle with address

45
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/*++
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
SmmStallLib.h
Abstract:
This library provides SMM functions for Stall.
These can be used to save size and simplify code.
All contents must be runtime and SMM safe.
--*/
#ifndef _SMM_STALL_LIB_H_
#define _SMM_STALL_LIB_H_
#include "PiDxe.h"
#include "Pi/PiSmmCis.h"
extern EFI_SMM_SYSTEM_TABLE2 *mSmst;
/**
Delay for at least the request number of microseconds
@param[in] Microseconds Number of microseconds to delay.

186
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __BASE_USBDEVICEMODE_LIB_H__
#define __BASE_USBDEVICEMODE_LIB_H__
#pragma pack(1)
typedef struct {
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bMaxBurst;
UINT8 bmAttributes;
UINT16 wBytesPerInterval;
} endpointCompanionDescriptor;
#pragma pack()
#pragma pack(1)
typedef struct {
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bEndpointAddress;
UINT8 bmAttributes;
UINT16 wMaxPacketSize;
UINT8 bInterval;
} endpointDescriptor;
#pragma pack()
typedef struct {
endpointDescriptor *pEpDesc;
endpointCompanionDescriptor *pEpCompDesc;
} USB_DEV_EP_INFO; //usbdEpInfo;
typedef struct {
VOID *pBuf;
UINT32 dataLen;
} USBD_IO_INFO;
typedef struct {
USBD_IO_INFO ioInfo;
USB_DEV_EP_INFO epInfo;
} USBD_IO_REQ;
UINTN
EFIAPI
usbdInitDCI (
VOID
);
BOOLEAN
EFIAPI
fbInit (
OUT VOID *pParams
);
BOOLEAN
EFIAPI
fbDeinit (
VOID
);
BOOLEAN
EFIAPI
fbStart (
VOID
);
BOOLEAN
EFIAPI
fbStop (
VOID
);
BOOLEAN
EFIAPI
usbdSetMmioBar (
UINT32 mmioBar
);
BOOLEAN
EFIAPI
udciDeinit (
VOID *pUdciHndl,
UINT32 flags
);
BOOLEAN
EFIAPI
udciIsr (
VOID *pUdciHndl
);
BOOLEAN
EFIAPI
udciConnect (
VOID *pUdciHndl
);
BOOLEAN
EFIAPI
udciDisconnect (
VOID *pUdciHndl
);
BOOLEAN
EFIAPI
udciSetAddress (
VOID *pUdciHndl,
UINT8 address
);
BOOLEAN
EFIAPI
udciInitEp (
VOID *pUdciHndl,
USB_DEV_EP_INFO *pEpInfo
);
BOOLEAN
EFIAPI
udciEnableEp (
VOID *pUdciHndl,
USB_DEV_EP_INFO *pEpInfo
);
BOOLEAN
EFIAPI
udciDisableEp (
VOID *pUdciHndl,
USB_DEV_EP_INFO *pEpInfo
);
BOOLEAN
EFIAPI
udciStallEp (
VOID *pUdciHndl,
USB_DEV_EP_INFO *pEpInfo
);
BOOLEAN
EFIAPI
udciClearStallEp (
VOID *pUdciHndl,
USB_DEV_EP_INFO *pEpInfo
);
BOOLEAN
EFIAPI
udciEp0TxStatus (
VOID *pUdciHndl
);
BOOLEAN
EFIAPI
udciEpTxData (
VOID *pUdciHndl,
USBD_IO_REQ *pIoReq
);
BOOLEAN
EFIAPI
udciEpRxData (
VOID *pUdciHndl,
USBD_IO_REQ *pIoReq