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Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

Browse Source 
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, 

which are for MinnowBoard MAX open source project.


Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
2015-01-12 09:37:20 +00:00
committed by zwei4
parent 6f785cfcc3
commit 3cbfba02fe
518 changed files with 118538 additions and 0 deletions
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342
Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c Normal file
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/*++
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
BiosIdLib.c
Abstract:
Boot service DXE BIOS ID library implementation.
These functions in this file can be called during DXE and cannot be called during runtime
or in SMM which should use a RT or SMM library.
--*/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/HobLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/BiosIdLib.h>
#include <Guid/BiosId.h>
#include <Protocol/FirmwareVolume2.h>
#include <Protocol/LoadedImage.h>
EFI_STATUS
GetImageFromFv (
IN EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv,
IN EFI_GUID *NameGuid,
IN EFI_SECTION_TYPE SectionType,
OUT VOID **Buffer,
OUT UINTN *Size
)
{
EFI_STATUS Status;
EFI_FV_FILETYPE FileType;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINT32 AuthenticationStatus;
//
// Read desired section content in NameGuid file
//
*Buffer = NULL;
*Size = 0;
Status = Fv->ReadSection (
Fv,
NameGuid,
SectionType,
0,
Buffer,
Size,
&AuthenticationStatus
);
if (EFI_ERROR (Status) && (SectionType == EFI_SECTION_TE)) {
//
// Try reading PE32 section, since the TE section does not exist
//
*Buffer = NULL;
*Size = 0;
Status = Fv->ReadSection (
Fv,
NameGuid,
EFI_SECTION_PE32,
0,
Buffer,
Size,
&AuthenticationStatus
);
}
if (EFI_ERROR (Status) &&
((SectionType == EFI_SECTION_TE) || (SectionType == EFI_SECTION_PE32))) {
//
// Try reading raw file, since the desired section does not exist
//
*Buffer = NULL;
*Size = 0;
Status = Fv->ReadFile (
Fv,
NameGuid,
Buffer,
Size,
&FileType,
&Attributes,
&AuthenticationStatus
);
}
return Status;
}
EFI_STATUS
GetImageEx (
IN EFI_HANDLE ImageHandle,
IN EFI_GUID *NameGuid,
IN EFI_SECTION_TYPE SectionType,
OUT VOID **Buffer,
OUT UINTN *Size,
BOOLEAN WithinImageFv
)
{
EFI_STATUS Status;
EFI_HANDLE *HandleBuffer;
UINTN HandleCount;
UINTN Index;
EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
EFI_FIRMWARE_VOLUME2_PROTOCOL *ImageFv;
EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
if (ImageHandle == NULL && WithinImageFv) {
return EFI_INVALID_PARAMETER;
}
Status = EFI_NOT_FOUND;
ImageFv = NULL;
if (ImageHandle != NULL) {
Status = gBS->HandleProtocol (
ImageHandle,
&gEfiLoadedImageProtocolGuid,
(VOID **) &LoadedImage
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = gBS->HandleProtocol (
LoadedImage->DeviceHandle,
&gEfiFirmwareVolume2ProtocolGuid,
(VOID **) &ImageFv
);
if (!EFI_ERROR (Status)) {
Status = GetImageFromFv (ImageFv, NameGuid, SectionType, Buffer, Size);
}
}
if (Status == EFI_SUCCESS || WithinImageFv) {
return Status;
}
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiFirmwareVolume2ProtocolGuid,
NULL,
&HandleCount,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Find desired image in all Fvs
//
for (Index = 0; Index < HandleCount; ++Index) {
Status = gBS->HandleProtocol (
HandleBuffer[Index],
&gEfiFirmwareVolume2ProtocolGuid,
(VOID**)&Fv
);
if (EFI_ERROR (Status)) {
gBS->FreePool(HandleBuffer);
return Status;
}
if (ImageFv != NULL && Fv == ImageFv) {
continue;
}
Status = GetImageFromFv (Fv, NameGuid, SectionType, Buffer, Size);
if (!EFI_ERROR (Status)) {
break;
}
}
gBS->FreePool(HandleBuffer);
//
// Not found image
//
if (Index == HandleCount) {
return EFI_NOT_FOUND;
}
return EFI_SUCCESS;
}
/**
This function returns BIOS ID by searching HOB or FV.
@param BiosIdImage The BIOS ID got from HOB or FV.
@retval EFI_SUCCESS All parameters were valid and BIOS ID has been got.
@retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified.
@retval EFI_INVALID_PARAMETER The parameter is NULL.
**/
EFI_STATUS
GetBiosId (
OUT BIOS_ID_IMAGE *BiosIdImage
)
{
EFI_STATUS Status;
VOID *Address = NULL;
UINTN Size = 0;
DEBUG ((EFI_D_INFO, "Get BIOS ID from FV\n"));
Status = GetImageEx (
NULL,
&gEfiBiosIdGuid,
EFI_SECTION_RAW,
&Address,
&Size,
FALSE
);
if (Status == EFI_SUCCESS) {
//
// BiosId image is present in FV
//
if (Address != NULL) {
Size = sizeof (BIOS_ID_IMAGE);
gBS->CopyMem (
(void *) BiosIdImage,
Address,
Size
);
//
// GetImage () allocated buffer for Address, now clear it.
//
gBS->FreePool (Address);
DEBUG ((EFI_D_INFO, "Get BIOS ID from FV successfully\n"));
DEBUG ((EFI_D_INFO, "BIOS ID: %s\n", (CHAR16 *) (&(BiosIdImage->BiosIdString))));
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}
/**
This function returns the Version & Release Date and Time by getting and converting
BIOS ID.
@param BiosVersion The Bios Version out of the conversion.
@param BiosReleaseDate The Bios Release Date out of the conversion.
@param BiosReleaseTime - The Bios Release Time out of the conversion.
@retval EFI_SUCCESS - BIOS Version & Release Date and Time have been got successfully.
@retval EFI_NOT_FOUND - BiosId image is not found, and no parameter will be modified.
@retval EFI_INVALID_PARAMETER - All the parameters are NULL.
**/
EFI_STATUS
GetBiosVersionDateTime (
OUT CHAR16 *BiosVersion, OPTIONAL
OUT CHAR16 *BiosReleaseDate, OPTIONAL
OUT CHAR16 *BiosReleaseTime OPTIONAL
)
{
EFI_STATUS Status;
BIOS_ID_IMAGE BiosIdImage;
if ((BiosVersion == NULL) && (BiosReleaseDate == NULL) && (BiosReleaseTime == NULL)) {
return EFI_INVALID_PARAMETER;
}
Status = GetBiosId (&BiosIdImage);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
if (BiosVersion != NULL) {
//
// Fill the BiosVersion data from the BIOS ID.
//
StrCpy (BiosVersion, (CHAR16 *) (&(BiosIdImage.BiosIdString)));
}
if (BiosReleaseDate != NULL) {
//
// Fill the build timestamp date from the BIOS ID in the "MM/DD/YY" format.
//
BiosReleaseDate[0] = BiosIdImage.BiosIdString.TimeStamp[2];
BiosReleaseDate[1] = BiosIdImage.BiosIdString.TimeStamp[3];
BiosReleaseDate[2] = (CHAR16) ((UINT8) ('/'));
BiosReleaseDate[3] = BiosIdImage.BiosIdString.TimeStamp[4];
BiosReleaseDate[4] = BiosIdImage.BiosIdString.TimeStamp[5];
BiosReleaseDate[5] = (CHAR16) ((UINT8) ('/'));
//
// Add 20 for SMBIOS table
// Current Linux kernel will misjudge 09 as year 0, so using 2009 for SMBIOS table
//
BiosReleaseDate[6] = '2';
BiosReleaseDate[7] = '0';
BiosReleaseDate[8] = BiosIdImage.BiosIdString.TimeStamp[0];
BiosReleaseDate[9] = BiosIdImage.BiosIdString.TimeStamp[1];
BiosReleaseDate[10] = (CHAR16) ((UINT8) ('\0'));
}
if (BiosReleaseTime != NULL) {
//
// Fill the build timestamp time from the BIOS ID in the "HH:MM" format.
//
BiosReleaseTime[0] = BiosIdImage.BiosIdString.TimeStamp[6];
BiosReleaseTime[1] = BiosIdImage.BiosIdString.TimeStamp[7];
BiosReleaseTime[2] = (CHAR16) ((UINT8) (':'));

55
Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf Normal file
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#/*++
#
# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
# Module Name:
#
# BiosIdLib.inf
#
# Abstract:
#
# Component description file for BIOS ID library
#
#--*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BiosIdLib
FILE_GUID = 98546145-64F1-4d2e-814F-6BF963DB7930
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = BiosIdLib
PI_SPECIFICATION_VERSION = 0x0001000A
[Sources]
BiosIdLib.c
[Packages]
MdePkg/MdePkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
[LibraryClasses]
HobLib
[Guids]

46
Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf Normal file
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#
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
# Module Name:
#
# CpuIA32Lib.inf
#
# Abstract:
#
# Component description file for the Cpu IA32 library.
#
#--*/
[defines]
INF_VERSION = 0x00010005
BASE_NAME = CpuIA32Lib
FILE_GUID = 98546178-64F1-4d2e-814F-6BF963DB7930
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CpuIA32Lib
PI_SPECIFICATION_VERSION = 0x0001000A
[Sources]
EfiCpuVersion.c
[Sources.IA32]

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Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c Normal file
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/** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
EfiCpuVersion.c
Abstract:
Provide cpu version extract considering extended family & model ID.
--*/
#include <Library/CpuIA32.h>
/**
Extract CPU detail version infomation
@param FamilyId FamilyId, including ExtendedFamilyId
@param Model Model, including ExtendedModel
@param SteppingId SteppingId
@param Processor Processor
**/
VOID
EFIAPI
EfiCpuVersion (
IN OUT UINT16 *FamilyId, OPTIONAL
IN OUT UINT8 *Model, OPTIONAL
IN OUT UINT8 *SteppingId, OPTIONAL
IN OUT UINT8 *Processor OPTIONAL
)
{
EFI_CPUID_REGISTER Register;
UINT8 TempFamilyId;
EfiCpuid (EFI_CPUID_VERSION_INFO, &Register);
if (SteppingId != NULL) {
*SteppingId = (UINT8) (Register.RegEax & 0xF);
}
if (Processor != NULL) {
*Processor = (UINT8) ((Register.RegEax >> 12) & 0x3);
}
if (Model != NULL || FamilyId != NULL) {
TempFamilyId = (UINT8) ((Register.RegEax >> 8) & 0xF);
if (Model != NULL) {
*Model = (UINT8) ((Register.RegEax >> 4) & 0xF);
if (TempFamilyId == 0x6 || TempFamilyId == 0xF) {
*Model = (UINT8) (*Model | ((Register.RegEax >> 12) & 0xF0));
}
}

228
Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S Normal file
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#
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#Module Name:
#
# CpuIA32.c
#
#Abstract:
#
#--*/
##include "CpuIA32.h"
#include "EfiBind.h"
#---------------------------------------------------------------------------
.586p:
#.MODEL flat,C
.code:
#---------------------------------------------------------------------------
.globl ASM_PFX(EfiHalt)
.globl ASM_PFX(EfiWbinvd)
.globl ASM_PFX(EfiInvd)
.globl ASM_PFX(EfiCpuid)
.globl ASM_PFX(EfiReadMsr)
.globl ASM_PFX(EfiWriteMsr)
.globl ASM_PFX(EfiReadTsc)
.globl ASM_PFX(EfiDisableCache)
.globl ASM_PFX(EfiEnableCache)
.globl ASM_PFX(EfiGetEflags)
.globl ASM_PFX(EfiDisableInterrupts)
.globl ASM_PFX(EfiEnableInterrupts)
.globl ASM_PFX(EfiCpuidExt)
#VOID
#EfiHalt (
# VOID
#)
ASM_PFX(EfiHalt):
hlt
ret
#EfiHalt ENDP
#VOID
#EfiWbinvd (
# VOID
#)
ASM_PFX(EfiWbinvd):
wbinvd
ret
#EfiWbinvd ENDP
#VOID
#EfiInvd (
# VOID
#)
ASM_PFX(EfiInvd):
invd
ret
#EfiInvd ENDP
#VOID
#EfiCpuid (IN UINT32 RegisterInEax,
# OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
ASM_PFX(EfiCpuid):
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %esi
pushl %edi
pushal
movl 8(%ebp), %eax #RegisterInEax
cpuid
cmpl $0, 0xC(%ebp) # Reg
je L1
movl 0xC(%ebp), %edi # Reg
movl %eax, (%edi) # Reg->RegEax
movl %ebx, 4(%edi) # Reg->RegEbx
movl %ecx, 8(%edi) # Reg->RegEcx
movl %edx, 0xC(%edi) # Reg->RegEdx
L1:
popal
popl %edi
popl %esi
popl %ebx
popl %ebp
ret
#EfiCpuid ENDP
#UINT64
#EfiReadMsr (
# IN UINT32 Index
# );
ASM_PFX(EfiReadMsr):
movl 4(%esp), %ecx # Index
rdmsr
ret
#EfiReadMsr ENDP
#VOID
#EfiWriteMsr (
# IN UINT32 Index,
# IN UINT64 Value
# );
ASM_PFX(EfiWriteMsr):
movl 4(%esp), %ecx # Index
movl 8(%esp), %eax # DWORD PTR Value[0]
movl 0xC(%esp), %edx # DWORD PTR Value[4]
wrmsr
ret
#EfiWriteMsr ENDP
#UINT64
#EfiReadTsc (
# VOID
# )
ASM_PFX(EfiReadTsc):
rdtsc
ret
#EfiReadTsc ENDP
#VOID
#EfiDisableCache (
# VOID
#)
ASM_PFX(EfiDisableCache):
movl %cr0, %eax
bswapl %eax
andb $0x60, %al
cmpb $0x60, %al
je L2
movl %cr0, %eax
orl $0x60000000, %eax
movl %eax, %cr0
wbinvd
L2:
ret
#EfiDisableCache ENDP
#VOID
#EfiEnableCache (
# VOID
# )
ASM_PFX(EfiEnableCache):
wbinvd
movl %cr0, %eax
andl $0x9fffffff, %eax
movl %eax, %cr0
ret
#EfiEnableCache ENDP
#UINT32
#EfiGetEflags (
# VOID
# )
ASM_PFX(EfiGetEflags):
pushfl
popl %eax
ret
#EfiGetEflags ENDP
#VOID
#EfiDisableInterrupts (
# VOID
# )
ASM_PFX(EfiDisableInterrupts):
cli
ret
#EfiDisableInterrupts ENDP
#VOID
#EfiEnableInterrupts (
# VOID
# )
ASM_PFX(EfiEnableInterrupts):
sti
ret
#EfiEnableInterrupts ENDP
#VOID
#EfiCpuidExt (
# IN UINT32 RegisterInEax,
# IN UINT32 CacheLevel,
# OUT EFI_CPUID_REGISTER *Regs
# )
ASM_PFX(EfiCpuidExt):
push %ebx
push %edi
push %esi
pushal
movl 0x30(%esp), %eax # RegisterInEax
movl 0x34(%esp), %ecx # CacheLevel
cpuid
movl 0x38(%esp), %edi # DWORD PTR Regs
movl %eax, (%edi) # Reg->RegEax
movl %ebx, 4(%edi) # Reg->RegEbx
movl %ecx, 8(%edi) # Reg->RegEcx
movl %edx, 0xC(%edi) # Reg->RegEdx

211
Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm Normal file
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;
; This file contains an 'Intel Sample Driver' and is
; licensed for Intel CPUs and chipsets under the terms of your
; license agreement with Intel or your vendor. This file may
; be modified by the user, subject to additional terms of the
; license agreement
;
;
; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
;
; This program and the accompanying materials are licensed and made available under
; the terms and conditions of the BSD License that accompanies this distribution.
; The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;
;Module Name:
;
; CpuIA32.c
;
;Abstract:
;
;--*/
;#include "CpuIA32.h"
;---------------------------------------------------------------------------
.586p
.model flat,C
.code
;---------------------------------------------------------------------------
;VOID
;EfiHalt (
; VOID
;)
EfiHalt PROC C PUBLIC
hlt
ret
EfiHalt ENDP
;VOID
;EfiWbinvd (
; VOID
;)
EfiWbinvd PROC C PUBLIC
wbinvd
ret
EfiWbinvd ENDP
;VOID
;EfiInvd (
; VOID
;)
EfiInvd PROC C PUBLIC
invd
ret
EfiInvd ENDP
;VOID
;EfiCpuid (IN UINT32 RegisterInEax,
; OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
EfiCpuid PROC C PUBLIC
push ebp
mov ebp, esp
push ebx
push esi
push edi
pushad
mov eax, dword ptr[ebp + 8] ;egisterInEax
cpuid
cmp dword ptr[ebp + 0Ch], 0 ; Reg
je @F
mov edi,dword ptr [ebp+0Ch] ; Reg
mov dword ptr [edi],eax ; Reg->RegEax
mov dword ptr [edi+4],ebx ; Reg->RegEbx
mov dword ptr [edi+8],ecx ; Reg->RegEcx
mov dword ptr [edi+0Ch],edx ; Reg->RegEdx
@@:
popad
pop edi
pop esi
pop ebx
pop ebp
ret
EfiCpuid ENDP
;UINT64
;EfiReadMsr (
; IN UINT32 Index
; );
EfiReadMsr PROC C PUBLIC
mov ecx, dword ptr [esp + 4]; Index
rdmsr
ret
EfiReadMsr ENDP
;VOID
;EfiWriteMsr (
; IN UINT32 Index,
; IN UINT64 Value
; );
EfiWriteMsr PROC C PUBLIC
mov ecx, dword ptr [esp+4]; Index
mov eax, dword ptr [esp+8]; DWORD PTR Value[0]
mov edx, dword ptr [esp+0Ch]; DWORD PTR Value[4]
wrmsr
ret
EfiWriteMsr ENDP
;UINT64
;EfiReadTsc (
; VOID
; )
EfiReadTsc PROC C PUBLIC
rdtsc
ret
EfiReadTsc ENDP
;VOID
;EfiDisableCache (
; VOID
;)
EfiDisableCache PROC C PUBLIC
mov eax, cr0
bswap eax
and al, 60h
cmp al, 60h
je @F
mov eax, cr0
or eax, 060000000h
mov cr0, eax
wbinvd
@@:
ret
EfiDisableCache ENDP
;VOID
;EfiEnableCache (
; VOID
; )
EfiEnableCache PROC C PUBLIC
wbinvd
mov eax, cr0
and eax, 09fffffffh
mov cr0, eax
ret
EfiEnableCache ENDP
;UINT32
;EfiGetEflags (
; VOID
; )
EfiGetEflags PROC C PUBLIC
pushfd
pop eax
ret
EfiGetEflags ENDP
;VOID
;EfiDisableInterrupts (
; VOID
; )
EfiDisableInterrupts PROC C PUBLIC
cli
ret
EfiDisableInterrupts ENDP
;VOID
;EfiEnableInterrupts (
; VOID
; )
EfiEnableInterrupts PROC C PUBLIC
sti
ret
EfiEnableInterrupts ENDP
;VOID
;EfiCpuidExt (
; IN UINT32 RegisterInEax,
; IN UINT32 CacheLevel,
; OUT EFI_CPUID_REGISTER *Regs
; )
EfiCpuidExt PROC C PUBLIC USES ebx edi esi
pushad
mov eax, dword ptr [esp + 30h] ; RegisterInEax
mov ecx, dword ptr [esp + 34h] ; CacheLevel
cpuid
mov edi, dword ptr [esp + 38h] ; DWORD PTR Regs
mov dword ptr [edi], eax ; Reg->RegEax
mov dword ptr [edi + 4], ebx ; Reg->RegEbx

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Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c Normal file
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/** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
CpuIA32.c
Abstract:
--*/
#include <Library/CpuIA32.h>
VOID
EfiHalt (VOID)
{
__asm {
hlt
}
}
VOID
EfiWbinvd (VOID)
{
__asm {
wbinvd
}
}
VOID
EfiInvd (VOID)
{
__asm {
invd
}
}
VOID
EfiCpuid (IN UINT32 RegisterInEax,
OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
{
__asm {
pushad
mov eax, RegisterInEax
cpuid
cmp Reg, 0
je _Exit
mov edi, DWORD PTR Reg
mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax
mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx
mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx
mov DWORD PTR [edi].RegEdx, edx ; Reg->RegEdx
_Exit:
popad
}
}
UINT64
EfiReadMsr (IN UINT32 Index)
{
__asm {
mov ecx, Index
rdmsr
}
}
VOID
EfiWriteMsr (
IN UINT32 Index,
IN UINT64 Value
)
{
__asm {
mov ecx, Index
mov eax, DWORD PTR Value[0]
mov edx, DWORD PTR Value[4]
wrmsr
}
}
UINT64
EfiReadTsc (VOID)
{
__asm {
rdtsc
}
}
VOID
EfiDisableCache (VOID)
{
__asm {
mov eax, cr0
bswap eax
and al, 60h
cmp al, 60h
je Exit
mov eax, cr0
or eax, 060000000h
mov cr0, eax
wbinvd
Exit:
}
}
VOID
EfiEnableCache (VOID)
{
__asm {
wbinvd
mov eax, cr0
and eax, 09fffffffh
mov cr0, eax
}
}
UINT32
EfiGetEflags (
VOID
)
{
__asm {
pushfd
pop eax
}
}
VOID
EfiDisableInterrupts (VOID)
{
__asm {
cli
}
}
VOID
EfiEnableInterrupts (
VOID
)
{
__asm {
sti
}
}
VOID
EfiCpuidExt (
IN UINT32 RegisterInEax,
IN UINT32 CacheLevel,
OUT EFI_CPUID_REGISTER *Regs
)
{
__asm {
pushad
mov eax, RegisterInEax
mov ecx, CacheLevel
cpuid
mov edi, DWORD PTR Regs

212
Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S Normal file
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#
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#* Module Name:
#*
#* Cpu.asm
#*
#* Abstract:
#*
#------------------------------------------------------------------------------
##include <EfiBind.h>
.globl ASM_PFX(EfiHalt)
.globl ASM_PFX(EfiWbinvd)
.globl ASM_PFX(EfiInvd)
.globl ASM_PFX(EfiCpuid)
.globl ASM_PFX(EfiReadTsc)
.globl ASM_PFX(EfiDisableCache)
.globl ASM_PFX(EfiEnableCache)
.globl ASM_PFX(EfiReadMsr)
.globl ASM_PFX(EfiWriteMsr)
.globl ASM_PFX(EfiGetEflags)
.globl ASM_PFX(EfiDisableInterrupts)
.globl ASM_PFX(EfiEnableInterrupts)
.globl ASM_PFX(EfiCpuidExt)
.text
#------------------------------------------------------------------------------
# VOID
# EfiHalt (
# VOID
# )
#------------------------------------------------------------------------------
ASM_PFX(EfiHalt):
hlt
retq
#------------------------------------------------------------------------------
# VOID
# EfiWbinvd (
# VOID
# )
#------------------------------------------------------------------------------
ASM_PFX(EfiWbinvd):
wbinvd
retq
#------------------------------------------------------------------------------
# VOID
# EfiInvd (
# VOID
# )
#------------------------------------------------------------------------------
ASM_PFX(EfiInvd):
invd
retq
#------------------------------------------------------------------------------
# VOID
# EfiCpuid (
# IN UINT32 RegisterInEax, // rcx
# OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
# )
#------------------------------------------------------------------------------
ASM_PFX(EfiCpuid):
push %rbx
mov %rdx,%r8
mov %rcx,%rax
cpuid
cmp $0x0,%r8
je _Exit
mov %eax,(%r8)
mov %ebx,0x4(%r8)
mov %ecx,0x8(%r8)
mov %edx,0xc(%r8)
_Exit:
pop %rbx
retq
#------------------------------------------------------------------------------
# UINT64
# EfiReadMsr (
# IN UINT32 Index, // rcx
# )
#------------------------------------------------------------------------------
ASM_PFX(EfiReadMsr):
rdmsr
shl $0x20,%rdx
or %rdx,%rax
retq
#------------------------------------------------------------------------------
# VOID
# EfiWriteMsr (
# IN UINT32 Index, // rcx
# IN UINT64 Value // rdx
# )
#------------------------------------------------------------------------------
ASM_PFX(EfiWriteMsr):
mov %rdx,%rax
sar $0x20,%rdx
wrmsr
retq
#------------------------------------------------------------------------------
# UINT64
# EfiReadTsc (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(EfiReadTsc):
rdtsc
shl $0x20,%rax
shrd $0x20,%rdx,%rax
retq
#------------------------------------------------------------------------------
# VOID
# EfiDisableCache (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(EfiDisableCache):
# added a check to see if cache is already disabled. If it is, then skip.
mov %cr0,%rax
and $0x60000000,%rax
cmp $0x0,%rax
jne 1f
mov %cr0,%rax
or $0x60000000,%rax
mov %rax,%cr0
wbinvd
1:
retq
#------------------------------------------------------------------------------
# VOID
# EfiEnableCache (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(EfiEnableCache):
wbinvd
mov %cr0,%rax
and $0xffffffff9fffffff,%rax
mov %rax,%cr0
retq
#------------------------------------------------------------------------------
# UINTN
# EfiGetEflags (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(EfiGetEflags):
pushfq
pop %rax
retq
#------------------------------------------------------------------------------
# VOID
# EfiDisableInterrupts (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(EfiDisableInterrupts):
cli
ret
#------------------------------------------------------------------------------
# VOID
# EfiEnableInterrupts (
# VOID
# );
#------------------------------------------------------------------------------
ASM_PFX(EfiEnableInterrupts):
sti
ret
#------------------------------------------------------------------------------
# VOID
# EfiCpuidExt (
# IN UINT32 RegisterInEax,
# IN UINT32 CacheLevel,
# OUT EFI_CPUID_REGISTER *Regs
# )
#------------------------------------------------------------------------------
ASM_PFX(EfiCpuidExt):
push %rbx

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TITLE Cpu.asm: Assembly code for the x64 resources
;
; This file contains an 'Intel Sample Driver' and is
; licensed for Intel CPUs and chipsets under the terms of your
; license agreement with Intel or your vendor. This file may
; be modified by the user, subject to additional terms of the
; license agreement
;
;
; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
;
; This program and the accompanying materials are licensed and made available under
; the terms and conditions of the BSD License that accompanies this distribution.
; The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;
;
;
;
;* Module Name:
;*
;* Cpu.asm
;*
;* Abstract:
;*
;------------------------------------------------------------------------------
text SEGMENT
;------------------------------------------------------------------------------
; VOID
; EfiHalt (
; VOID
; )
;------------------------------------------------------------------------------
EfiHalt PROC PUBLIC
hlt
ret
EfiHalt ENDP
;------------------------------------------------------------------------------
; VOID
; EfiWbinvd (
; VOID
; )
;------------------------------------------------------------------------------
EfiWbinvd PROC PUBLIC
wbinvd
ret
EfiWbinvd ENDP
;------------------------------------------------------------------------------
; VOID
; EfiInvd (
; VOID
; )
;------------------------------------------------------------------------------
EfiInvd PROC PUBLIC
invd
ret
EfiInvd ENDP
;------------------------------------------------------------------------------
; VOID
; EfiCpuid (
; IN UINT32 RegisterInEax, // rcx
; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
; )
;------------------------------------------------------------------------------
EfiCpuid PROC PUBLIC
push rbx
mov r8, rdx ; r8 = *Reg
mov rax, rcx ; RegisterInEax
cpuid
cmp r8, 0
je _Exit
mov [r8 + 0], eax ; Reg->RegEax
mov [r8 + 4], ebx ; Reg->RegEbx
mov [r8 + 8], ecx ; Reg->RegEcx
mov [r8 + 12], edx ; Reg->RegEdx
_Exit:
pop rbx
ret
EfiCpuid ENDP
;------------------------------------------------------------------------------
; UINT64
; EfiReadMsr (
; IN UINT32 Index, // rcx
; )
;------------------------------------------------------------------------------
EfiReadMsr PROC PUBLIC
rdmsr
sal rdx, 32 ; edx:eax -> rax
or rax, rdx ; rax = edx:eax
ret
EfiReadMsr ENDP
;------------------------------------------------------------------------------
; VOID
; EfiWriteMsr (
; IN UINT32 Index, // rcx
; IN UINT64 Value // rdx
; )
;------------------------------------------------------------------------------
EfiWriteMsr PROC PUBLIC
mov rax, rdx ; rdx = Value
sar rdx, 32 ; convert rdx to edx upper 32-bits
wrmsr ; wrmsr[ecx] result = edx:eax
ret
EfiWriteMsr ENDP
;------------------------------------------------------------------------------
; UINT64
; EfiReadTsc (
; VOID
; );
;------------------------------------------------------------------------------
EfiReadTsc PROC PUBLIC
rdtsc
shl rax, 32
shrd rax, rdx, 32
ret
EfiReadTsc ENDP
;------------------------------------------------------------------------------
; VOID
; EfiDisableCache (
; VOID
; );
;------------------------------------------------------------------------------
EfiDisableCache PROC PUBLIC
; added a check to see if cache is already disabled. If it is, then skip.
mov rax, cr0
and rax, 060000000h
cmp rax, 0
jne @f
mov rax, cr0
or rax, 060000000h
mov cr0, rax
wbinvd
@@:
ret
EfiDisableCache ENDP
;------------------------------------------------------------------------------
; VOID
; EfiEnableCache (
; VOID
; );
;------------------------------------------------------------------------------
EfiEnableCache PROC PUBLIC
wbinvd
mov rax, cr0
and rax, 09fffffffh
mov cr0, rax
ret
EfiEnableCache ENDP
;------------------------------------------------------------------------------
; UINTN
; EfiGetEflags (
; VOID
; );
;------------------------------------------------------------------------------
EfiGetEflags PROC PUBLIC
pushfq
pop rax
ret
EfiGetEflags ENDP
;------------------------------------------------------------------------------
; VOID
; EfiDisableInterrupts (
; VOID
; );
;------------------------------------------------------------------------------
EfiDisableInterrupts PROC PUBLIC
cli
ret
EfiDisableInterrupts ENDP
;------------------------------------------------------------------------------
; VOID
; EfiEnableInterrupts (
; VOID
; );
;------------------------------------------------------------------------------
EfiEnableInterrupts PROC PUBLIC
sti
ret
EfiEnableInterrupts ENDP
;------------------------------------------------------------------------------
; VOID
; EfiCpuidExt (
; IN UINT32 RegisterInEax,
; IN UINT32 CacheLevel,
; OUT EFI_CPUID_REGISTER *Regs
; )
;------------------------------------------------------------------------------
EfiCpuidExt PROC PUBLIC
push rbx
mov rax, rcx ; rax = RegisterInEax
mov rcx, rdx ; rcx = CacheLevel
cpuid

287
Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c Normal file
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/*++
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
EfiRegTableLib.c
Abstract:
Lib function for table driven register initialization.
Revision History
--*/
#include <Library/EfiRegTableLib.h>
#include <Library/S3BootScriptLib.h>
//
// Local Functions
//
/**
Local worker function to process PCI_WRITE table entries. Performs write and
may also call BootScriptSave protocol if indicated in the Entry flags
@param Entry A pointer to the PCI_WRITE entry to process
@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
when processing the entry.
@retval Nothing.
**/
STATIC
VOID
PciWrite (
EFI_REG_TABLE_PCI_WRITE *Entry,
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
)
{
EFI_STATUS Status;
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
(UINT64) Entry->PciAddress,
1,
&Entry->Data
);
ASSERT_EFI_ERROR (Status);
if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
Status = S3BootScriptSavePciCfgWrite (
(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
(UINT64) Entry->PciAddress,
1,
&Entry->Data
);
ASSERT_EFI_ERROR (Status);
}
}
/**
Local worker function to process PCI_READ_MODIFY_WRITE table entries.
Performs RMW write and may also call BootScriptSave protocol if indicated in
the Entry flags.
@param Entry A pointer to the PCI_READ_MODIFY_WRITE entry to process.
@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
when processing the entry.
@retval Nothing.
**/
STATIC
VOID
PciReadModifyWrite (
EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
)
{
EFI_STATUS Status;
UINT32 TempData;
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
(UINT64) Entry->PciAddress,
1,
&TempData
);
ASSERT_EFI_ERROR (Status);
Entry->OrMask &= Entry->AndMask;
TempData &= ~Entry->AndMask;
TempData |= Entry->OrMask;
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
(UINT64) Entry->PciAddress,
1,
&TempData
);
ASSERT_EFI_ERROR (Status);
if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
Status = S3BootScriptSavePciCfgReadWrite (
(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
(UINT64) Entry->PciAddress,
&Entry->OrMask,
&Entry->AndMask
);
ASSERT_EFI_ERROR (Status);
}
}
/**
Local worker function to process MEM_READ_MODIFY_WRITE table entries.
Performs RMW write and may also call BootScriptSave protocol if indicated in
the Entry flags.
@param Entry A pointer to the MEM_READ_MODIFY_WRITE entry to process.
@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
when processing the entry.
@retval Nothing.
**/
STATIC
VOID
MemReadModifyWrite (
EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
)
{
EFI_STATUS Status;
UINT32 TempData;
Status = PciRootBridgeIo->Mem.Read (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
(UINT64) Entry->MemAddress,
1,
&TempData
);
ASSERT_EFI_ERROR (Status);
Entry->OrMask &= Entry->AndMask;
TempData &= ~Entry->AndMask;
TempData |= Entry->OrMask;
Status = PciRootBridgeIo->Mem.Write (
PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
(UINT64) Entry->MemAddress,
1,
&TempData
);
ASSERT_EFI_ERROR (Status);
if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
Status = S3BootScriptSaveMemReadWrite (
(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
Entry->MemAddress,
&Entry->OrMask,
&Entry->AndMask
);
ASSERT_EFI_ERROR (Status);
}
}
//
// Exported functions
//
/**
Processes register table assuming which may contain PCI, IO, MEM, and STALL
entries.
No parameter checking is done so the caller must be careful about omitting
values for PciRootBridgeIo or CpuIo parameters. If the regtable does
not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
NULL). If the regtable does not contain any IO or Mem entries, it is safe to
omit the CpuIo (supply NULL).
The RegTableEntry parameter is not checked, but is required.
gBS is assumed to have been defined and is used when processing stalls.
The function processes each entry sequentially until an OP_TERMINATE_TABLE
entry is encountered.
@param RegTableEntry A pointer to the register table to process
@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
when processing PCI table entries
@param CpuIo A pointer to the instance of CpuIo that is used when processing IO and
MEM table entries
@retval Nothing.
**/
VOID
ProcessRegTablePci (
EFI_REG_TABLE *RegTableEntry,
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
EFI_CPU_IO_PROTOCOL *CpuIo
)
{
while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {
switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
case OP_PCI_WRITE:
PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);
break;
case OP_PCI_READ_MODIFY_WRITE:
PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);
break;
case OP_MEM_READ_MODIFY_WRITE:
MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);
break;
default:
DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));
ASSERT (0);
break;
}
RegTableEntry++;
}
}
/**
Processes register table assuming which may contain IO, MEM, and STALL
entries, but must NOT contain any PCI entries. Any PCI entries cause an
ASSERT in a DEBUG build and are skipped in a free build.
No parameter checking is done. Both RegTableEntry and CpuIo parameters are
required.
gBS is assumed to have been defined and is used when processing stalls.
The function processes each entry sequentially until an OP_TERMINATE_TABLE
entry is encountered.
@param RegTableEntry A pointer to the register table to process
@param CpuIo A pointer to the instance of CpuIo that is used when processing IO and
MEM table entries
@retval Nothing.
**/
VOID
ProcessRegTableCpu (
EFI_REG_TABLE *RegTableEntry,
EFI_CPU_IO_PROTOCOL *CpuIo
)
{
while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {
switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {

52
Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.inf Normal file
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#
#
#/*++
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
# Module Name:
#
# EfiRegTableLib.inf
#
# Abstract:
#
# Component description file.
#
#--*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = EfiRegTableLib
FILE_GUID = 98546145-64F1-4d2e-814F-6BF963DB7930
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = EfiRegTableLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
EfiRegTableLib.c

467
Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c Normal file
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/** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/FlashDeviceLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiRuntimeLib.h>
#include <Protocol/SmmBase2.h>
#include <Guid/EventGroup.h>
#include "SpiChipDefinitions.h"
UINTN FlashDeviceBase = FLASH_DEVICE_BASE_ADDRESS;
EFI_SPI_PROTOCOL *mSpiProtocol = NULL;
EFI_STATUS
SpiFlashErase (
UINT8 *BaseAddress,
UINTN NumBytes
)
{
EFI_STATUS Status = EFI_SUCCESS;
UINT32 SectorSize;
UINT32 SpiAddress;
SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;
SectorSize = SECTOR_SIZE_4KB;
while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_SERASE,
SPI_WREN,
FALSE,
TRUE,
FALSE,
(UINT32) SpiAddress,
0,
NULL,
EnumSpiRegionBios
);
if (EFI_ERROR (Status)) {
break;
}
SpiAddress += SectorSize;
NumBytes -= SectorSize;
}
return Status;
}
EFI_STATUS
SpiFlashBlockErase (
UINT8 *BaseAddress,
UINTN NumBytes
)
{
EFI_STATUS Status = EFI_SUCCESS;
UINT32 SectorSize;
UINT32 SpiAddress;
SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;
SectorSize = SECTOR_SIZE_64KB;
while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_BERASE,
SPI_WREN,
FALSE,
TRUE,
FALSE,
(UINT32) SpiAddress,
0,
NULL,
EnumSpiRegionBios
);
if (EFI_ERROR (Status)) {
break;
}
SpiAddress += SectorSize;
NumBytes -= SectorSize;
}
return Status;
}
static
EFI_STATUS
SpiFlashWrite (
UINT8 *DstBufferPtr,
UINT8 *Byte,
IN UINTN Length
)
{
EFI_STATUS Status;
UINT32 NumBytes = (UINT32)Length;
UINT8* pBuf8 = Byte;
UINT32 SpiAddress;
SpiAddress = (UINT32)(UINTN)(DstBufferPtr) - (UINT32)FlashDeviceBase;
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_PROG,
SPI_WREN,
TRUE,
TRUE,
TRUE,
(UINT32)SpiAddress,
NumBytes,
pBuf8,
EnumSpiRegionBios
);
return Status;
}
/**
Read the Serial Flash Status Registers.
@param SpiStatus Pointer to a caller-allocated UINT8. On successful return, it contains the
status data read from the Serial Flash Status Register.
@retval EFI_SUCCESS Operation success, status is returned in SpiStatus.
@retval EFI_DEVICE_ERROR The block device is not functioning correctly and the operation failed.
**/
EFI_STATUS
ReadStatusRegister (
UINT8 *SpiStatus
)
{
EFI_STATUS Status;
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_RDSR,
SPI_WREN,
TRUE,
FALSE,
FALSE,
0,
1,
SpiStatus,
EnumSpiRegionBios
);
return Status;
}
EFI_STATUS
SpiFlashLock (
IN UINT8 *BaseAddress,
IN UINTN NumBytes,
IN BOOLEAN Lock
)
{
EFI_STATUS Status;
UINT8 SpiData;
UINT8 SpiStatus;
if (Lock) {
SpiData = SF_SR_WPE;
} else {
SpiData = 0;
}
//
// Always disable block protection to workaround tool issue.
// Feature may be re-enabled in a future bios.
//
SpiData = 0;
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_WRSR,
SPI_EWSR,
TRUE,
TRUE,
TRUE,
0,
1,
&SpiData,
EnumSpiRegionBios
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = ReadStatusRegister (&SpiStatus);
if (EFI_ERROR (Status)) {
return Status;
}
if ((SpiStatus & SpiData) != SpiData) {
Status = EFI_DEVICE_ERROR;
}
return Status;
}
/**
Read NumBytes bytes of data from the address specified by
PAddress into Buffer.
@param[in] PAddress The starting physical address of the read.
@param[in,out] NumBytes On input, the number of bytes to read. On output, the number
of bytes actually read.
@param[out] Buffer The destination data buffer for the read.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceRead (
IN UINTN PAddress,
IN OUT UINTN *NumBytes,
OUT UINT8 *Buffer
)
{
CopyMem(Buffer, (VOID*)PAddress, *NumBytes);
return EFI_SUCCESS;
}
/**
Write NumBytes bytes of data from Buffer to the address specified by
PAddresss.
@param[in] PAddress The starting physical address of the write.
@param[in,out] NumBytes On input, the number of bytes to write. On output,
the actual number of bytes written.
@param[in] Buffer The source data buffer for the write.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceWrite (
IN UINTN PAddress,
IN OUT UINTN *NumBytes,
IN UINT8 *Buffer
)
{
EFI_STATUS Status;
Status = SpiFlashWrite((UINT8 *)PAddress, Buffer, *NumBytes);
return Status;
}
/**
Erase the block staring at PAddress.
@param[in] PAddress The starting physical address of the block to be erased.
This library assume that caller garantee that the PAddress
is at the starting address of this block.
@param[in] LbaLength The length of the logical block to be erased.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceBlockErase (
IN UINTN PAddress,
IN UINTN LbaLength
)
{
EFI_STATUS Status;
Status = SpiFlashBlockErase((UINT8 *)PAddress, LbaLength);
return Status;
}
/**
Lock or unlock the block staring at PAddress.
@param[in] PAddress The starting physical address of region to be (un)locked.
@param[in] LbaLength The length of the logical block to be erased.
@param[in] Lock TRUE to lock. FALSE to unlock.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceBlockLock (
IN UINTN PAddress,
IN UINTN LbaLength,
IN BOOLEAN Lock
)
{
EFI_STATUS Status;
Status = SpiFlashLock((UINT8*)PAddress, LbaLength, Lock);
return Status;
}
VOID
EFIAPI
LibFvbFlashDeviceVirtualAddressChangeNotifyEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
gRT->ConvertPointer (0, (VOID **) &mSpiProtocol);
gRT->ConvertPointer (0, (VOID **) &FlashDeviceBase);
}
/**
The library constructuor.
The function does the necessary initialization work for this library
instance. Please put all initialization works in it.
@param[in] ImageHandle The firmware allocated handle for the UEFI image.
@param[in] SystemTable A pointer to the EFI system table.
@retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
It will ASSERT on error for debug version.
@retval EFI_ERROR Please reference LocateProtocol for error code details.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceSupportInit (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_EVENT Event;
UINT8 SfId[3];
UINT8 FlashIndex;
UINT8 SpiReadError;
UINT8 SpiNotMatchError;
EFI_SMM_BASE2_PROTOCOL *SmmBase;
BOOLEAN InSmm;
SpiReadError = 0x00;
SpiNotMatchError = 0x00;
InSmm = FALSE;
Status = gBS->LocateProtocol (
&gEfiSmmBase2ProtocolGuid,
NULL,
(void **)&SmmBase
);
if (!EFI_ERROR(Status)) {
Status = SmmBase->InSmm(SmmBase, &InSmm);
if (EFI_ERROR(Status)) {
InSmm = FALSE;
}
}
if (!InSmm) {
Status = gBS->LocateProtocol (
&gEfiSpiProtocolGuid,
NULL,
(VOID **)&mSpiProtocol
);
ASSERT_EFI_ERROR (Status);
Status = gBS->CreateEventEx (
EVT_NOTIFY_SIGNAL,
TPL_NOTIFY,
LibFvbFlashDeviceVirtualAddressChangeNotifyEvent,
NULL,
&gEfiEventVirtualAddressChangeGuid,
&Event
);
ASSERT_EFI_ERROR (Status);
} else {
Status = gBS->LocateProtocol (
&gEfiSmmSpiProtocolGuid,
NULL,
(VOID **)&mSpiProtocol
);
ASSERT_EFI_ERROR (Status);
}
for (FlashIndex = EnumSpiFlashW25Q64; FlashIndex < EnumSpiFlashMax; FlashIndex++) {
Status = mSpiProtocol->Init (mSpiProtocol, &(mInitTable[FlashIndex]));
if (!EFI_ERROR (Status)) {
//
// Read Vendor/Device IDs to check if the driver supports the Serial Flash device.
//
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_READ_ID,
SPI_WREN,
TRUE,
FALSE,
FALSE,
0,
3,
SfId,
EnumSpiRegionAll
);
if (!EFI_ERROR (Status)) {
if ((SfId[0] == mInitTable[FlashIndex].VendorId) &&
(SfId[1] == mInitTable[FlashIndex].DeviceId0) &&
(SfId[2] == mInitTable[FlashIndex].DeviceId1)) {
//
// Found a matching SPI device, FlashIndex now contains flash device.
//
DEBUG ((EFI_D_ERROR, "OK - Found SPI Flash Type in SPI Flash Driver, Device Type ID 0 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId0));
DEBUG ((EFI_D_ERROR, "Device Type ID 1 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId1));
if (mInitTable[FlashIndex].BiosStartOffset == (UINTN) (-1)) {
DEBUG ((EFI_D_ERROR, "ERROR - The size of BIOS image is bigger than SPI Flash device!\n"));
CpuDeadLoop ();
}
break;
} else {
SpiNotMatchError++;
}
} else {
SpiReadError++;
}
}
}
DEBUG ((EFI_D_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 = 0x%X\n", SfId[0], SfId[1], SfId[2]));
if (FlashIndex < EnumSpiFlashMax) {
return EFI_SUCCESS;
} else {
if (SpiReadError != 0) {
DEBUG ((EFI_D_ERROR, "ERROR - SPI Read ID execution failed! Error Count = %d\n", SpiReadError));
}
else {

50
Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.inf Normal file
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@@ -0,0 +1,50 @@
#
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FlashDeviceLib
FILE_GUID = E38A1C3C-928C-4bf7-B6C1-7F0EF163FAA5
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = FlashDeviceLib | DXE_SMM_DRIVER DXE_RUNTIME_DRIVER
CONSTRUCTOR = LibFvbFlashDeviceSupportInit
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
FlashDeviceLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec

840
Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.h Normal file
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@@ -0,0 +1,840 @@
/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Library/SpiFlash.H>
#define FLASH_SIZE 0x300000
#define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1)
//
// Serial Flash device initialization data table provided to the
// Intel(R) SPI Host Controller Compatibility Interface.
//
SPI_INIT_TABLE mInitTable[] = {
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25QXX, // DeviceId 0
SF_DEVICE_ID1_W25Q64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_ATMEL, // VendorId
SF_DEVICE_ID0_AT25DF321A, // DeviceId 0
SF_DEVICE_ID1_AT25DF321A, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_ATMEL, // VendorId
SF_DEVICE_ID0_AT26DF321, // DeviceId 0
SF_DEVICE_ID1_AT26DF321, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_ATMEL, // VendorId
SF_DEVICE_ID0_AT25DF641, // DeviceId 0
SF_DEVICE_ID1_AT25DF641, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25QXX, // DeviceId 0
SF_DEVICE_ID1_W25Q16, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25QXX, // DeviceId 0
SF_DEVICE_ID1_W25Q32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register.
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25XXX, // DeviceId 0
SF_DEVICE_ID1_W25X32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25XXX, // DeviceId 0
SF_DEVICE_ID1_W25X64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25QXX, // DeviceId 0
SF_DEVICE_ID1_W25Q128, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25LXX, // DeviceId 0
SF_DEVICE_ID1_MX25L16, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25LXX, // DeviceId 0
SF_DEVICE_ID1_MX25L32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25LXX, // DeviceId 0
SF_DEVICE_ID1_MX25L64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25LXX, // DeviceId 0
SF_DEVICE_ID1_MX25L128, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25UXX, // DeviceId 0
SF_DEVICE_ID1_MX25U6435F, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_SST, // VendorId
SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
SF_DEVICE_ID1_SST25VF016B,// DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_SST, // VendorId
SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
SF_DEVICE_ID1_SST25VF064C,// DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
//
// Minnow2 SPI type
//
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_N25Q064, // DeviceId 0
SF_DEVICE_ID1_N25Q064, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle20MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle20MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle20MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle20MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_M25PXXX, // DeviceId 0
SF_DEVICE_ID1_M25PX16, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_N25QXXX, // DeviceId 0
SF_DEVICE_ID1_N25Q032, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_M25PXXX, // DeviceId 0
SF_DEVICE_ID1_M25PX32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_M25PXXX, // DeviceId 0
SF_DEVICE_ID1_M25PX64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_N25QXXX, // DeviceId 0
SF_DEVICE_ID1_N25Q128, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_EON, // VendorId
SF_DEVICE_ID0_EN25QXX, // DeviceId 0
SF_DEVICE_ID1_EN25Q16, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_EON, // VendorId
SF_DEVICE_ID0_EN25QXX, // DeviceId 0
SF_DEVICE_ID1_EN25Q32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_EON, // VendorId
SF_DEVICE_ID0_EN25QXX, // DeviceId 0
SF_DEVICE_ID1_EN25Q64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_EON, // VendorId
SF_DEVICE_ID0_EN25QXX, // DeviceId 0
SF_DEVICE_ID1_EN25Q128, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_AMIC, // VendorId
SF_DEVICE_ID0_A25L016, // DeviceId 0
SF_DEVICE_ID1_A25L016, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.

51
Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c Normal file
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/*++
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
I2CLib.c
--*/
#ifdef ECP_FLAG
#include "EdkIIGlueDxe.h"
#else
#include <Library/DebugLib.h>
#include <Library/TimerLib.h>
#endif
#include <PchRegs/PchRegsPcu.h>
#include <PchRegs.h>
#include <PlatformBaseAddresses.h>
#include <PchRegs/PchRegsLpss.h>
#ifdef ECP_FLAG
#include "I2CLib.h"
#else
#include <Library/I2CLib.h>
#endif
#include <Protocol/GlobalNvsArea.h>
#ifndef ECP_FLAG
#include <Library/UefiBootServicesTableLib.h>
#endif
EFI_STATUS ByteReadI2C(

53
Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf Normal file
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## @file
# Null instance of Debug Agent Library with empty functions.
#
# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = I2CLib
FILE_GUID = 7f62bf44-2ba7-4c2d-9d4a-91c8906ff053
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = I2CLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources.common]
I2CLib.c
[LibraryClasses]
BaseLib
IoLib
TimerLib

32
Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/CommonHeader.h Normal file
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/**@file
Common header file shared by all source files.
This file includes package header files, library classes and protocol, PPI & GUID definitions.
Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __COMMON_HEADER_H_
#define __COMMON_HEADER_H_
#include <Base.h>

260
Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.c Normal file
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/** @file
ICH9 ACPI Timer implements one instance of Timer Library.
Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CommonHeader.h"
/**
The constructor function enables ACPI IO space.
If ACPI I/O space not enabled, this function will enable it.
It will always return RETURN_SUCCESS.
@retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
**/
RETURN_STATUS
EFIAPI
IntelPchAcpiTimerLibConstructor (
VOID
)
{
if ((PchLpcPciCfg8(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_EN) == 0) {
//
// If ACPI I/O space is not enabled, program ACPI I/O base address and enable it.
//
MmioWrite16 (
MmPciAddress (
0,
DEFAULT_PCI_BUS_NUMBER_PCH,
PCI_DEVICE_NUMBER_PCH_LPC,
PCI_FUNCTION_NUMBER_PCH_LPC,
R_PCH_LPC_ACPI_BASE
),
((PcdGet16 (PcdPchAcpiIoPortBaseAddress) & B_PCH_LPC_ACPI_BASE_BAR) | B_PCH_LPC_ACPI_BASE_EN)
);
}
return RETURN_SUCCESS;
}
/**
Internal function to read the current tick counter of ACPI.
Internal function to read the current tick counter of ACPI.
@return The tick counter read.
**/
STATIC
UINT32
InternalAcpiGetTimerTick (
VOID
)
{
return IoRead32 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_TMR);
}
/**
Stalls the CPU for at least the given number of ticks.
Stalls the CPU for at least the given number of ticks. It's invoked by
MicroSecondDelay() and NanoSecondDelay().
@param Delay A period of time to delay in ticks.
**/
STATIC
VOID
InternalAcpiDelay (
IN UINT32 Delay
)
{
UINT32 Ticks;
UINT32 Times;
Times = Delay >> 22;
Delay &= BIT22 - 1;
do {
//
// The target timer count is calculated here
//
Ticks = InternalAcpiGetTimerTick () + Delay;
Delay = BIT22;
//
// Wait until time out
// Delay >= 2^23 could not be handled by this function
// Timer wrap-arounds are handled correctly by this function
//
while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {
CpuPause ();
}
} while (Times-- > 0);
}
/**
Stalls the CPU for at least the given number of microseconds.
Stalls the CPU for the number of microseconds specified by MicroSeconds.
@param MicroSeconds The minimum number of microseconds to delay.
@return MicroSeconds
**/
UINTN
EFIAPI
MicroSecondDelay (
IN UINTN MicroSeconds
)
{
InternalAcpiDelay (
(UINT32)DivU64x32 (
MultU64x32 (
MicroSeconds,
V_PCH_ACPI_PM1_TMR_FREQUENCY
),
1000000u
)
);
return MicroSeconds;
}
/**
Stalls the CPU for at least the given number of nanoseconds.
Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
@param NanoSeconds The minimum number of nanoseconds to delay.
@return NanoSeconds
**/
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
)
{
InternalAcpiDelay (
(UINT32)DivU64x32 (
MultU64x32 (
NanoSeconds,
V_PCH_ACPI_PM1_TMR_FREQUENCY
),
1000000000u
)
);
return NanoSeconds;
}
/**
Retrieves the current value of a 64-bit free running performance counter.
Retrieves the current value of a 64-bit free running performance counter. The
counter can either count up by 1 or count down by 1. If the physical
performance counter counts by a larger increment, then the counter values
must be translated. The properties of the counter can be retrieved from
GetPerformanceCounterProperties().
@return The current value of the free running performance counter.
**/
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return (UINT64)InternalAcpiGetTimerTick ();
}
/**
Retrieves the 64-bit frequency in Hz and the range of performance counter
values.
If StartValue is not NULL, then the value that the performance counter starts
with immediately after is it rolls over is returned in StartValue. If
EndValue is not NULL, then the value that the performance counter end with
immediately before it rolls over is returned in EndValue. The 64-bit
frequency of the performance counter in Hz is always returned. If StartValue
is less than EndValue, then the performance counter counts up. If StartValue
is greater than EndValue, then the performance counter counts down. For
example, a 64-bit free running counter that counts up would have a StartValue
of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
@param StartValue The value the performance counter starts with when it
rolls over.
@param EndValue The value that the performance counter ends with before
it rolls over.
@return The frequency in Hz.
**/
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
*StartValue = 0;
}
if (EndValue != NULL) {
*EndValue = V_PCH_ACPI_PM1_TMR_MAX_VAL - 1;
}
return V_PCH_ACPI_PM1_TMR_FREQUENCY;
}
/**
Converts elapsed ticks of performance counter to time in nanoseconds.
This function converts the elapsed ticks of running performance counter to
time value in unit of nanoseconds.
@param Ticks The number of elapsed ticks of running performance counter.
@return The elapsed time in nanoseconds.
**/
UINT64
EFIAPI
GetTimeInNanoSecond (
IN UINT64 Ticks
)
{
UINT64 NanoSeconds;
UINT32 Remainder;
//
// Ticks
// Time = --------- x 1,000,000,000
// Frequency
//
NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, V_PCH_ACPI_PM1_TMR_FREQUENCY, &Remainder), 1000000000u);
//

56
Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf Normal file
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#/** @file
# Intel ICH9 Acpi Timer Instance
#
# ICH9 Acpi timer implements one instance of Timer Library. Acpi timer cannot be programmed,
# so it could be used by any types of drivers, including SMM drivers and Runtime drivers.
# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = IntelPchAcpiTimerLib
FILE_GUID = 0C0AC8C1-E368-4d20-85FE-23EFB3DB094E
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = TimerLib
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x00020000
CONSTRUCTOR = IntelPchAcpiTimerLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources.common]
IntelPchAcpiTimerLib.c
CommonHeader.h
[Packages]
MdePkg/MdePkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec

426
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c Normal file
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/** @file
Clock generator setting for multiplatform.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <BoardClkGens.h>
#include <Guid/SetupVariable.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Library/BaseMemoryLib.h>
#ifndef __GNUC__
#pragma optimize( "", off )
#endif
#define CLKGEN_EN 1
#define EFI_DEBUG 1
CLOCK_GENERATOR_DETAILS mSupportedClockGeneratorTable[] =
{
{ ClockGeneratorCk410, CK410_GENERATOR_ID , CK410_GENERATOR_SPREAD_SPECTRUM_BYTE, CK410_GENERATOR_SPREAD_SPECTRUM_BIT },
{ ClockGeneratorCk505, CK505_GENERATOR_ID , CK505_GENERATOR_SPREAD_SPECTRUM_BYTE, CK505_GENERATOR_SPREAD_SPECTRUM_BIT }
};
/**
Configure the clock generator using the SMBUS PPI services.
This function performs a block write, and dumps debug information.
@param PeiServices General purpose services available to every PEIM.
@param ClockType Clock generator's model name.
@param ClockAddress SMBUS address of clock generator.
@param ConfigurationTableLength Length of configuration table.
@param ConfigurationTable Pointer of configuration table.
@retval EFI_SUCCESS - Operation success.
**/
EFI_STATUS
ConfigureClockGenerator (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_SMBUS_PPI *SmbusPpi,
IN CLOCK_GENERATOR_TYPE ClockType,
IN UINT8 ClockAddress,
IN UINTN ConfigurationTableLength,
IN OUT UINT8 *ConfigurationTable
)
{
EFI_STATUS Status;
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH];
UINTN Length;
EFI_SMBUS_DEVICE_COMMAND Command;
#if CLKGEN_CONFIG_EXTRA
UINT8 j;
#endif
//
// Verify input arguments
//
ASSERT_EFI_ERROR (ConfigurationTableLength >= 6);
ASSERT_EFI_ERROR (ConfigurationTableLength <= MAX_CLOCK_GENERATOR_BUFFER_LENGTH);
ASSERT_EFI_ERROR (ClockType < ClockGeneratorMax);
ASSERT_EFI_ERROR (ConfigurationTable != NULL);
//
// Read the clock generator
//
SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
Length = sizeof (Buffer);
Command = 0;
Status = SmbusPpi->Execute (
PeiServices,
SmbusPpi,
SlaveAddress,
Command,
EfiSmbusReadBlock,
FALSE,
&Length,
Buffer
);
ASSERT_EFI_ERROR (Status);
#ifdef EFI_DEBUG
{
UINT8 i;
for (i = 0; i < sizeof (Buffer); i++) {
DEBUG((EFI_D_ERROR, "CK505 default Clock Generator Byte %d: %x\n", i, Buffer[i]));
}
#if CLKGEN_EN
for (i = 0; i < ConfigurationTableLength; i++) {
DEBUG((EFI_D_ERROR, "BIOS structure Clock Generator Byte %d: %x\n", i, ConfigurationTable[i]));
}
#endif
}
#endif
DEBUG((EFI_D_ERROR, "Expected Clock Generator ID is %x, expecting %x\n", mSupportedClockGeneratorTable[ClockType].ClockId,(Buffer[7]&0xF)));
//
// Program clock generator
//
Command = 0;
#if CLKGEN_EN
#if CLKGEN_CONFIG_EXTRA
for (j = 0; j < ConfigurationTableLength; j++) {
Buffer[j] = ConfigurationTable[j];
}
Buffer[30] = 0x00;
Status = SmbusPpi->Execute (
PeiServices,
SmbusPpi,
SlaveAddress,
Command,
EfiSmbusWriteBlock,
FALSE,
&Length,
Buffer
);
#else
Status = SmbusPpi->Execute (
PeiServices,
SmbusPpi,
SlaveAddress,
Command,
EfiSmbusWriteBlock,
FALSE,
&ConfigurationTableLength,
ConfigurationTable
);
#endif // CLKGEN_CONFIG_EXTRA
#else
ConfigurationTable[4] = (ConfigurationTable[4] & 0x3) | (Buffer[4] & 0xFC);
Command = 4;
Length = 1;
Status = SmbusPpi->Execute (
PeiServices,
SmbusPpi,
SlaveAddress,
Command,
EfiSmbusWriteBlock,
FALSE,
&Length,
&ConfigurationTable[4]
);
#endif //CLKGEN_EN
ASSERT_EFI_ERROR (Status);
//
// Dump contents after write
//
#ifdef EFI_DEBUG
{
UINT8 i;
SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
Length = sizeof (Buffer);
Command = 0;
Status = SmbusPpi->Execute (
PeiServices,
SmbusPpi,
SlaveAddress,
Command,
EfiSmbusReadBlock,
FALSE,
&Length,
Buffer
);
for (i = 0; i < ConfigurationTableLength; i++) {
DEBUG((EFI_D_ERROR, "Clock Generator Byte %d: %x\n", i, Buffer[i]));
}
}
#endif
return EFI_SUCCESS;
}
/**
Configure the clock generator using the SMBUS PPI services.
This function performs a block write, and dumps debug information.
@param PeiServices General purpose services available to every PEIM.
@param ClockType Clock generator's model name.
@param ClockAddress SMBUS address of clock generator.
@param ConfigurationTableLength Length of configuration table.
@param ConfigurationTable Pointer of configuration table.
@retval EFI_SUCCESS Operation success.
**/
UINT8
ReadClockGeneratorID (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_SMBUS_PPI *SmbusPpi,
IN UINT8 ClockAddress
)
{
EFI_STATUS Status;
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH];
UINTN Length;
EFI_SMBUS_DEVICE_COMMAND Command;
//
// Read the clock generator
//
SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
Length = sizeof (Buffer);
Command = 0;
Status = SmbusPpi->Execute (
PeiServices,
SmbusPpi,
SlaveAddress,
Command,
EfiSmbusReadBlock,
FALSE,
&Length,
Buffer
);
//
// Sanity check that the requested clock type is present in our supported clocks table
//
DEBUG((EFI_D_ERROR, "Expected Clock Generator ID is 0x%x\n", Buffer[7]));
return (Buffer[7]);
}
/**
Configure the clock generator to enable free-running operation. This keeps
the clocks from being stopped when the system enters C3 or C4.
@param None
@retval EFI_SUCCESS The function completed successfully.
**/
EFI_STATUS
ConfigurePlatformClocks (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *SmbusPpi
)
{
//
// Comment it out for now
// Not supported by Hybrid model.
//
EFI_STATUS Status;
UINT8 *ConfigurationTable;
CLOCK_GENERATOR_TYPE ClockType = ClockGeneratorCk505;
UINT8 ConfigurationTable_Desktop[] = CLOCK_GENERATOR_SETTINGS_DESKTOP;
UINT8 ConfigurationTable_Mobile[] = CLOCK_GENERATOR_SETTINGS_MOBILE;
UINT8 ConfigurationTable_Tablet[] = CLOCK_GENERATOR_SEETINGS_TABLET;
EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
BOOLEAN EnableSpreadSpectrum;
UINT8 ClockGenID=0;
SYSTEM_CONFIGURATION SystemConfiguration;
UINTN Length;
EFI_SMBUS_DEVICE_COMMAND Command;
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
UINT8 Data;
UINT8 ClockAddress = CLOCK_GENERATOR_ADDRESS;
UINTN VariableSize;
EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
//
// Obtain Platform Info from HOB.
//
Status = GetPlatformInfoHob ((CONST EFI_PEI_SERVICES **) PeiServices, &PlatformInfoHob);
ASSERT_EFI_ERROR (Status);
DEBUG((EFI_D_ERROR, "PlatformInfo protocol is working in ConfigurePlatformClocks()...%x\n",PlatformInfoHob->PlatformFlavor));
//
// Locate SMBUS PPI
//
Status = (**PeiServices).LocatePpi (
(CONST EFI_PEI_SERVICES **) PeiServices,
&gEfiPeiSmbusPpiGuid,
0,
NULL,
&SmbusPpi
);
ASSERT_EFI_ERROR (Status);
Data = 0;
SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
Length = 1;
Command = 0x87; //Control Register 7 Vendor ID Check
Status = ((EFI_PEI_SMBUS_PPI *) SmbusPpi)->Execute (
PeiServices,
SmbusPpi,
SlaveAddress,
Command,
EfiSmbusReadByte,
FALSE,
&Length,
&Data
);
if (EFI_ERROR (Status) || ((Data & 0x0F) != CK505_GENERATOR_ID)) {
DEBUG((EFI_D_ERROR, "Clock Generator CK505 Not Present, vendor ID on board is %x\n",(Data & 0x0F)));
return EFI_SUCCESS;
}
ClockGenID = Data & 0x0F;
EnableSpreadSpectrum = FALSE;
VariableSize = sizeof (SYSTEM_CONFIGURATION);
ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
Status = (*PeiServices)->LocatePpi (
(CONST EFI_PEI_SERVICES **) PeiServices,
&gEfiPeiReadOnlyVariable2PpiGuid,
0,
NULL,
(VOID **) &Variable
);
//
// Use normal setup default from NVRAM variable,
// the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
//
VariableSize = sizeof(SYSTEM_CONFIGURATION);
Status = Variable->GetVariable (Variable,
L"Setup",
&gEfiSetupVariableGuid,
NULL,
&VariableSize,
&SystemConfiguration);
if(!EFI_ERROR (Status)){
EnableSpreadSpectrum = SystemConfiguration.EnableClockSpreadSpec;
}
//
// Perform platform-specific intialization dependent upon Board ID:
//
DEBUG((EFI_D_ERROR, "board id is %x, platform id is %x\n",PlatformInfoHob->BoardId,PlatformInfoHob->PlatformFlavor));
switch (PlatformInfoHob->BoardId) {
case BOARD_ID_MINNOW2:
default:
switch(PlatformInfoHob->PlatformFlavor) {
case FlavorTablet:
ConfigurationTable = ConfigurationTable_Tablet;
Length = sizeof (ConfigurationTable_Tablet);
break;
case FlavorMobile:
ConfigurationTable = ConfigurationTable_Mobile;
Length = sizeof (ConfigurationTable_Mobile);
break;
case FlavorDesktop:
default:
ConfigurationTable = ConfigurationTable_Desktop;
Length = sizeof (ConfigurationTable_Desktop);
break;
}
break;
}
//
// Perform common clock initialization:
//
// Program Spread Spectrum function.
//
if (EnableSpreadSpectrum)
{
ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSpectrumByteOffset] |= mSupportedClockGeneratorTable[ClockType].SpreadSpectrumBitOffset;
} else {
ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSpectrumByteOffset] &= ~(mSupportedClockGeneratorTable[ClockType].SpreadSpectrumBitOffset);
}
#if CLKGEN_EN
Status = ConfigureClockGenerator (PeiServices, SmbusPpi, ClockType, ClockAddress, Length, ConfigurationTable);
ASSERT_EFI_ERROR (Status);
#endif // CLKGEN_EN
return EFI_SUCCESS;
}
static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
{
EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEfiPeiSmbusPpiGuid,
ConfigurePlatformClocks
}
};
EFI_STATUS
InstallPlatformClocksNotify (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status;
DEBUG ((EFI_D_INFO, "InstallPlatformClocksNotify()...\n"));

260
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h Normal file
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/**@file
Clock generator setting for multiplatform.
This file includes package header files, library classes.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _BOARD_CLK_GEN_H_
#define _BOARD_CLK_GEN_H_
#include <PiPei.h>
#include <Library/HobLib.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/SmbusLib.h>
#include <Ppi/Smbus.h>
#include <IndustryStandard/SmBus.h>
#include <Guid/PlatformInfo.h>
#define CLOCK_GENERATOR_ADDRESS 0xd2
#define CLOCK_GENERATOR_SEETINGS_TABLET {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
#define CLOCK_GENERATOR_SETTINGS_MOBILE {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
#define CLOCK_GENERATOR_SETTINGS_DESKTOP {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
typedef enum {
ClockGeneratorCk410,
ClockGeneratorCk505,
ClockGeneratorMax
} CLOCK_GENERATOR_TYPE;
typedef struct {
CLOCK_GENERATOR_TYPE ClockType;
UINT8 ClockId;
UINT8 SpreadSpectrumByteOffset;
UINT8 SpreadSpectrumBitOffset;
} CLOCK_GENERATOR_DETAILS;
#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20
//
// CK410 Definitions
//
#define CK410_GENERATOR_ID 0x65
#define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE 1
#define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
#define CK410_GENERATOR_CLOCK_FREERUN_BYTE 4
#define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2)
//
// CK505 Definitions
//
#define VF_CK505_GENERATOR_ID 0x5
#define CK505_GENERATOR_ID 0x5 // Confirmed readout is 5
#define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE 4
#define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1)
#define CK505_GENERATOR_PERCENT_SPREAD_BYTE 1
#define CK505_GENERATOR_PERCENT_MASK ~(0xE)
#define CK505_GENERATOR_PERCENT_250_VALUE 0xC
#define CK505_GENERATOR_PERCENT_050_VALUE 0x4
#define CK505_GENERATOR_PERCENT_000_VALUE 0x2
//
// IDT Definitions
//
#define IDT_GENERATOR_ID_REVA 0x1 //IDT Rev A
#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BYTE 0
#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
#define IDTRevA_GENERATOR_PERCENT_SPREAD_BYTE 5
#define IDTRevA_GENERATOR_PERCENT_250_VALUE 0xF
#define IDTRevA_GENERATOR_PERCENT_050_VALUE 0x3
#define IDTRevA_GENERATOR_PERCENT_000_VALUE 0xE
#define IDTRevA_GENERATOR_PERCENT_MASK ~(0xF)
#define IDT_GENERATOR_ID_REVB 0x11 //IDT RevB
#define IDT_GENERATOR_ID_REVD 0x21 //IDT RevD
//
// CLOCK CONTROLLER
// SmBus address to read DIMM SPD
//
#define SMBUS_BASE_ADDRESS 0xEFA0
#define SMBUS_BUS_DEV_FUNC 0x1F0300
#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4
#define SMBUS_ADDR_CH_A_1 0xA0
#define SMBUS_ADDR_CH_A_2 0xA2
#define SMBUS_ADDR_CH_B_1 0xA4
#define SMBUS_ADDR_CH_B_2 0xA6
//
// Bits for FWH_DEC_EN1<4E>Firmware Hub Decode Enable Register (LPC I/F<>D31:F0)
//
#define B_ICH_LPC_FWH_BIOS_DEC_F0 0x4000
#define B_ICH_LPC_FWH_BIOS_DEC_E0 0x1000
#define B_ICH_LPC_FWH_BIOS_DEC_E8 0x2000
#define B_ICH_LPC_FWH_BIOS_LEG_F 0x0080
#define B_ICH_LPC_FWH_BIOS_LEG_E 0x0040
//
// An arbitrary maximum length for clock generator buffers
//
#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20
//
// SmBus Bus Device Function and Register Definitions
//
#define SMBUS_BUS_NUM 0
#define SMBUS_DEV_NUM 31
#define SMBUS_FUNC_NUM 3
#define SMBUS_BUS_DEV_FUNC_NUM \
SB_PCI_CFG_ADDRESS(SMBUS_BUS_NUM, SMBUS_DEV_NUM, SMBUS_FUNC_NUM, 0)
//
//ICH7: SMBus I/O Space Equates;
//
#define BIT_SLAVE_ADDR BIT00
#define BIT_COMMAND BIT01
#define BIT_DATA BIT02
#define BIT_COUNT BIT03
#define BIT_WORD BIT04
#define BIT_CONTROL BIT05
#define BIT_PEC BIT06
#define BIT_READ BIT07
#define SMBUS_IO_READ_BIT BIT00
#define SMB_CMD_QUICK 0x00
#define SMB_CMD_BYTE 0x04
#define SMB_CMD_BYTE_DATA 0x08
#define SMB_CMD_WORD_DATA 0x0C
#define SMB_CMD_PROCESS_CALL 0x10
#define SMB_CMD_BLOCK 0x14
#define SMB_CMD_I2C_READ 0x18
#define SMB_CMD_RESERVED 0x1c
#define HST_STS_BYTE_DONE 0x80
#define SMB_HST_STS 0x000
#define SMB_HST_CNT 0x002
#define SMB_HST_CMD 0x003
#define SMB_HST_ADD 0x004
#define SMB_HST_DAT_0 0x005
#define SMB_HST_DAT_1 0x006
#define SMB_HST_BLK_DAT 0x007
#define SMB_PEC 0x008
#define SMB_RCV_SLVA 0x009
#define SMB_SLV_DAT 0x00A
#define SMB_AUX_STS 0x00C
#define SMB_AUX_CTL 0x00D
#define SMB_SMLINK_PIN_CTL 0x00E
#define SMB_SMBUS_PIN_CTL 0x00F
#define SMB_SLV_STS 0x010
#define SMB_SLV_CMD 0x011
#define SMB_NTFY_DADDR 0x014
#define SMB_NTFY_DLOW 0x016
#define SMB_NTFY_DHIGH 0x017
//
// PCI Register Definitions - use SmbusPolicyPpi->PciAddress + offset listed below
//
#define R_COMMAND 0x04 // PCI Command Register, 16bit
#define B_IOSE 0x01 // RW
#define R_BASE_ADDRESS 0x20 // PCI BAR for SMBus I/O
#define B_BASE_ADDRESS 0xFFE0 // RW
#define R_HOST_CONFIGURATION 0x40 // SMBus Host Configuration Register
#define B_HST_EN 0x01 // RW
#define B_SMB_SMI_EN 0x02 // RW
#define B_I2C_EN 0x04 // RW
//
// I/O Register Definitions - use SmbusPolicyPpi->BaseAddress + offset listed below
//
#define HOST_STATUS_REGISTER 0x00 // Host Status Register R/W
#define HST_STS_HOST_BUSY 0x01 // RO
#define HST_STS_INTR 0x02 // R/WC
#define HST_STS_DEV_ERR 0x04 // R/WC
#define HST_STS_BUS_ERR 0x08 // R/WC
#define HST_STS_FAILED 0x10 // R/WC
#define SMBUS_B_SMBALERT_STS 0x20 // R/WC
#define HST_STS_INUSE 0x40 // R/WC
#define SMBUS_B_BYTE_DONE_STS 0x80 // R/WC
#define SMBUS_B_HSTS_ALL 0xFF // R/WC
#define HOST_CONTROL_REGISTER 0x02 // Host Control Register R/W
#define HST_CNT_INTREN 0x01 // RW
#define HST_CNT_KILL 0x02 // RW
#define SMBUS_B_SMB_CMD 0x1C // RW
#define SMBUS_V_SMB_CMD_QUICK 0x00
#define SMBUS_V_SMB_CMD_BYTE 0x04
#define SMBUS_V_SMB_CMD_BYTE_DATA 0x08
#define SMBUS_V_SMB_CMD_WORD_DATA 0x0C
#define SMBUS_V_SMB_CMD_PROCESS_CALL 0x10
#define SMBUS_V_SMB_CMD_BLOCK 0x14
#define SMBUS_V_SMB_CMD_IIC_READ 0x18
#define SMBUS_B_LAST_BYTE 0x20 // WO
#define HST_CNT_START 0x40 // WO
#define HST_CNT_PEC_EN 0x80 // RW
#define HOST_COMMAND_REGISTER 0x03 // Host Command Register R/W
#define XMIT_SLAVE_ADDRESS_REGISTER 0x04 // Transmit Slave Address Register R/W
#define SMBUS_B_RW_SEL 0x01 // RW
#define SMBUS_B_ADDRESS 0xFE // RW
#define HOST_DATA_0_REGISTER 0x05 // Data 0 Register R/W
#define HOST_DATA_1_REGISTER 0x06 // Data 1 Register R/W
#define HOST_BLOCK_DATA_BYTE_REGISTER 0x07 // Host Block Data Register R/W
#define SMBUS_R_PEC 0x08 // Packet Error Check Data Register R/W
#define SMBUS_R_RSA 0x09 // Receive Slave Address Register R/W
#define SMBUS_B_SLAVE_ADDR 0x7F // RW
#define SMBUS_R_SD 0x0A // Receive Slave Data Register R/W
#define SMBUS_R_AUXS 0x0C // Auxiliary Status Register R/WC
#define SMBUS_B_CRCE 0x01 //R/WC
#define AUXILIARY_CONTROL_REGISTER 0x0D // Auxiliary Control Register R/W
#define SMBUS_B_AAC 0x01 //R/W
#define SMBUS_B_E32B 0x02 //R/W
#define SMBUS_R_SMLC 0x0E // SMLINK Pin Control Register R/W
#define SMBUS_B_SMLINK0_CUR_STS 0x01 // RO
#define SMBUS_B_SMLINK1_CUR_STS 0x02 // RO
#define SMBUS_B_SMLINK_CLK_CTL 0x04 // RW
#define SMBUS_R_SMBC 0x0F // SMBus Pin Control Register R/W
#define SMBUS_B_SMBCLK_CUR_STS 0x01 // RO
#define SMBUS_B_SMBDATA_CUR_STS 0x02 // RO
#define SMBUS_B_SMBCLK_CTL 0x04 // RW
#define SMBUS_R_SSTS 0x10 // Slave Status Register R/WC
#define SMBUS_B_HOST_NOTIFY_STS 0x01 // R/WC
#define SMBUS_R_SCMD 0x11 // Slave Command Register R/W
#define SMBUS_B_HOST_NOTIFY_INTREN 0x01 // R/W
#define SMBUS_B_HOST_NOTIFY_WKEN 0x02 // R/W
#define SMBUS_B_SMBALERT_DIS 0x04 // R/W
#define SMBUS_R_NDA 0x14 // Notify Device Address Register RO
#define SMBUS_B_DEVICE_ADDRESS 0xFE // RO
#define SMBUS_R_NDLB 0x16 // Notify Data Low Byte Register RO
#define SMBUS_R_NDHB 0x17 // Notify Data High Byte Register RO
#define BUS_TRIES 3 // How many times to retry on Bus Errors
#define SMBUS_NUM_RESERVED 21 // Number of device addresses that are
// reserved by the SMBus spec.
#define SMBUS_ADDRESS_ARP 0xC2 >> 1
#define SMBUS_DATA_PREPARE_TO_ARP 0x01
#define SMBUS_DATA_RESET_DEVICE 0x02
#define SMBUS_DATA_GET_UDID_GENERAL 0x03
#define SMBUS_DATA_ASSIGN_ADDRESS 0x04
#define SMBUS_GET_UDID_LENGTH 17 // 16 byte UDID + 1 byte address

535
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c Normal file
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/** @file
Gpio setting for multiplatform..
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <BoardGpios.h>
#include <Guid/SetupVariable.h>
//
//AlpineValley platform ocde begin
//
#define AV_SC_REG_GPIOS_MUXES_SEL0 0x48
#define AV_SC_REG_GPIOS_MUXES_SEL1 0x4C
#define AV_SC_REG_GPIOS_MUXES_SEL2 0x50
#define AV_SC_REG_GPIOS_MUXES_EN0 0x54
#define AV_SC_REG_GPIOS_MUXES_EN1 0x58
#define AV_SC_REG_GPIOS_MUXES_EN2 0x5C
//
//AlpineValley platform code end
//
EFI_GUID gPeiSmbusPpiGuid = EFI_PEI_SMBUS_PPI_GUID;
/**
@param None
@retval EFI_SUCCESS The function completed successfully.
**/
EFI_STATUS
ConfigurePlatformSysCtrlGpio (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *SmbusPpi
)
{
//
//AlpineValley platform code begin
//
// Initialize GPIO Settings:
//
UINT32 Status;
EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
DEBUG ((EFI_D_INFO, "ConfigurePlatformSysCtrlGpio()...\n"));
//
// Obtain Platform Info from HOB.
//
Status = GetPlatformInfoHob ((const EFI_PEI_SERVICES **)PeiServices, &PlatformInfoHob);
ASSERT_EFI_ERROR (Status);
//
// The GPIO settings are dependent upon the platform. Obtain the Board ID through
// the EC to determine the current platform.
//
DEBUG ((EFI_D_INFO, "Platform Flavor | Board ID = 0x%X | 0x%X\n", PlatformInfoHob->PlatformFlavor, PlatformInfoHob->BoardId));
Status = (**PeiServices).LocatePpi (
(const EFI_PEI_SERVICES **)PeiServices,
&gPeiSmbusPpiGuid,
0,
NULL,
(void **)&SmbusPpi
);
ASSERT_EFI_ERROR (Status);
//
// Select/modify the GPIO initialization data based on the Board ID.
//
switch (PlatformInfoHob->BoardId)
{
default:
Status = EFI_SUCCESS;
//
// Do nothing for other RVP boards.
//
break;
}
return Status;
}
static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
{
EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEfiPeiSmbusPpiGuid,
ConfigurePlatformSysCtrlGpio
}
};
EFI_STATUS
InstallPlatformSysCtrlGPIONotify (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status;
DEBUG ((EFI_D_INFO, "InstallPlatformSysCtrlGPIONotify()...\n"));
Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
ASSERT_EFI_ERROR (Status);
return EFI_SUCCESS;
}
#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
/**
Returns the Correct GPIO table for Mobile/Desktop respectively.
Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
@param PeiServices General purpose services available to every PEIM.
@param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
@param BoardId BoardId ID as determined through the EC.
@retval EFI_SUCCESS The function completed successfully.
@retval EFI_DEVICE_ERROR KSC fails to respond.
**/
EFI_STATUS
MultiPlatformGpioTableInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
EFI_STATUS Status;
EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
UINTN VarSize;
SYSTEM_CONFIGURATION SystemConfiguration;
DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));
//
// Select/modify the GPIO initialization data based on the Board ID.
//
switch (PlatformInfoHob->BoardId) {
case BOARD_ID_MINNOW2: // Minnow2
Status = (**PeiServices).LocatePpi (
PeiServices,
&gEfiPeiReadOnlyVariable2PpiGuid,
0,
NULL,
(void **)&PeiReadOnlyVarPpi
);
ASSERT_EFI_ERROR (Status);
VarSize = sizeof (SYSTEM_CONFIGURATION);
Status = PeiReadOnlyVarPpi->GetVariable (
PeiReadOnlyVarPpi,
PLATFORM_SETUP_VARIABLE_NAME,
&gEfiSetupVariableGuid,
NULL,
&VarSize,
&SystemConfiguration
);
if (SystemConfiguration.GpioWakeCapability == 1) {
PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData2;
}
else {
PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData;
}
PlatformInfoHob->PlatformGpioData_NC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_NC[0];
PlatformInfoHob->PlatformGpioData_SC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SC[0];
PlatformInfoHob->PlatformGpioData_SUS = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SUS[0];
break;
}
return EFI_SUCCESS;
}
UINT32
GPIORead32 (
IN UINT32 mmio_conf
)
{
UINT32 conf_val;
UINT32 i;
conf_val = MmioRead32(mmio_conf);
for(i=0;i<5;i++){
if(conf_val == 0xffffffff)
conf_val = MmioRead32(mmio_conf);
else
break;
}
return conf_val;
}
/**
Set GPIO CONF0 and PAD_VAL registers for NC/SC/SUS GPIO clusters
@param Gpio_Mmio_Offset GPIO_SCORE_OFFSET or GPIO_NCORE_OFFSET or GPIO_SSUS_OFFSET.
@param Gpio_Pin_Num Pin numbers to config for each GPIO clusters.
@param Gpio_Conf_Data GPIO_CONF_PAD_INIT data array for each GPIO clusters.
**/
VOID
InternalGpioConfig (
IN UINT32 Gpio_Mmio_Offset,
IN UINT32 Gpio_Pin_Num,
GPIO_CONF_PAD_INIT* Gpio_Conf_Data
)
{
UINT32 index;
UINT32 mmio_conf0;
UINT32 mmio_padval;
PAD_CONF0 conf0_val;
PAD_VAL pad_val;
//
// GPIO WELL -- Memory base registers
//
// A0 BIOS Spec doesn't mention it although X0 does. comment out now.
// GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
//
for(index=0; index < Gpio_Pin_Num; index++)
{
//
// Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
//
mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
#ifdef EFI_DEBUG
DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
#endif
DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
Gpio_Conf_Data[index].usage,
Gpio_Conf_Data[index].func,
Gpio_Conf_Data[index].int_type,
Gpio_Conf_Data[index].pull,
mmio_conf0));
//
// Step 1: PadVal Programming.
//
pad_val.dw = GPIORead32(mmio_padval);
//
// Config PAD_VAL only for GPIO (Non-Native) Pin
//
if(Native != Gpio_Conf_Data[index].usage)
{
pad_val.dw &= ~0x6; // Clear bits 1:2
pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
//
// set GPO default value
//
if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
{
pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
}
}
DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
MmioWrite32(mmio_padval, pad_val.dw);
//
// Step 2: CONF0 Programming
// Read GPIO default CONF0 value, which is assumed to be default value after reset.
//
conf0_val.dw = GPIORead32(mmio_conf0);
//
// Set Function #
//
conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
if(GPO == Gpio_Conf_Data[index].usage)
{
//
// If used as GPO, then internal pull need to be disabled.
//
conf0_val.r.Pull_assign = 0; // Non-pull
}
else
{
//
// Set PullUp / PullDown
//
if(P_20K_H == Gpio_Conf_Data[index].pull)
{
conf0_val.r.Pull_assign = 0x1; // PullUp
conf0_val.r.Pull_strength = 0x2;// 20K
}
else if(P_20K_L == Gpio_Conf_Data[index].pull)
{
conf0_val.r.Pull_assign = 0x2; // PullDown
conf0_val.r.Pull_strength = 0x2;// 20K
}
else if(P_10K_H == Gpio_Conf_Data[index].pull)
{
conf0_val.r.Pull_assign = 0x1; // PullUp
conf0_val.r.Pull_strength = 0x1;// 10K
}
else if(P_10K_L == Gpio_Conf_Data[index].pull)
{
conf0_val.r.Pull_assign = 0x2; // PullDown
conf0_val.r.Pull_strength = 0x1;// 10K
}
else if(P_2K_H == Gpio_Conf_Data[index].pull)
{
conf0_val.r.Pull_assign = 0x1; // PullUp
conf0_val.r.Pull_strength = 0x0;// 2K
}
else if(P_2K_L == Gpio_Conf_Data[index].pull)
{
conf0_val.r.Pull_assign = 0x2; // PullDown
conf0_val.r.Pull_strength = 0x0;// 2K
}
else if(P_NONE == Gpio_Conf_Data[index].pull)
{
conf0_val.r.Pull_assign = 0; // Non-pull
}
else
{
ASSERT(FALSE); // Invalid value
}
}
//
// Set INT Trigger Type
//
conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
//
// Set INT Trigger Type
//
if(TRIG_ == Gpio_Conf_Data[index].int_type)
{
//
// Interrupt not capable, clear bits 27:24
//
}
else
{
conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
}
DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
//
// Write back the targeted GPIO config value according to platform (board) GPIO setting.
//
MmioWrite32 (mmio_conf0, conf0_val.dw);
}
//
// A0 BIOS Spec doesn't mention it although X0 does. comment out now.
// GPIO SCORE write 0x01001002 to IOBASE + 0x0900
//
}
/**
Returns the Correct GPIO table for Mobile/Desktop respectively.
Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
@param PeiServices General purpose services available to every PEIM.
@param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
@param BoardId BoardId ID as determined through the EC.
@retval EFI_SUCCESS The function completed successfully.
@retval EFI_DEVICE_ERROR KSC fails to respond.
**/
EFI_STATUS
MultiPlatformGpioProgram (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
#if !_SIMIC_
CFIO_INIT_STRUCT* PlatformCfioDataPtr;
PlatformCfioDataPtr = (CFIO_INIT_STRUCT *) (UINTN) PlatformInfoHob->PlatformCfioData;
DEBUG ((EFI_D_INFO, "MultiPlatformGpioProgram()...\n"));
//
// SCORE GPIO WELL -- IO base registers
//
//
// GPIO_USE_SEL Register -> 1 = GPIO 0 = Native
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, PlatformCfioDataPtr->Use_Sel_SC0);
//
// Set GP_LVL Register
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL , PlatformCfioDataPtr->GP_Lvl_SC0);
//
// GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL, PlatformCfioDataPtr->Io_Sel_SC0);
//
// GPIO Triger Positive Edge Enable Register
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE, PlatformCfioDataPtr->TPE_SC0);
//
// GPIO Trigger Negative Edge Enable Register
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE, PlatformCfioDataPtr->TNE_SC0);
//
// GPIO Trigger Status
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS, PlatformCfioDataPtr->TS_SC0);
//
// GPIO_USE_SEL2 Register -> 1 = GPIO 0 = Native
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2, PlatformCfioDataPtr->Use_Sel_SC1);
//
// Set GP_LVL2 Register
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2, PlatformCfioDataPtr->GP_Lvl_SC1);
//
// GP_IO_SEL2 Register -> 1 = Input 0 = Output. If Native Mode don't care
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2, PlatformCfioDataPtr->Io_Sel_SC1);
//
// GPIO_USE_SEL3 Register -> 1 = GPIO 0 = Native
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3, PlatformCfioDataPtr->Use_Sel_SC2);
//
// Set GP_LVL3 Register
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL3, PlatformCfioDataPtr->GP_Lvl_SC2);
//
// GP_IO_SEL3 Register -> 1 = Input 0 = Output if Native Mode don't care
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL3, PlatformCfioDataPtr->Io_Sel_SC2);
//
// SUS GPIO WELL -- IO base registers
//
//
// GPIO_USE_SEL Register -> 1 = GPIO 0 = Native
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_USE_SEL, PlatformCfioDataPtr->Use_Sel_SS);
//
// Set GP_LVL Register
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_LVL , PlatformCfioDataPtr->GP_Lvl_SS);
//
// GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care.
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_IO_SEL, PlatformCfioDataPtr->Io_Sel_SS);
//
// GPIO Triger Positive Edge Enable Register.
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TPE, PlatformCfioDataPtr->TPE_SS);
//
// GPIO Trigger Negative Edge Enable Register.
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TNE, PlatformCfioDataPtr->TNE_SS);
//
// GPIO Trigger Status.
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS, PlatformCfioDataPtr->TS_SS);
//
// GPIO Wake Enable.
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN, PlatformCfioDataPtr->WE_SS);
//
// Config SC/NC/SUS GPIO Pins
//
switch (PlatformInfoHob->BoardId) {
case BOARD_ID_MINNOW2:
DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));
InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SC);
InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);
InternalGpioConfig(GPIO_SSUS_OFFSET, sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SUS);
break;
default:
break;
}
//
// configure the CFIO Pnp settings
//
if (PlatformInfoHob->CfioEnabled) {
if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2){

329
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h Normal file
View File

@@ -0,0 +1,329 @@
/**@file
Gpio setting for multiplatform.
This file includes package header files, library classes.
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _BOARDGPIOS_H_
#define _BOARDGPIOS_H_
#include <PiPei.h>
#include "PchAccess.h"
#include "PlatformBaseAddresses.h"
#include <../MultiPlatformLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Guid/PlatformInfo.h>
#include <Ppi/Smbus.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Guid/SetupVariable.h>
GPIO_CONF_PAD_INIT mNB_BB_FAB3_GpioInitData_SC_TRI[] =
{
// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
GPIO_INIT_ITEM("PLT_CLK0 GPIOC_96 " ,TRISTS ,NA ,F0 , , ,NONE ,0x6a),
GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99 " ,TRISTS ,NA ,F0 , , ,NONE ,0x68),
};
//
// Minnow2
//
#define MINNOW2_GPIO_USE_SEL_VAL_0_31 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_32_63 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_SUS 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_SUS2 0x00000007
#define MINNOW2_GPIO_IO_SEL_VAL_0_31 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_32_63 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_SUS 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_SUS2 0x00000007
#define MINNOW2_GPIO_LVL_VAL_0_31 0x00000000
#define MINNOW2_GPIO_LVL_VAL_32_63 0x00000000
#define MINNOW2_GPIO_LVL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_LVL_VAL_SUS 0x00000000
#define MINNOW2_GPIO_LVL_VAL_SUS2 0x00000007
#define MINNOW2_GPIO_TPE_VAL_0_31 0x00000000
#define MINNOW2_GPIO_TPE_VAL_SUS 0x00000000
#define MINNOW2_GPIO_TPE_VAL_SUS2 0x00000007
#define MINNOW2_GPIO_TNE_VAL_0_31 0x00000000
#define MINNOW2_GPIO_TNE_VAL_SUS 0x00000000
#define MINNOW2_GPIO_TNE_VAL_SUS2 0x00000007
#define MINNOW2_GPIO_TS_VAL_0_31 0x00000000
#define MINNOW2_GPIO_TS_VAL_SUS 0x00000000
#define MINNOW2_GPIO_TS_VAL_SUS2 0x00000007
static CFIO_INIT_STRUCT mMinnow2CfioInitData =
{
MINNOW2_GPIO_USE_SEL_VAL_0_31,
MINNOW2_GPIO_USE_SEL_VAL_32_63,
MINNOW2_GPIO_USE_SEL_VAL_64_70,
MINNOW2_GPIO_USE_SEL_VAL_SUS,
MINNOW2_GPIO_IO_SEL_VAL_0_31,
MINNOW2_GPIO_IO_SEL_VAL_32_63,
MINNOW2_GPIO_IO_SEL_VAL_64_70,
MINNOW2_GPIO_IO_SEL_VAL_SUS,
MINNOW2_GPIO_LVL_VAL_0_31,
MINNOW2_GPIO_LVL_VAL_32_63,
MINNOW2_GPIO_LVL_VAL_64_70,
MINNOW2_GPIO_LVL_VAL_SUS,
MINNOW2_GPIO_TPE_VAL_0_31,
MINNOW2_GPIO_TPE_VAL_SUS,
MINNOW2_GPIO_TNE_VAL_0_31,
MINNOW2_GPIO_TNE_VAL_SUS,
MINNOW2_GPIO_TS_VAL_0_31,
MINNOW2_GPIO_TS_VAL_SUS
};
static CFIO_INIT_STRUCT mMinnow2CfioInitData2 =
{
MINNOW2_GPIO_USE_SEL_VAL_0_31,
MINNOW2_GPIO_USE_SEL_VAL_32_63,
MINNOW2_GPIO_USE_SEL_VAL_64_70,
MINNOW2_GPIO_USE_SEL_VAL_SUS2,
MINNOW2_GPIO_IO_SEL_VAL_0_31,
MINNOW2_GPIO_IO_SEL_VAL_32_63,
MINNOW2_GPIO_IO_SEL_VAL_64_70,
MINNOW2_GPIO_IO_SEL_VAL_SUS2,
MINNOW2_GPIO_LVL_VAL_0_31,
MINNOW2_GPIO_LVL_VAL_32_63,
MINNOW2_GPIO_LVL_VAL_64_70,
MINNOW2_GPIO_LVL_VAL_SUS2,
MINNOW2_GPIO_TPE_VAL_0_31,
MINNOW2_GPIO_TPE_VAL_SUS2,
MINNOW2_GPIO_TNE_VAL_0_31,
MINNOW2_GPIO_TNE_VAL_SUS2,
MINNOW2_GPIO_TS_VAL_0_31,
MINNOW2_GPIO_TS_VAL_SUS2
};
static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_NC[] =
{
// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
GPIO_INIT_ITEM("HV_DDI0_HPD GPIONC_0 " ,Native ,NA ,F2 , , ,NONE ,0x13),
GPIO_INIT_ITEM("HV_DDI0_DDC_SDA GPIONC_1 " ,Native ,NA ,F2 , , ,NONE ,0x12),
GPIO_INIT_ITEM("HV_DDI0_DDC_SCL GPIONC_2 " ,Native ,NA ,F2 , , ,NONE ,0x11),
GPIO_INIT_ITEM("PANEL0_VDDEN GPIONC_3 " ,GPIO ,NA ,F0 , , ,NONE ,0x14),
GPIO_INIT_ITEM("PANEL0_BKLTEN GPIONC_4 " ,GPIO ,NA ,F0 , , ,NONE ,0x15),
GPIO_INIT_ITEM("PANEL0_BKLTCTL GPIONC_5 " ,GPIO ,NA ,F0 , , ,NONE ,0x16),
GPIO_INIT_ITEM("HV_DDI1_HPD GPIONC_6 " ,GPI ,NA ,F0 , , ,20K_L ,0x18),
GPIO_INIT_ITEM("HV_DDI1_DDC_SDA GPIONC_7 " ,Native ,NA ,F2 , , ,20K_L ,0x19),
GPIO_INIT_ITEM("HV_DDI1_DDC_SCL GPIONC_8 " ,GPI ,NA ,F0 , , ,20K_L ,0x17),
GPIO_INIT_ITEM("PANEL1_VDDEN GPIONC_9 " ,GPIO ,NA ,F0 , , ,NONE ,0x10),
GPIO_INIT_ITEM("PANEL1_BKLTEN GPIONC_10" ,GPIO ,NA ,F0 , , ,NONE ,0x0e),
GPIO_INIT_ITEM("PANEL1_BKLTCTL GPIONC_11" ,GPIO ,NA ,F0 , , ,NONE ,0x0f),
GPIO_INIT_ITEM("GP_INTD_DSI_TE1 GPIONC_12" ,GPO ,NA ,F0 , , ,NONE ,0x0c),
GPIO_INIT_ITEM("HV_DDI2_DDC_SDA GPIONC_13" ,GPI ,NA ,F0 , , ,10K_L ,0x1a),
GPIO_INIT_ITEM("HV_DDI2_DDC_SCL GPIONC_14" ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
GPIO_INIT_ITEM("GP_CAMERASB00 GPIONC_15" ,GPIO ,NA ,F0 , , ,NONE ,0x01),
GPIO_INIT_ITEM("GP_CAMERASB01 GPIONC_16" ,GPIO ,NA ,F0 , , ,NONE ,0x04),
GPIO_INIT_ITEM("GP_CAMERASB02 GPIONC_17" ,GPIO ,NA ,F0 , , ,NONE ,0x08),
GPIO_INIT_ITEM("GP_CAMERASB03 GPIONC_18" ,GPIO ,NA ,F0 , , ,NONE ,0x0b),
GPIO_INIT_ITEM("GP_CAMERASB04 GPIONC_19" ,GPIO ,NA ,F0 , , ,NONE ,0x00),
GPIO_INIT_ITEM("GP_CAMERASB05 GPIONC_20" ,GPIO ,NA ,F0 , , ,NONE ,0x03),
GPIO_INIT_ITEM("GP_CAMERASB06 GPIONC_21" ,GPIO ,NA ,F0 , , ,NONE ,0x06),
GPIO_INIT_ITEM("GP_CAMERASB07 GPIONC_22" ,GPIO ,NA ,F0 , , ,NONE ,0x0a),
GPIO_INIT_ITEM("GP_CAMERASB08 GPIONC_23" ,GPIO ,NA ,F0 , , ,NONE ,0x0d),
GPIO_INIT_ITEM("GP_CAMERASB09 GPIONC_24" ,GPIO ,NA ,F0 , , ,NONE ,0x02),
GPIO_INIT_ITEM("GP_CAMERASB10 GPIONC_25" ,GPIO ,NA ,F0 , , ,NONE ,0x05),
GPIO_INIT_ITEM("GP_CAMERASB11 GPIONC_26" ,GPIO ,NA ,F0 , , ,NONE ,0x09),
};
static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_SC[] = {
// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
GPIO_INIT_ITEM("SATA_GP0 GPIOC_0 " ,Native ,NA ,F1 , , ,NONE ,0x55),
GPIO_INIT_ITEM("SATA_GP1 GPIOC_1 " ,Native ,NA ,F1 , , ,NONE ,0x59),
GPIO_INIT_ITEM("SATA_LEDN GPIOC_2 " ,Native ,NA ,F1 , , ,NONE ,0x5d),
GPIO_INIT_ITEM("PCIE_CLKREQ0B GPIOC_3 " ,Native ,NA ,F1 , , ,10K_H ,0x60),
GPIO_INIT_ITEM("PCIE_CLKREQ1B GPIOC_4 " ,Native ,NA ,F1 , , ,10K_H ,0x63),
GPIO_INIT_ITEM("PCIE_CLKREQ2B GPIOC_5 " ,Native ,NA ,F1 , , ,10K_H ,0x66),
GPIO_INIT_ITEM("PCIE_CLKREQ3B GPIOC_6 " ,GPIO ,NA ,F0 , , ,NONE ,0x62),
GPIO_INIT_ITEM("SDMMC3_WP GPIOC_7 " ,Native ,NA ,F2 , , ,NONE ,0x65),
GPIO_INIT_ITEM("HDA_RSTB GPIOC_8 " ,GPIO ,NA ,F0 , , ,NONE ,0x22),
GPIO_INIT_ITEM("HDA_SYNC GPIOC_9 " ,GPIO ,NA ,F0 , , ,NONE ,0x25),
GPIO_INIT_ITEM("HDA_CLK GPIOC_10 " ,GPIO ,NA ,F0 , , ,NONE ,0x24),
GPIO_INIT_ITEM("HDA_SDO GPIOC_11 " ,GPIO ,NA ,F0 , , ,NONE ,0x26),
GPIO_INIT_ITEM("HDA_SDI0 GPIOC_12 " ,GPIO ,NA ,F0 , , ,NONE ,0x27),
GPIO_INIT_ITEM("HDA_SDI1 GPIOC_13 " ,GPIO ,NA ,F0 , , ,NONE ,0x23),
GPIO_INIT_ITEM("HDA_DOCKRSTB GPIOC_14 " ,GPIO ,NA ,F0 , , ,NONE ,0x28),
GPIO_INIT_ITEM("HDA_DOCKENB GPIOC_15 " ,GPIO ,NA ,F0 , , ,NONE ,0x54),
GPIO_INIT_ITEM("SDMMC1_CLK GPIOC_16 " ,GPIO ,NA ,F0 , , ,NONE ,0x3e),
GPIO_INIT_ITEM("SDMMC1_D0 GPIOC_17 " ,GPIO ,NA ,F0 , , ,NONE ,0x3d),
GPIO_INIT_ITEM("SDMMC1_D1 GPIOC_18 " ,GPIO ,NA ,F0 , , ,NONE ,0x40),
GPIO_INIT_ITEM("SDMMC1_D2 GPIOC_19 " ,GPIO ,NA ,F0 , , ,NONE ,0x3b),
GPIO_INIT_ITEM("SDMMC1_D3_CD_B GPIOC_20 " ,GPIO ,NA ,F0 , , ,NONE ,0x36),
GPIO_INIT_ITEM("MMC1_D4_SD_WE GPIOC_21 " ,GPIO ,NA ,F0 , , ,NONE ,0x38),
GPIO_INIT_ITEM("MMC1_D5 GPIOC_22 " ,GPIO ,NA ,F0 , , ,NONE ,0x3c),
GPIO_INIT_ITEM("MMC1_D6 GPIOC_23 " ,GPIO ,NA ,F0 , , ,NONE ,0x37),
GPIO_INIT_ITEM("MMC1_D7 GPIOC_24 " ,GPIO ,NA ,F0 , , ,NONE ,0x3f),
GPIO_INIT_ITEM("SDMMC1_CMD GPIOC_25 " ,GPIO ,NA ,F0 , , ,NONE ,0x39),
GPIO_INIT_ITEM("MMC1_RESET_B GPIOC_26 " ,GPIO ,NA ,F0 , , ,NONE ,0x33),
GPIO_INIT_ITEM("SDMMC2_CLK GPIOC_27 " ,GPIO ,NA ,F0 , , ,NONE ,0x32),
GPIO_INIT_ITEM("SDMMC2_D0 GPIOC_28 " ,GPIO ,NA ,F0 , , ,NONE ,0x35),
GPIO_INIT_ITEM("SDMMC2_D1 GPIOC_29 " ,GPIO ,NA ,F0 , , ,NONE ,0x2f),
GPIO_INIT_ITEM("SDMMC2_D2 GPIOC_30 " ,GPIO ,NA ,F0 , , ,NONE ,0x34),
GPIO_INIT_ITEM("SDMMC2_D3_CD_B GPIOC_31 " ,GPIO ,NA ,F0 , , ,NONE ,0x31),
GPIO_INIT_ITEM("SDMMC2_CMD GPIOC_32 " ,GPIO ,NA ,F0 , , ,NONE ,0x30),
//
//Just for test, We make the setting that all is same with Bayleybay.
//
GPIO_INIT_ITEM("SDMMC3_CLK GPIOC_33 " ,Native ,NA ,F1 , , ,NONE ,0x2b),
GPIO_INIT_ITEM("SDMMC3_D0 GPIOC_34 " ,Native ,NA ,F1 , , ,NONE ,0x2e),
GPIO_INIT_ITEM("SDMMC3_D1 GPIOC_35 " ,Native ,NA ,F1 ,YES , ,NONE ,0x29),
GPIO_INIT_ITEM("SDMMC3_D2 GPIOC_36 " ,Native ,NA ,F1 , , ,NONE ,0x2d),
GPIO_INIT_ITEM("SDMMC3_D3 GPIOC_37 " ,Native ,NA ,F1 , , ,NONE ,0x2a),
GPIO_INIT_ITEM("SDMMC3_CD_B GPIOC_38 " ,Native ,NA ,F1 ,YES ,Edge_Both ,NONE ,0x3a),
GPIO_INIT_ITEM("SDMMC3_CMD GPIOC_39 " ,Native ,NA ,F1 , , ,NONE ,0x2c),
GPIO_INIT_ITEM("SDMMC3_1P8_EN GPIOC_40 " ,Native ,NA ,F1 , , ,NONE ,0x5f),
GPIO_INIT_ITEM("SDMMC3_PWR_EN_B GPIOC_41 " ,Native ,NA ,F1 , , ,NONE ,0x69),
GPIO_INIT_ITEM("LPC_AD0 GPIOC_42 " ,GPIO ,NA ,F0 , , ,NONE ,0x46),
GPIO_INIT_ITEM("LPC_AD1 GPIOC_43 " ,GPIO ,NA ,F0 , , ,NONE ,0x44),
GPIO_INIT_ITEM("LPC_AD2 GPIOC_44 " ,GPIO ,NA ,F0 , , ,NONE ,0x43),
GPIO_INIT_ITEM("LPC_AD3 GPIOC_45 " ,GPIO ,NA ,F0 , , ,NONE ,0x42),
GPIO_INIT_ITEM("LPC_FRAMEB GPIOC_46 " ,GPIO ,NA ,F0 , , ,NONE ,0x45),
GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,GPIO ,NA ,F0 , , ,NONE ,0x47),
GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,GPIO ,NA ,F0 , , ,NONE ,0x41),
GPIO_INIT_ITEM("LPC_CLKRUNB GPIOC_49 " ,GPIO ,NA ,F0 , , ,NONE ,0x48),
GPIO_INIT_ITEM("ILB_SERIRQ GPIOC_50 " ,GPIO ,NA ,F0 , , ,NONE ,0x56),
GPIO_INIT_ITEM("SMB_DATA GPIOC_51 " ,Native ,NA ,F1 , , ,NONE ,0x5a),
GPIO_INIT_ITEM("SMB_CLK GPIOC_52 " ,Native ,NA ,F1 , , ,NONE ,0x58),
GPIO_INIT_ITEM("SMB_ALERTB GPIOC_53 " ,Native ,NA ,F1 , , ,10K_H ,0x5c),
GPIO_INIT_ITEM("SPKR GPIOC_54 " ,GPI ,NA ,F0 , , ,20K_H ,0x67),
GPIO_INIT_ITEM("MHSI_ACDATA GPIOC_55 " ,GPIO ,NA ,F0 , , ,NONE ,0x4d),
GPIO_INIT_ITEM("MHSI_ACFLAG GPIOC_56 " ,GPI ,NA ,F0 , , ,20K_H ,0x4f),
GPIO_INIT_ITEM("MHSI_ACWAKE GPIOC_58 " ,GPIO ,NA ,F0 , , ,NONE ,0x4e),
GPIO_INIT_ITEM("MHSI_CADATA GPIOC_59 " ,GPIO ,NA ,F0 , , ,NONE ,0x51),
GPIO_INIT_ITEM("MHSI_CAFLAG GPIOC_60 " ,GPO ,HI ,F0 , , ,20K_H ,0x50),
GPIO_INIT_ITEM("GP_SSP_2_CLK GPIOC_62 " ,GPI ,NA ,F0 , , ,20K_H ,0x0d),
GPIO_INIT_ITEM("GP_SSP_2_FS GPIOC_63 " ,GPI ,NA ,F0 , , ,20K_H ,0x0c),
GPIO_INIT_ITEM("GP_SSP_2_RXD GPIOC_64 " ,GPI ,NA ,F0 , , ,20K_H ,0x0f),
GPIO_INIT_ITEM("GP_SSP_2_TXD GPIOC_65 " ,GPI ,NA ,F0 , , ,20K_H ,0x0e),
GPIO_INIT_ITEM("SPI1_CS0_B GPIOC_66 " ,Native ,NA ,F1 , , ,20K_H ,0x11),
GPIO_INIT_ITEM("SPI1_MISO GPIOC_67 " ,Native ,NA ,F1 , , ,20K_H ,0x12),
GPIO_INIT_ITEM("SPI1_MOSI GPIOC_68 " ,Native ,NA ,F1 , , ,20K_H ,0x13),
GPIO_INIT_ITEM("SPI1_CLK GPIOC_69 " ,Native ,NA ,F1 , , ,20K_H ,0x10),
GPIO_INIT_ITEM("UART1_RXD GPIOC_70 " ,Native ,NA ,F1 , , ,20K_H ,0x02),
GPIO_INIT_ITEM("UART1_TXD GPIOC_71 " ,Native ,NA ,F1 , , ,20K_H ,0x01),
GPIO_INIT_ITEM("UART1_RTS_B GPIOC_72 " ,GPI ,NA ,F0 , , ,20K_H ,0x00),
GPIO_INIT_ITEM("UART1_CTS_B GPIOC_73 " ,GPI ,NA ,F0 , , ,20K_H ,0x04),
GPIO_INIT_ITEM("UART2_RXD GPIOC_74 " ,Native ,NA ,F1 , , ,20K_H ,0x06),
GPIO_INIT_ITEM("UART2_TXD GPIOC_75 " ,Native ,NA ,F1 , , ,20K_H ,0x07),
GPIO_INIT_ITEM("UART2_RTS_B GPIOC_76 " ,GPIO ,NA ,F0 , , ,NONE ,0x09),
GPIO_INIT_ITEM("UART2_CTS_B GPIOC_77 " ,Native ,NA ,F1 , , ,20K_H ,0x08),
GPIO_INIT_ITEM("I2C0_SDA GPIOC_78 " ,GPIO ,NA ,F0 , , ,NONE ,0x21),
GPIO_INIT_ITEM("I2C0_SCL GPIOC_79 " ,GPIO ,NA ,F0 , , ,NONE ,0x20),
GPIO_INIT_ITEM("I2C1_SDA GPIOC_80 " ,Native ,NA ,F1 , , ,NONE ,0x1f),
GPIO_INIT_ITEM("I2C1_SCL GPIOC_81 " ,Native ,NA ,F1 , , ,NONE ,0x1e),
GPIO_INIT_ITEM("I2C2_SDA GPIOC_82 " ,GPIO ,NA ,F0 , , ,NONE ,0x1d),
GPIO_INIT_ITEM("I2C2_SCL GPIOC_83 " ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
GPIO_INIT_ITEM("I2C3_SDA GPIOC_84 " ,GPIO ,NA ,F0 , , ,NONE ,0x19),
GPIO_INIT_ITEM("I2C3_SCL GPIOC_85 " ,GPIO ,NA ,F0 , , ,NONE ,0x1c),
GPIO_INIT_ITEM("I2C4_SDA GPIOC_86 " ,Native ,NA ,F1 , , ,20K_H ,0x1a),
GPIO_INIT_ITEM("I2C4_SCL GPIOC_87 " ,GPIO ,NA ,F0 , , ,NONE ,0x17),
GPIO_INIT_ITEM("I2C5_SDA GPIOC_88 " ,Native ,NA ,F1 , , ,20K_H ,0x15),
GPIO_INIT_ITEM("I2C5_SCL GPIOC_89 " ,Native ,NA ,F1 , , ,20K_H ,0x14),
GPIO_INIT_ITEM("I2C6_SDA GPIOC_90 " ,Native ,NA ,F1 , , ,20K_H ,0x18),
GPIO_INIT_ITEM("I2C6_SCL GPIOC_91 " ,Native ,NA ,F1 , , ,20K_H ,0x16),
GPIO_INIT_ITEM("I2C_NFC_SDA GPIOC_92 " ,GPIO ,NA ,F1 , , ,NONE ,0x05),
GPIO_INIT_ITEM("I2C_NFC_SCL GPIOC_93 " ,GPO ,LO ,F1 , , ,NONE ,0x03),
GPIO_INIT_ITEM("PWM0 GPIOC_94 " ,Native ,NA ,F1 , , ,20K_L ,0x0a),
GPIO_INIT_ITEM("PWM1 GPIOC_95 " ,Native ,NA ,F1 , , ,20K_L ,0x0b),
GPIO_INIT_ITEM("PLT_CLK0 GPIOC_96 " ,GPIO ,NA ,F0 , , ,NONE ,0x6a),
GPIO_INIT_ITEM("PLT_CLK1 GPIOC_97 " ,GPIO ,NA ,F0 , , ,NONE ,0x57),
GPIO_INIT_ITEM("PLT_CLK2 GPIOC_98 " ,GPIO ,NA ,F0 , , ,NONE ,0x5b),
GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99 " ,GPIO ,NA ,F0 , , ,NONE ,0x68),
GPIO_INIT_ITEM("PLT_CLK4 GPIOC_100" ,GPIO ,NA ,F0 , , ,NONE ,0x61),
GPIO_INIT_ITEM("PLT_CLK5 GPIOC_101" ,GPIO ,NA ,F0 , , ,NONE ,0x64),
};
static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_SUS[] = {
// Pad Name GPIO Number Used As GPIO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
GPIO_INIT_ITEM("GPIO_SUS0 GPIO_SUS0" ,GPI ,NA ,F0 , , ,20K_H ,0x1d),
GPIO_INIT_ITEM("GPIO_SUS1 GPIO_SUS1" ,GPI ,NA ,F0 , , ,20K_H ,0x21),
GPIO_INIT_ITEM("GPIO_SUS2 GPIO_SUS2" ,GPI ,NA ,F0 , , ,20K_H ,0x1e),
GPIO_INIT_ITEM("GPIO_SUS3 GPIO_SUS3" ,Native ,NA ,F6 ,YES ,Level_Low ,2K_H ,0x1f),
GPIO_INIT_ITEM("GPIO_SUS4 GPIO_SUS4" ,GPIO ,NA ,F0 , , ,NONE ,0x20),
GPIO_INIT_ITEM("GPIO_SUS5 GPIO_SUS5" ,GPI ,NA ,F0 , , ,NONE ,0x22),
GPIO_INIT_ITEM("GPIO_SUS6 GPIO_SUS6" ,GPI ,NA ,F0 , , ,NONE ,0x24),
GPIO_INIT_ITEM("GPIO_SUS7 GPIO_SUS7" ,GPI ,NA ,F0 , , ,NONE ,0x23),
GPIO_INIT_ITEM("SEC_GPIO_SUS8 GPIO_SUS8" ,GPO ,HI ,F0 , , ,20K_H ,0x26),
GPIO_INIT_ITEM("SEC_GPIO_SUS9 GPIO_SUS9" ,GPO ,HI ,F0 , , ,20K_H ,0x25),
GPIO_INIT_ITEM("SEC_GPIO_SUS10 GPIO_SUS10" ,GPO ,HI ,F0 , , ,NONE ,0x12),
GPIO_INIT_ITEM("SUSPWRDNACK GPIOS_11 " ,Native ,NA ,F0 , , ,10K_H ,0x07),
GPIO_INIT_ITEM("PMU_SUSCLK GPIOS_12 " ,Native ,NA ,F0 , , ,NONE ,0x0b),
GPIO_INIT_ITEM("PMU_SLP_S0IX_B GPIOS_13 " ,Native ,NA ,F0 , , ,NONE ,0x14),
GPIO_INIT_ITEM("PMU_SLP_LAN_B GPIOS_14 " ,GPO ,LO ,F1 , , ,10K_H ,0x11),
GPIO_INIT_ITEM("PMU_WAKE_B GPIOS_15 " ,Native ,NA ,F0 , , ,20K_H ,0x01),
GPIO_INIT_ITEM("PMU_PWRBTN_B GPIOS_16 " ,Native ,NA ,F0 , , ,20K_H ,0x08),
GPIO_INIT_ITEM("PMU_WAKE_LAN_B GPIOS_17 " ,GPIO ,NA ,F1 , , ,NONE ,0x0a),
GPIO_INIT_ITEM("SUS_STAT_B GPIOS_18 " ,GPO ,NA ,F1 , , ,NONE ,0x13),
GPIO_INIT_ITEM("USB_OC0_B GPIOS_19 " ,Native ,NA ,F0 , , ,10K_H ,0x0c),
GPIO_INIT_ITEM("USB_OC1_B GPIOS_20 " ,Native ,NA ,F0 , , ,10K_H ,0x00),
GPIO_INIT_ITEM("SPI_CS1_B GPIOS_21 " ,Native ,NA ,F0 , , ,NONE ,0x02),
GPIO_INIT_ITEM("GPIO_DFX0 GPIOS_22 " ,GPIO ,NA ,F0 , , ,NONE ,0x17),
GPIO_INIT_ITEM("GPIO_DFX1 GPIOS_23 " ,GPIO ,NA ,F0 , , ,NONE ,0x27),
GPIO_INIT_ITEM("GPIO_DFX2 GPIOS_24 " ,GPIO ,NA ,F0 , , ,NONE ,0x1c),
GPIO_INIT_ITEM("GPIO_DFX3 GPIOS_25 " ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
GPIO_INIT_ITEM("GPIO_DFX4 GPIOS_26 " ,GPIO ,NA ,F0 , , ,NONE ,0x16),
GPIO_INIT_ITEM("GPIO_DFX5 GPIOS_27 " ,GPI ,NA ,F0 , , ,20K_H ,0x15),
GPIO_INIT_ITEM("GPIO_DFX6 GPIOS_28 " ,GPI ,NA ,F0 , , ,20K_H ,0x18),
GPIO_INIT_ITEM("GPIO_DFX7 GPIOS_29 " ,GPI ,NA ,F0 , , ,20K_H ,0x19),
GPIO_INIT_ITEM("GPIO_DFX8 GPIOS_30 " ,GPI ,NA ,F0 , , ,20K_H ,0x1a),
GPIO_INIT_ITEM("USB_ULPI_0_CLK GPIOS_31 " ,GPIO ,NA ,F0 , , ,NONE ,0x33),
GPIO_INIT_ITEM("USB_ULPI_0_DATA0 GPIOS_32 " ,GPIO ,NA ,F0 , , ,NONE ,0x38),
GPIO_INIT_ITEM("USB_ULPI_0_DATA1 GPIOS_33 " ,GPIO ,NA ,F0 , , ,NONE ,0x36),
GPIO_INIT_ITEM("USB_ULPI_0_DATA2 GPIOS_34 " ,GPIO ,NA ,F0 , , ,NONE ,0x31),
GPIO_INIT_ITEM("USB_ULPI_0_DATA3 GPIOS_35 " ,GPIO ,NA ,F0 , , ,NONE ,0x37),
GPIO_INIT_ITEM("USB_ULPI_0_DATA4 GPIOS_36 " ,GPIO ,NA ,F0 , , ,NONE ,0x30),
GPIO_INIT_ITEM("USB_ULPI_0_DATA5 GPIOS_37 " ,GPIO ,NA ,F0 , , ,NONE ,0x39),
GPIO_INIT_ITEM("USB_ULPI_0_DATA6 GPIOS_38 " ,GPIO ,NA ,F0 , , ,NONE ,0x32),
GPIO_INIT_ITEM("USB_ULPI_0_DATA7 GPIOS_39 " ,GPIO ,NA ,F0 , , ,NONE ,0x3a),
GPIO_INIT_ITEM("USB_ULPI_0_DIR GPIOS_40 " ,GPIO ,NA ,F0 , , ,NONE ,0x34),
GPIO_INIT_ITEM("USB_ULPI_0_NXT GPIOS_41 " ,GPIO ,NA ,F0 , , ,NONE ,0x35),
GPIO_INIT_ITEM("USB_ULPI_0_STP GPIOS_42 " ,GPIO ,NA ,F0 , , ,NONE ,0x3b),
GPIO_INIT_ITEM("USB_ULPI_0_REFCLK GPIOS_43 " ,GPIO ,NA ,F0 , , ,NONE ,0x28),
};
EFI_STATUS
MultiPlatformGpioTableInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob

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/** @file
Jumper setting for multiplatform.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <BoardJumpers.h>
BOOLEAN
IsRecoveryJumper (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
return FALSE;
}

35
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.h Normal file
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/**@file
Jumper setting for multiplatform.
This file includes package header files, library classes.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _BOARDJUMPERS_H_
#define _BOARDJUMPERS_H_
#include <PiPei.h>
#include "PchAccess.h"
#include "PlatformBaseAddresses.h"
#include <Library/IoLib.h>
#include <Library/DebugLib.h>

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/** @file
ACPI oem ids setting for multiplatform.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <BoardOemIds.h>
//
// Global module data
//
EFI_STATUS
InitializeBoardOemId (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
UINT64 OemId;
UINT64 OemTableId;
//
// Set OEM ID according to Board ID.
//
switch (PlatformInfoHob->BoardId) {
case BOARD_ID_MINNOW2:
default:
OemId = EFI_ACPI_OEM_ID_DEFAULT;

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/**@file
ACPI oem ids setting for multiplatform.
This file includes package header files, library classes.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Guid/PlatformInfo.h>
#include <Library/BaseMemoryLib.h>
#define EFI_ACPI_OEM_ID_DEFAULT SIGNATURE_64('I', 'N', 'T', 'E', 'L', ' ', ' ', ' ') // max 6 chars
#define EFI_ACPI_OEM_ID1 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '1', ' ', ' ') // max 6 chars
#define EFI_ACPI_OEM_ID2 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '2', ' ', ' ') // max 6 chars
#define EFI_ACPI_OEM_TABLE_ID_DEFAULT SIGNATURE_64('E', 'D', 'K', '2', ' ', ' ', ' ', ' ')

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/** @file
Subsystem IDs setting for multiplatform.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <BoardSsidSvid.h>
//
// Global module data
//
EFI_STATUS
InitializeBoardSsidSvid (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
UINT32 SsidSvidValue = 0;
//
// Set OEM ID according to Board ID.
//
switch (PlatformInfoHob->BoardId) {

40
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h Normal file
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/**@file
Subsystem IDs setting for multiplatform.
This file includes package header files, library classes.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Guid/PlatformInfo.h>
#include <Library/BaseMemoryLib.h>
//
// Default Vendor ID and Subsystem ID
//
#define SUBSYSTEM_VENDOR_ID1 0x8086
#define SUBSYSTEM_DEVICE_ID1 0x1999
#define SUBSYSTEM_SVID_SSID1 (SUBSYSTEM_VENDOR_ID1 + (SUBSYSTEM_DEVICE_ID1 << 16))
#define SUBSYSTEM_VENDOR_ID2 0x8086
#define SUBSYSTEM_DEVICE_ID2 0x1888
#define SUBSYSTEM_SVID_SSID2 (SUBSYSTEM_VENDOR_ID2 + (SUBSYSTEM_DEVICE_ID2 << 16))

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/** @file
Multiplatform initialization.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <MultiPlatformLib.h>
/**
Platform Type detection. Because the PEI globle variable
is in the flash, it could not change directly.So use
2 PPIs to distinguish the platform type.
@param FfsHeader Pointer to Firmware File System file header.
@param PeiServices General purpose services available to every PEIM.
@retval EFI_SUCCESS Memory initialization completed successfully.
@retval Others All other error conditions encountered result in an ASSERT.
**/
EFI_STATUS
MultiPlatformInfoInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
UINT32 PcieLength;
EFI_STATUS Status;
PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);
PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET);
//
// Update ICH Type
//
//
// Device ID
//
PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);
PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);
//
//64MB
//
PcieLength = 0x04000000;
//
// Don't support BASE above 4GB currently.
//
PlatformInfoHob->PciData.PciExpressSize = PcieLength;
PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress);
PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);
PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;
PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;
PlatformInfoHob->CpuData.CpuAddressWidth = 36;
PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;
PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;
PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;
//
// Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.
//
if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {
PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;
} else {
PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;
}
PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;
//
// Platform PCI MMIO Size in unit of 1MB.
//
PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
//
// Enable ICH IOAPIC
//
PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;
DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n", PlatformInfoHob->PlatformFlavor,FlavorTablet,FlavorMobile,FlavorDesktop));
//
// Get Platform Info and fill the Hob.
//
PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;
//
// Get GPIO table
//
Status = MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
//
// Program GPIO
//
Status = MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);

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/**@file
Multiplatform initialization header file.
This file includes package header files, library classes.
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MULTIPLATFORM_LIB_H_
#define _MULTIPLATFORM_LIB_H_
#define LEN_64M 0x4000000
//
// Default PCI32 resource size
//
#define RES_MEM32_MIN_LEN 0x38000000
#define RES_IO_BASE 0x0D00
#define RES_IO_LIMIT 0xFFFF
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <FrameworkPei.h>
#include "PlatformBaseAddresses.h"
#include "PchAccess.h"
#include "SetupMode.h"
#include "PlatformBootMode.h"
#include "Platform.h"
#include <Ppi/Stall.h>
#include <Guid/SetupVariable.h>
#include <Ppi/AtaController.h>
#include <Ppi/FindFv.h>
#include <Ppi/BootInRecoveryMode.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Ppi/Capsule.h>
#include <Guid/EfiVpdData.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Library/BaseLib.h>
#include <IndustryStandard/Pci22.h>
#include <Ppi/Speaker.h>
#include <Guid/FirmwareFileSystem.h>
#include <Guid/MemoryTypeInformation.h>
#include <Ppi/Cache.h>
#include <Ppi/Reset.h>
#include <Ppi/EndOfPeiPhase.h>
#include <Ppi/MemoryDiscovered.h>
#include <Guid/GlobalVariable.h>
#include <Ppi/RecoveryModule.h>
#include <Ppi/DeviceRecoveryModule.h>
#include <Guid/Capsule.h>
#include <Guid/RecoveryDevice.h>
#include <Ppi/MasterBootMode.h>
#include <Guid/PlatformInfo.h>
#include <BoardOemIds/BoardOemIds.h>
#include <BoardSsidSvid/BoardSsidSvid.h>
EFI_STATUS
GetPlatformInfoHob (
IN CONST EFI_PEI_SERVICES **PeiServices,
OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
);
EFI_STATUS
MultiPlatformGpioTableInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob

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#
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
# Module Name:
#
# MultiPlatform.inf
#
# Abstract:
#
#
--*/
[defines]
INF_VERSION = 0x00010005
BASE_NAME = MultiPlatformLib
FILE_GUID = AB83A52B-B44A-462c-B099-444CC0ED274D
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
LIBRARY_CLASS = MultiPlatformLib
PI_SPECIFICATION_VERSION = 0x0001000A
[sources]
MultiPlatformLib.c
MultiPlatformLib.h
PlatformInfoHob.c
#GPIO
BoardGpios/BoardGpios.c
BoardGpios/BoardGpios.h
#ClkGen
BoardClkGens/BoardClkGens.c
BoardClkGens/BoardClkGens.h
#Jumper
BoardJumpers/BoardJumpers.c
BoardJumpers/BoardJumpers.h
#OemId
BoardOemIds/BoardOemIds.c
BoardOemIds/BoardOemIds.h
#SSIDSVID
BoardSsidSvid/BoardSsidSvid.c
BoardSsidSvid/BoardSsidSvid.h
[Guids]
gEfiPlatformInfoGuid # ALWAYS_CONSUMED
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec
[LibraryClasses]
DebugLib
HobLib
IoLib
# PeiKscLib

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/** @file
Platform Hob access interface for multiplatform.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <MultiPlatformLib.h>
/**
Returns the Platform Info of the platform from the HOB.
@param PeiServices General purpose services available to every PEIM.
@param PlatformInfoHob Pointer to the PLATFORM_INFO_HOB Pointer
@retval EFI_SUCCESS The function completed successfully.
@retval EFI_NOT_FOUND PlatformInfoHob data doesn't exist, use default instead.
**/
EFI_STATUS
GetPlatformInfoHob (
IN CONST EFI_PEI_SERVICES **PeiServices,
OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
)
{
EFI_PEI_HOB_POINTERS GuidHob;
//
// Find the PlatformInfo HOB
//
GuidHob.Raw = GetHobList ();
if (GuidHob.Raw == NULL) {
return EFI_NOT_FOUND;
}
if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {
*PlatformInfoHob = GET_GUID_HOB_DATA (GuidHob.Guid);
}
//
// PlatformInfo PEIM should provide this HOB data, if not ASSERT and return error.

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#
#
#/*++
#
# Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
# Module Name:
#
# PeiDxePchPlatformLib.inf
#
# Abstract:
#
# Component description file for PEI/DXE PCH Platform Lib
#
#--*/
[defines]
INF_VERSION = 0x00010005
BASE_NAME = PchPlatformLib
FILE_GUID = 32F89CBC-305D-4bdd-8B2C-9C65592E66AC
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PchPlatformLib
[sources.common]
PchPlatformLibrary.h
PchPlatformLibrary.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
[LibraryClasses]
BaseLib
PciLib
IoLib

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/**
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchPlatformLib.c
@brief
PCH Platform Lib implementation.
**/
#include "PchPlatformLibrary.h"
//
// Silicon Steppings
//
/**
Return Pch stepping type
@param[in] None
@retval PCH_STEPPING Pch stepping type
**/
PCH_STEPPING
EFIAPI
PchStepping (
VOID
)
{
UINT8 RevId;
RevId = MmioRead8 (
MmPciAddress (0,
DEFAULT_PCI_BUS_NUMBER_PCH,
PCI_DEVICE_NUMBER_PCH_LPC,
PCI_FUNCTION_NUMBER_PCH_LPC,
R_PCH_LPC_RID_CC)
);
switch (RevId) {
case V_PCH_LPC_RID_0:
case V_PCH_LPC_RID_1:
return PchA0;
break;
case V_PCH_LPC_RID_2:
case V_PCH_LPC_RID_3:
return PchA1;
break;
case V_PCH_LPC_RID_4:
case V_PCH_LPC_RID_5:
return PchB0;
break;
case V_PCH_LPC_RID_6:
case V_PCH_LPC_RID_7:
return PchB1;
break;
case V_PCH_LPC_RID_8:
case V_PCH_LPC_RID_9:
return PchB2;
break;
case V_PCH_LPC_RID_A:
case V_PCH_LPC_RID_B:
return PchB3;
break;
case V_PCH_LPC_RID_C:
case V_PCH_LPC_RID_D:
return PchC0;
break;
default:
return PchSteppingMax;
break;
}
}
/**
Determine if PCH is supported
@param[in] None
@retval TRUE PCH is supported
@retval FALSE PCH is not supported
**/
BOOLEAN
IsPchSupported (
VOID
)
{
UINT32 Identifiers;
UINT16 PcuVendorId;
UINT16 PcuDeviceId;
Identifiers = MmioRead32 (
MmPciAddress (0,
DEFAULT_PCI_BUS_NUMBER_PCH,
PCI_DEVICE_NUMBER_PCH_LPC,
PCI_FUNCTION_NUMBER_PCH_LPC,
R_PCH_LPC_REG_ID)
);
PcuDeviceId = (UINT16) ((Identifiers & B_PCH_LPC_DEVICE_ID) >> 16);
PcuVendorId = (UINT16) (Identifiers & B_PCH_LPC_VENDOR_ID);

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/**
**/
/**
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@file
PchPlatformLibrary.h
@brief
Header file for PCH Platform Lib implementation.
**/
#ifndef _PCH_PLATFORM_LIBRARY_IMPLEMENTATION_H_
#define _PCH_PLATFORM_LIBRARY_IMPLEMENTATION_H_
#include "PchAccess.h"
#ifdef ECP_FLAG
#include "EdkIIGlueBase.h"
#include "Library/EdkIIGlueMemoryAllocationLib.h"
#else

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/**@file
Common header file shared by all source files.
This file includes package header files, library classes and protocol, PPI & GUID definitions.
Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __COMMON_HEADER_H_
#define __COMMON_HEADER_H_
#include <Base.h>
#include <Library/TimerLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>

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/** @file
PCH Smm Library Services that implements both S/W SMI generation and detection.
Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CommonHeader.h"
/**
Triggers a run time or boot time SMI.
This function triggers a software SMM interrupt and set the APMC status with an 8-bit Data.
@param Data The value to set the APMC status.
**/
VOID
InternalTriggerSmi (
IN UINT8 Data
)
{
ASSERT(FALSE);
}
/**
Triggers an SMI at boot time.
This function triggers a software SMM interrupt at boot time.
**/
VOID
EFIAPI
TriggerBootServiceSoftwareSmi (
VOID
)
{
ASSERT(FALSE);
}
/**
Triggers an SMI at run time.
This function triggers a software SMM interrupt at run time.
**/
VOID
EFIAPI
TriggerRuntimeSoftwareSmi (
VOID
)
{
ASSERT(FALSE);
}
/**
Gets the software SMI data.
This function tests if a software SMM interrupt happens. If a software SMI happens,
it retrieves the SMM data and returns it as a non-negative value; otherwise a negative
value is returned.
@return Data The data retrieved from SMM data port in case of a software SMI;
otherwise a negative value.
**/
INTN
InternalGetSwSmiData (
VOID
)
{
ASSERT(FALSE);
return -1;
}
/**
Test if a boot time software SMI happened.
This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
it was triggered at boot time, it returns TRUE. Otherwise, it returns FALSE.
@retval TRUE A software SMI triggered at boot time happened.
@retval FLASE No software SMI happened or the software SMI was triggered at run time.
**/
BOOLEAN
EFIAPI
IsBootServiceSoftwareSmi (
VOID
)
{
ASSERT(FALSE);
return FALSE;
}
/**
Test if a run time software SMI happened.
This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
it was triggered at run time, it returns TRUE. Otherwise, it returns FALSE.
@retval TRUE A software SMI triggered at run time happened.
@retval FLASE No software SMI happened or the software SMI was triggered at boot time.
**/
BOOLEAN
EFIAPI
IsRuntimeSoftwareSmi (
VOID
)
{
ASSERT(FALSE);
return FALSE;
}
/**
Clear APM SMI Status Bit; Set the EOS bit.
**/
VOID
EFIAPI
ClearSmi (
VOID
)
{
UINT16 PmBase;
//
// Get PMBase
//
PmBase = PcdGet16 (PcdPchAcpiIoPortBaseAddress);
//
// Clear the APM SMI Status Bit

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## @file
# Component description file for Intel Ich7 SMM Library.
#
# ICH SMM Library that layers on top of the I/O Library to directly
# access SMM power management registers.
# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PchSmmLib
FILE_GUID = A6A16CCB-91B0-42f4-B4F3-D17D7A5662E6
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = SmmLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
PchSmmLib.c
[Packages]
MdePkg/MdePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec

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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
BdsPlatform.h
Abstract:
Head file for BDS Platform specific code
--*/
#ifndef _BDS_PLATFORM_H
#define _BDS_PLATFORM_H
#include <FrameworkDxe.h>
#include <Protocol/FirmwareVolume2.h>
#include <Protocol/DevicePath.h>
#include <Protocol/SimpleNetwork.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/LoadFile.h>
#include <Protocol/LegacyBios.h>
#include <Protocol/PciIo.h>
#include <Protocol/SmmAccess2.h>
#include <Protocol/DxeSmmReadyToLock.h>
#include <Protocol/UserManager.h>
#include <Protocol/DeferredImageLoad.h>
#include <Protocol/AcpiS3Save.h>
#include <Protocol/ExitPmAuth.h>
#include <Protocol/MmioDevice.h>
#include <Protocol/I2cBusMcg.h>
#include <Protocol/I2cHostMcg.h>
#include <Guid/CapsuleVendor.h>
#include <Guid/MemoryTypeInformation.h>
#include <Guid/GlobalVariable.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/GenericBdsLib.h>
#include <Library/PlatformBdsLib.h>
#include <Library/DevicePathLib.h>
#include <Library/UefiLib.h>
#include <Library/HobLib.h>
#include <Library/PrintLib.h>
#include <Library/PerformanceLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <IndustryStandard/Pci.h>
extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges [];
extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [];
extern EFI_DEVICE_PATH_PROTOCOL *gPlatformAllPossiblePciVgaConsole [];
extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence [];
extern EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption [];
extern EFI_DEVICE_PATH_PROTOCOL *gPlatformBootOption [];
extern EFI_DEVICE_PATH_PROTOCOL *gUserAuthenticationDevice[];
extern BDS_CONSOLE_CONNECT_ENTRY gPlatformSimpleConsole [];
extern EFI_DEVICE_PATH_PROTOCOL *gPlatformSimpleBootOption [];
//
// the short form device path for Usb keyboard
//
#define CLASS_HID 3
#define SUBCLASS_BOOT 1
#define PROTOCOL_KEYBOARD 1
#define PCI_DEVICE_PATH_NODE(Func, Dev) \
{ \
HARDWARE_DEVICE_PATH, \
HW_PCI_DP, \
{ \
(UINT8) (sizeof (PCI_DEVICE_PATH)), \
(UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
}, \
(Func), \
(Dev) \
}
#define PNPID_DEVICE_PATH_NODE(PnpId) \
{ \
{ \
ACPI_DEVICE_PATH, \
ACPI_DP, \
{ \
(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
} \
}, \
EISA_PNP_ID((PnpId)), \
0 \
}
#define gUart(BaudRate, DataBits, Parity, StopBits) \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_UART_DP, \
{ \
(UINT8) (sizeof (UART_DEVICE_PATH)), \
(UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \
} \
}, \
0, \
(BaudRate), \
(DataBits), \
(Parity), \
(StopBits) \
}
#define gPcAnsiTerminal \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_VENDOR_DP, \
{ \
(UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
(UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
} \
}, \
DEVICE_PATH_MESSAGING_PC_ANSI \
}
#define gUsbKeyboardMouse \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_USB_CLASS_DP, \
(UINT8) (sizeof (USB_CLASS_DEVICE_PATH)), \
(UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) \
}, \
0xffff, \
0xffff, \
CLASS_HID, \
SUBCLASS_BOOT, \
PROTOCOL_KEYBOARD \
}
#define gEndEntire \
{ \
END_DEVICE_PATH_TYPE, \
END_ENTIRE_DEVICE_PATH_SUBTYPE, \
{ \
END_DEVICE_PATH_LENGTH, \
0 \
} \
}
#define gPciRootBridge \
PNPID_DEVICE_PATH_NODE(0x0A03)
#define gPnpPs2Keyboard \
PNPID_DEVICE_PATH_NODE(0x0303)
#define gPnp16550ComPort \
PNPID_DEVICE_PATH_NODE(0x0501)
#define gPciePort0Bridge \
PCI_DEVICE_PATH_NODE(0, 0x1C)
#define gPciePort1Bridge \
PCI_DEVICE_PATH_NODE(1, 0x1C)
#define gPciePort2Bridge \
PCI_DEVICE_PATH_NODE(2, 0x1C)
#define gPciePort3Bridge \
PCI_DEVICE_PATH_NODE(3, 0x1C)
#define gPciIsaBridge \
PCI_DEVICE_PATH_NODE(0, 0x1f)
//
// Platform Root Bridge
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
//
// Below is the platform console device path
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH IsaBridge;
ACPI_HID_DEVICE_PATH Keyboard;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ISA_KEYBOARD_DEVICE_PATH;
typedef struct {
VENDOR_DEVICE_PATH VendorDevicePath;
EFI_DEVICE_PATH_PROTOCOL End;
} HII_VENDOR_DEVICE_PATH;
typedef struct {
USB_CLASS_DEVICE_PATH UsbClass;
EFI_DEVICE_PATH_PROTOCOL End;
} USB_CLASS_FORMAT_DEVICE_PATH;
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH OnboardVga;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ONBOARD_VGA_DEVICE_PATH;
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH AgpBridge;
PCI_DEVICE_PATH AgpDevice;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_OFFBOARD_VGA_DEVICE_PATH;
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH IsaBridge;
ACPI_HID_DEVICE_PATH IsaSerial;
UART_DEVICE_PATH Uart;
VENDOR_DEVICE_PATH TerminalType;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ISA_SERIAL_DEVICE_PATH;
//
// Below is the boot option device path
//
typedef struct {
BBS_BBS_DEVICE_PATH LegacyHD;
EFI_DEVICE_PATH_PROTOCOL End;
} LEGACY_HD_DEVICE_PATH;
//
// Below is the platform IDE device path
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH IsaBridge;
ATAPI_DEVICE_PATH Ide;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_IDE_DEVICE_PATH;
//
// Floppy device path definition
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH IsaBridge;
ACPI_HID_DEVICE_PATH Floppy;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_FLOPPY_DEVICE_PATH;
//
// Below is the platform USB controller device path for
// USB disk as user authentication device.
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH PciDevice;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_USB_DEVICE_PATH;
//
// Below is the platform PCI device path
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH PciDevice;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_PCI_DEVICE_PATH;
typedef enum {
PMIC_Equal = 0, // = 0
PMIC_Greater_Than, // > 1
PMIC_Smaller_Than, // < 2
PMIC_Greater_Equal, // >= 3
PMIC_Smaller_Equal, // <= 4
PMIC_Any // don't care 5
} PMIC_Condition_list;
typedef enum {
PMIC_White_List = 0, //White list
PMIC_Black_List = 1 //Black list
} PMIC_Compliance_mode;
typedef struct {
UINT8 Cond_Choice; // PMIC_Condition_list
UINT8 Cond_Number; // the number
}PMIC_Condition_Item;
typedef struct {
PMIC_Condition_Item PMIC_BoardID;
PMIC_Condition_Item PMIC_FabID;
PMIC_Condition_Item Soc_Stepping;//define PMIC type, 1:Dialog , 2:Rohm
PMIC_Condition_Item PMIC_VendID;
PMIC_Condition_Item PMIC_RevID;
PMIC_Compliance_mode mode; //if 1, blacklist; if 0, white list.
} PMIC_Compliance_Item;
//
// Platform BDS Functions
//
VOID
PlatformBdsGetDriverOption (
IN LIST_ENTRY *BdsDriverLists
);
VOID
PlatformBdsPredictBootOption (
IN LIST_ENTRY *BdsBootOptionList
);
EFI_STATUS
PlatformBdsShowProgress (
EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
CHAR16 *Title,
EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
UINTN Progress,
UINTN PreviousValue
);
VOID
PlatformBdsConnectSequence (
VOID
);
EFI_STATUS
PlatformBdsConnectConsole (
IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
);
EFI_STATUS
PlatformBdsNoConsoleAction (
VOID
);
VOID
PlatformBdsEnterFrontPage (
IN UINT16 TimeoutDefault,
IN BOOLEAN ConnectAllHappened
);
VOID
EFIAPI
PlatformBdsUserIdentify (
OUT EFI_USER_PROFILE_HANDLE *User,
OUT BOOLEAN *DeferredImage
);
VOID
EFIAPI
PlatformBdsConnectAuthDevice (
VOID
);
VOID
PlatformBdsEnterFrontPageWithHotKey (
IN UINT16 TimeoutDefault,
IN BOOLEAN ConnectAllHappened
);
EFI_STATUS
ShowProgress (
IN UINT16 TimeoutDefault
);
EFI_STATUS
InitializeFrontPage (
IN BOOLEAN InitializeHiiData
);
VOID
UpdateFrontPageStrings (
VOID
);
EFI_STATUS
CallFrontPage (
VOID
);
VOID
CallBootManager (
VOID
);
VOID
CallDeviceManager (
VOID
);
VOID
BdsStartBootMaint (
VOID
);
CHAR16 *
GetStringById (
IN EFI_STRING_ID Id
);
EFI_STATUS
WaitForSingleEvent (
IN EFI_EVENT Event,
IN UINT64 Timeout OPTIONAL
);
#define ONE_SECOND 10000000
#define FRONT_PAGE_KEY_CONTINUE 0x1000
#define FRONT_PAGE_KEY_LANGUAGE 0x1234
#define FRONT_PAGE_KEY_BOOT_MANAGER 0x1064
#define FRONT_PAGE_KEY_DEVICE_MANAGER 0x8567
#define FRONT_PAGE_KEY_BOOT_MAINTAIN 0x9876
#define PORT_A_DVO 0 // ; DVO A
#define PORT_B_DVO 1 // ; DVO B
#define PORT_C_DVO 2 // ; DVO C
#define PORT_D_DVO 3 // ; DVO D
#define PORT_LVDS 4 // ; Integrated LVDS port
#define PORT_ANALOG_TV 5 // ; Integrated TV port
#define PORT_CRT 6 // ; integrated Analog port
#define PORT_B_DP 7 // ; DisplayPort B
#define PORT_C_DP 8 // ; DisplayPort C
#define PORT_D_DP 9 // ; DisplayPort D
#define PORT_A_DP 10 // ; DisplayPort A (for eDP on ILK)
#define PORT_B_HDMI 11 // ; HDMI B
#define PORT_C_HDMI 12 // ; HDMI C
#define PORT_D_HDMI 13 // ; HDMI D
#define PORT_B_DVI 14 // ; DVI B
#define PORT_C_DVI 15 // ; DVI C
#define PORT_D_DVI 16 // ; DVI D
#define PORT_MIPI_A 21 // ; MIPI
#define PORT_MIPI_B 22
#define PORT_MIPI_C 23
extern BOOLEAN gConnectAllHappened;
extern UINTN gCallbackKey;
VOID
BdsBootDeviceSelect (
VOID
);
VOID FastBoot(VOID);
extern BOOLEAN mModeInitialized;
//
// Boot video resolution and text mode.
//
extern UINT32 mBootHorizontalResolution ;
extern UINT32 mBootVerticalResolution ;
extern UINT32 mBootTextModeColumn ;
extern UINT32 mBootTextModeRow ;

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#/** @file
# Component name for module PlatformBootManagerLib
#
# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformBdsLib
FILE_GUID = A6BC385D-59E5-4b77-87D7-200ABAA83C15
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x0002000A
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
BdsPlatform.c
BdsPlatform.h
PlatformData.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
ShellPkg/ShellPkg.dec
CryptoPkg/CryptoPkg.dec
SecurityPkg/SecurityPkg.dec
[LibraryClasses]
DxeServicesTableLib
BaseLib
MemoryAllocationLib
UefiBootServicesTableLib
UefiRuntimeServicesTableLib
BaseMemoryLib
DebugLib
PcdLib
GenericBdsLib
DevicePathLib
UefiLib
HobLib
PciLib
PrintLib
BaseCryptLib
# TcgPhysicalPresenceLib
# TrEEPhysicalPresenceLib
FileHandleLib
S3BootScriptLib
SerialPortLib
[Protocols]
gEfiFirmwareVolume2ProtocolGuid
gEfiSimpleNetworkProtocolGuid
gEfiLoadFileProtocolGuid
gEfiPciIoProtocolGuid
gEfiSmmAccess2ProtocolGuid
gEfiDxeSmmReadyToLockProtocolGuid
gEfiUserManagerProtocolGuid
gEfiDeferredImageLoadProtocolGuid
gEfiAcpiS3SaveProtocolGuid
gEfiSpiProtocolGuid ## PROTOCOL CONSUMES
gExitPmAuthProtocolGuid
gEfiTdtOperationProtocolGuid
gEfiGlobalNvsAreaProtocolGuid
gEfiMmioDeviceProtocolGuid
gEfiI2cMasterProtocolGuid
gEfiI2cHostProtocolGuid
[Guids]
gEfiMemoryTypeInformationGuid
gEfiCapsuleVendorGuid
gEfiGlobalVariableGuid
gEfiNormalSetupGuid
gEfiPartTypeSystemPartGuid
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base
gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
gPlatformModuleTokenSpaceGuid.PcdFlashFvShellBase
gPlatformModuleTokenSpaceGuid.PcdFlashFvShellSize
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile
gPlatformModuleTokenSpaceGuid.PcdIFWISigBaseAddress
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow

265
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/** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PlatformData.c
Abstract:
Defined the platform specific device path which will be used by
platform Bbd to perform the platform policy connect.
--*/
#include "BdsPlatform.h"
//
// Predefined platform default time out value
//
UINT16 gPlatformBootTimeOutDefault = 10;
//
// Predefined platform root bridge
//
PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = {
gPciRootBridge,
gEndEntire
};
EFI_DEVICE_PATH_PROTOCOL* gPlatformRootBridges [] = {
(EFI_DEVICE_PATH_PROTOCOL*)&gPlatformRootBridge0,
NULL
};
//
// Platform specific ISA keyboard device path
//
PLATFORM_ISA_KEYBOARD_DEVICE_PATH gIsaKeyboardDevicePath = {
gPciRootBridge,
gPciIsaBridge,
gPnpPs2Keyboard,
gEndEntire
};
//
// Platform specific on chip PCI VGA device path
//
PLATFORM_ONBOARD_VGA_DEVICE_PATH gOnChipPciVgaDevicePath = {
gPciRootBridge,
PCI_DEVICE_PATH_NODE(0, 0x2),
gEndEntire
};
//
// Platform specific plug in PCI VGA device path
//
PLATFORM_OFFBOARD_VGA_DEVICE_PATH gPlugInPciVgaDevicePath = {
gPciRootBridge,
PCI_DEVICE_PATH_NODE(0, 0x1),
PCI_DEVICE_PATH_NODE(0, 0x0),
gEndEntire
};
//
// Platform specific ISA serial device path
//
PLATFORM_ISA_SERIAL_DEVICE_PATH gIsaSerialDevicePath = {
gPciRootBridge,
gPciIsaBridge,
gPnp16550ComPort,
gUart(115200, 8, 1, 1),
gPcAnsiTerminal,
gEndEntire
};
//
// Platform specific Button Array device path
//
HII_VENDOR_DEVICE_PATH gHiiVendorDevicePath0 = {
{
{
HARDWARE_DEVICE_PATH,
HW_VENDOR_DP,
{
(UINT8) (sizeof (VENDOR_DEVICE_PATH)),
(UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)
}
},
//
// {C8752FDE-B5C8-4528-897D-6920FE771E38}
//
{ 0xC8752FDE, 0xB5C8, 0x4528, { 0x89, 0x7D, 0x69, 0x20, 0xFE, 0x77, 0x1E, 0x38 } }
},
{
END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{
(UINT8) (END_DEVICE_PATH_LENGTH),
(UINT8) ((END_DEVICE_PATH_LENGTH) >> 8)
}
}
};
USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {
gUsbKeyboardMouse,
gEndEntire
};
//
// Predefined platform default console device path
//
BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [] = {
{(EFI_DEVICE_PATH_PROTOCOL*)&gIsaSerialDevicePath, CONSOLE_ALL},
{(EFI_DEVICE_PATH_PROTOCOL*)&gHiiVendorDevicePath0, CONSOLE_IN},
{(EFI_DEVICE_PATH_PROTOCOL*)&gIsaKeyboardDevicePath, CONSOLE_IN},
{(EFI_DEVICE_PATH_PROTOCOL*)&gUsbClassKeyboardDevicePath, CONSOLE_IN},
{NULL, 0}
};
//
// All the possible platform PCI VGA device path
//
EFI_DEVICE_PATH_PROTOCOL* gPlatformAllPossiblePciVgaConsole [] = {
(EFI_DEVICE_PATH_PROTOCOL*)&gOnChipPciVgaDevicePath,
(EFI_DEVICE_PATH_PROTOCOL*)&gPlugInPciVgaDevicePath,
NULL
};
//
// Legacy hard disk boot option
//
LEGACY_HD_DEVICE_PATH gLegacyHd = {
{
BBS_DEVICE_PATH,
BBS_BBS_DP,
(UINT8)(sizeof(BBS_BBS_DEVICE_PATH)),
(UINT8)((sizeof(BBS_BBS_DEVICE_PATH)) >> 8),
BBS_TYPE_HARDDRIVE,
0,
0
},
gEndEntire
};
//
// Legacy cdrom boot option
//
LEGACY_HD_DEVICE_PATH gLegacyCdrom = {
{
BBS_DEVICE_PATH,
BBS_BBS_DP,
(UINT8)(sizeof(BBS_BBS_DEVICE_PATH)),
(UINT8)((sizeof(BBS_BBS_DEVICE_PATH)) >> 8),
BBS_TYPE_CDROM,
0,
0
},
gEndEntire
};
//
// Predefined platform specific perdict boot option
//
EFI_DEVICE_PATH_PROTOCOL* gPlatformBootOption [] = {
(EFI_DEVICE_PATH_PROTOCOL*)&gLegacyHd,
(EFI_DEVICE_PATH_PROTOCOL*)&gLegacyCdrom,
NULL
};
//
// Predefined platform specific driver option
//
EFI_DEVICE_PATH_PROTOCOL* gPlatformDriverOption [] = {
NULL
};
//
// Predefined platform connect sequence
//
EFI_DEVICE_PATH_PROTOCOL* gPlatformConnectSequence [] = {
(EFI_DEVICE_PATH_PROTOCOL *)&gPlatformRootBridge0, // Force PCI enumer before Legacy OpROM shadow
NULL
};
//
// Platform specific USB controller device path
//
PLATFORM_USB_DEVICE_PATH gUsbDevicePath0 = {
gPciRootBridge,
PCI_DEVICE_PATH_NODE(0, 0x1D),
gEndEntire
};
PLATFORM_USB_DEVICE_PATH gUsbDevicePath1 = {
gPciRootBridge,
PCI_DEVICE_PATH_NODE(1, 0x1D),
gEndEntire
};
PLATFORM_USB_DEVICE_PATH gUsbDevicePath2 = {
gPciRootBridge,
PCI_DEVICE_PATH_NODE(2, 0x1D),
gEndEntire
};
PLATFORM_USB_DEVICE_PATH gUsbDevicePath3 = {
gPciRootBridge,
PCI_DEVICE_PATH_NODE(3, 0x1D),
gEndEntire
};
//
// Predefined platform device path for user authtication
//
EFI_DEVICE_PATH_PROTOCOL* gUserAuthenticationDevice[] = {
//
// Predefined device path for secure card (USB disk).
//
(EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath0,
(EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath1,
(EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath2,
(EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath3,
NULL
};
//
// Predefined platform console device path
//
BDS_CONSOLE_CONNECT_ENTRY gPlatformSimpleConsole [] = {
{(EFI_DEVICE_PATH_PROTOCOL*)&gOnChipPciVgaDevicePath, CONSOLE_OUT},
{(EFI_DEVICE_PATH_PROTOCOL*)&gIsaSerialDevicePath, CONSOLE_ALL},
{(EFI_DEVICE_PATH_PROTOCOL*)&gHiiVendorDevicePath0, CONSOLE_IN},
{(EFI_DEVICE_PATH_PROTOCOL*)&gUsbClassKeyboardDevicePath, CONSOLE_IN},
{NULL, 0}
};
//
// eMMC device at BDF(0x0, 0x17, 0x0)
//
PLATFORM_PCI_DEVICE_PATH gEmmcBootDevPath0 = {
gPciRootBridge,
PCI_DEVICE_PATH_NODE (0x00, 0x10),
gEndEntire
};

111
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/*++
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
CmosTable.h
Abstract:
--*/
#include <Base.h>
#include <Library/IoLib.h>
#include <Library/PlatformCmosLib.h>
#include "CmosMap.h"
#include <PchAccess.h>
#include "PlatformBaseAddresses.h"
#define DEFAULT_VALUE 0
#define DEFAULT_ATTRIBUTES 0
#define EXCLUDE_FROM_CHECKSUM CMOS_ATTRIBUTE_EXCLUDE_FROM_CHECKSUM
#define CMOS_DEBUG_PRINT_LEVEL_DEFAULT_VALUE 0x46 // EFI_D_WARN|EFI_D_INFO|EFI_D_LOAD
#define CMOS_DEBUG_PRINT_LEVEL_3_DEFAULT_VALUE 0x80 // EFI_D_ERROR
//
// Add the CMOS entry below
//
CMOS_ENTRY mCmosTable[] = {
{ CPU_HT_POLICY, CPU_HT_POLICY_ENABLED, EXCLUDE_FROM_CHECKSUM },
{ TPM_POLICY, TPM_POLICY_ENABLED, DEFAULT_ATTRIBUTES },
{ CMOS_LCDPANELTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_LCDPANELSCALING_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_IGDBOOTTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_BACKLIGHT_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_LFP_PANEL_COLOR_DEPTH_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_EDP_ACTIVE_LFP_CONFIG_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_PRIMARY_DISPLAY_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_IGD_DISPLAY_PIPE_B_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_SDVOPANELTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_PLATFORM_RESET_OS, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_CPU_BSP_SELECT, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_CPU_RATIO_OFFSET, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_ICH_PORT80_OFFSET, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ CMOS_MAXRATIO_CONFIG_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },
{ RTC_ADDRESS_CENTURY, RTC_ADDRESS_CENTURY_DEFAULT, CMOS_ATTRIBUTE_EXCLUDE_FROM_CHECKSUM },
{ CMOS_POST_CODE_BREAK_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },
{ CMOS_POST_CODE_BREAK_1_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },
{ CMOS_POST_CODE_BREAK_2_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },
{ CMOS_POST_CODE_BREAK_3_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },
{ CMOS_DEBUG_PRINT_LEVEL_REG, CMOS_DEBUG_PRINT_LEVEL_DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },
{ CMOS_DEBUG_PRINT_LEVEL_1_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },
{ CMOS_DEBUG_PRINT_LEVEL_2_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },
{ CMOS_DEBUG_PRINT_LEVEL_3_REG, CMOS_DEBUG_PRINT_LEVEL_3_DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },
};
/**
Funtion to return platform CMOS entry.
@param [out] CmosEntry Platform CMOS entry.
@param [out] CmosEntryCount Number of platform CMOS entry.
@return Status.
**/
RETURN_STATUS
EFIAPI
GetPlatformCmosEntry (
OUT CMOS_ENTRY **CmosEntry,
OUT UINTN *CmosEntryCount
)
{
*CmosEntry = mCmosTable;
*CmosEntryCount = sizeof(mCmosTable)/sizeof(mCmosTable[0]);
return RETURN_SUCCESS;
}
/**
Function to check if Battery lost or CMOS cleared.
@reval TRUE Battery is always present.
@reval FALSE CMOS is cleared.
**/
BOOLEAN
EFIAPI
CheckCmosBatteryStatus (
VOID
)
{
//
// Check if the CMOS battery is present

35
Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf Normal file
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#/** @file
#
# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformCmosLib
FILE_GUID = ECA883EF-0CBE-40b6-84BC-FA4A709782F7
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformCmosLib
[Sources]
PlatformCmosLib.c

49
Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c Normal file
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/** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PiPei.h"
#include <Library/HobLib.h>
#include <Library\BaseLib.h>
#include <Library/DebugLib.h>
#include <Guid/MemoryConfigData.h>
#include <PlatformFspLib.h>
EFI_STATUS
PlatformHobCreateFromFsp (
IN CONST EFI_PEI_SERVICES **PeiServices,
VOID *HobList
)
{
VOID *HobData;
VOID *NewHobData;
UINTN DataSize;
//
// Other hob, todo: put this into FspWrapPlatformLib
//
if ((HobList = GetNextGuidHob (&gEfiMemoryConfigDataGuid, HobList)) != NULL) {
HobData = GET_GUID_HOB_DATA (HobList);
DataSize = GET_GUID_HOB_DATA_SIZE(HobList);
DEBUG((EFI_D_ERROR, "gEfiMemoryConfigDataGuid Hob found: 0x%x.\n", DataSize));
NewHobData = BuildGuidHob (&gEfiMemoryConfigDataGuid, DataSize);

54
Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf Normal file
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#
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
# FSP Platform HOB Library
#
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformFspLib
FILE_GUID = 1305A712-33A6-4fa7-BA59-AEAC3362931A
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformFspLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
PlatformFspLib.c
[Packages]
MdePkg/MdePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
IntelFspWrapperPkg/IntelFspWrapperPkg.dec

178
Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.c Normal file
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/** @file
Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
IdeBus.h
Abstract:
System reset Library Services. This library class provides a set of
methods to reset whole system with manipulate ICH.
**/
#include <Base.h>
#include <Library/ResetSystemLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/PciLib.h>
#include "PchRegs.h"
#include "Rsci.h"
#include "Platform.h"
#define RESET_GENERATOR_PORT R_PCH_RST_CNT
VOID
EFIAPI
PlatformResetHook (
UINT8 ResetType
)
{
//
// Platform need to save OS reset request/types for next Android boot
//
IoWrite8 (0x72, CMOS_RESET_TYPE_BY_OS);
IoWrite8 (0x73, ResetType);
}
/**
Calling this function causes a system-wide reset. This sets
all circuitry within the system to its initial state. This type of reset
is asynchronous to system operation and operates without regard to
cycle boundaries.
System reset should not return, if it returns, it means the system does
not support cold reset.
**/
VOID
EFIAPI
ResetCold (
VOID
)
{
PlatformResetHook(COLD_RESET);
IoWrite8 (RESET_GENERATOR_PORT, 0x2);
IoWrite8 (RESET_GENERATOR_PORT, 0x6);
}
/**
Calling this function causes a system-wide initialization. The processors
are set to their initial state, and pending cycles are not corrupted.
System reset should not return, if it returns, it means the system does
not support warm reset.
**/
VOID
EFIAPI
ResetWarm (
VOID
)
{
PlatformResetHook(WARM_RESET);
IoWrite8 (RESET_GENERATOR_PORT, 0x0);
IoWrite8 (RESET_GENERATOR_PORT, 0x4);
}
/**
Calling this function causes the system to enter a power state equivalent
to the ACPI G2/S5 or G3 states.
System shutdown should not return, if it returns, it means the system does
not support shut down reset.
**/
VOID
EFIAPI
ResetShutdown (
VOID
)
{
UINT16 PchPmioBase;
UINT16 Data16;
UINT32 Data32;
PchPmioBase = (UINT16) (PciRead16 (PCI_LIB_ADDRESS(0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ACPI_BASE)) & ~BIT0);
//
// Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5
//
Data16 = 0;
IoWrite16 (
(UINTN)(PchPmioBase + R_PCH_ACPI_GPE0a_EN),
(UINT16)Data16
);
//
// Clear Sleep SMI Status
//
IoWrite16 (PchPmioBase + R_PCH_SMI_STS,
(UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_STS) | B_PCH_SMI_STS_ON_SLP_EN));
//
// Clear Sleep Type Enable
//
IoWrite16 (PchPmioBase + R_PCH_SMI_EN,
(UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_EN) & (~B_PCH_SMI_EN_ON_SLP_EN)));
//
// Clear Power Button Status
//
IoWrite16(PchPmioBase + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);
//
// Secondly, Power Button Status bit must be cleared
//
// Write a "1" to bit[8] of power button status register at
// (ABASE + PM1_STS) to clear this bit
// Clear it through SMI Status register
//
Data16 = B_PCH_SMI_STS_PM1_STS_REG;
IoWrite16 ((UINTN) (PchPmioBase + R_PCH_SMI_STS), Data16);
//
// Finally, transform system into S5 sleep state
//
Data32 = IoRead32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT));
Data32 = (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5);
IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);
Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN;
IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);
return;
}
/**
Calling this function causes the system to enter a power state for capsule
update.
Reset update should not return, if it returns, it means the system does
not support capsule update.
**/

52
Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf Normal file
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#/** @file
# Component description file for Intel Ich7 Reset System Library.
#
# Reset System Library that layers on top of the I/O Library to directly
# access a standard SMBUS host controller.
# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ResetSystemLib
FILE_GUID = D4FF05AA-3C7D-4b8a-A1EE-AA5EFA0B1732
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ResetSystemLib
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x00020000
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF
#
[Sources.common]
ResetSystemLib.c
[Packages]
Vlv2TbltDevicePkg/PlatformPkg.dec

69
Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h Normal file
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/** @file
Header file of Serial port hardware definition.
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as
permitted by such license, no part of this software or
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written
consent of Intel Corporation.
Module Name: PlatformSerialPortLib.h
**/
#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
#define __PLATFORM_SERIAL_PORT_LIB_H_
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/SerialPortLib.h>
//
// UART Register Offsets
//
#define BAUD_LOW_OFFSET 0x00
#define BAUD_HIGH_OFFSET 0x01
#define IER_OFFSET 0x01
#define LCR_SHADOW_OFFSET 0x01
#define FCR_SHADOW_OFFSET 0x02
#define IR_CONTROL_OFFSET 0x02
#define FCR_OFFSET 0x02
#define EIR_OFFSET 0x02
#define BSR_OFFSET 0x03
#define LCR_OFFSET 0x03
#define MCR_OFFSET 0x04
#define LSR_OFFSET 0x05
#define MSR_OFFSET 0x06
//
// UART Register Bit Defines
//
#define LSR_TXRDY 0x20
#define LSR_RXDA 0x01
#define DLAB 0x01
#define UART_DATA 8
#define UART_STOP 1

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/** @file
Serial I/O Port library functions with no library constructor/destructor
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as
permitted by such license, no part of this software or
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written
consent of Intel Corporation.
Module Name: SerialPortLib.c
**/
#include "PlatformSerialPortLib.h"
UINT16 gComBase = 0x3f8;
UINTN gBps = 115200;
UINT8 gData = 8;
UINT8 gStop = 1;
UINT8 gParity = 0;
UINT8 gBreakSet = 0;
/**
Initialize Serial Port
The Baud Rate Divisor registers are programmed and the LCR
is used to configure the communications format. Hard coded
UART config comes from globals in DebugSerialPlatform lib.
@param None
@retval None
**/
RETURN_STATUS
EFIAPI
UARTInitialize (
VOID
)
{
UINTN Divisor;
UINT8 OutputData;
UINT8 Data;
//
// Map 5..8 to 0..3
//
Data = (UINT8) (gData - (UINT8) 5);
//
// Calculate divisor for baud generator
//
Divisor = 115200 / gBps;
//
// Set communications format
//
OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
IoWrite8 (gComBase + LCR_OFFSET, OutputData);
//
// Configure baud rate
//
IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));
IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
//
// Switch back to bank 0
//
OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
IoWrite8 (gComBase + LCR_OFFSET, OutputData);
return RETURN_SUCCESS;
}
/**
Common function to initialize UART Serial device and USB Serial device.
@param None
@retval None
**/
RETURN_STATUS
EFIAPI
SerialPortInitialize (
VOID
)
{
UARTInitialize ();
return RETURN_SUCCESS;
}
/**
Write data to serial device.
If the buffer is NULL, then return 0;
if NumberOfBytes is zero, then return 0.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device.
**/
UINTN
EFIAPI
UARTDbgOut (
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
UINTN Result;
UINT8 Data;
if (NULL == Buffer) {
return 0;
}
Result = NumberOfBytes;
while (NumberOfBytes--) {
//
// Wait for the serial port to be ready.
//
do {
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
} while ((Data & LSR_TXRDY) == 0);
IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++);
}
return Result;
}
/**
Common function to write data to UART Serial device and USB Serial device.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
**/
UINTN
EFIAPI
SerialPortWrite (
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgOut (Buffer, NumberOfBytes);
}
return RETURN_SUCCESS;
}
/**
Read data from serial device and save the datas in buffer.
If the buffer is NULL, then return 0;
if NumberOfBytes is zero, then return 0.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.
@retval !0 Actual number of bytes raed to serial device.
**/
UINTN
EFIAPI
UARTDbgIn (
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
UINTN Result;
UINT8 Data;
if (NULL == Buffer) {
return 0;
}
Result = NumberOfBytes;
while (NumberOfBytes--) {
//
// Wait for the serial port to be ready.
//
do {
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
} while ((Data & LSR_RXDA) == 0);
*Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase));
}
return Result;
}
/**
Common function to Read data from UART serial device, USB serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
**/
UINTN
EFIAPI
SerialPortRead (
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgIn (Buffer, NumberOfBytes);
}
return RETURN_SUCCESS;
}
/**
Polls a serial device to see if there is any data waiting to be read.
Polls aserial device to see if there is any data waiting to be read.
If there is data waiting to be read from the serial device, then TRUE is returned.
If there is no data waiting to be read from the serial device, then FALSE is returned.
@retval TRUE Data is waiting to be read from the serial device.
@retval FALSE There is no data waiting to be read from the serial device.
**/
BOOLEAN
EFIAPI
SerialPortPoll (
VOID
)
{

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#/** @file
#
# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SerialPortLib
FILE_GUID = 15B26F43-A389-4bae-BDE3-4BB0719B7D4F
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = SerialPortLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF
#
[Sources]
SerialPortLib.c
SioInit.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
[LibraryClasses]
BaseLib
PcdLib
IoLib
PciLib
TimerLib

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/** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
SioInit.c
Abstract:
Functions for LpcSio initialization
--*/
#include "PlatformSerialPortLib.h"
#include "SioInit.h"
typedef struct {
UINT8 Register;
UINT8 Value;
} EFI_SIO_TABLE;
EFI_SIO_TABLE mSioTableWpcn381u[] = {
{0x29, 0x0A0},
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{0x21, 0x001}, // Global Device Enable
{0x26, 0x000}
};
EFI_SIO_TABLE mSioTableWdcp376[] = {
{0x29, 0x0A0},
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{0x21, 0x001}, // Global Device Enable
{0x26, 0x000},
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K}, // Select PS2 Keyboard
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x011}, // Set to IRQ1
{0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC Clock Source
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M}, // Select PS2 Mouse
{WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to IRQ12
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE} // Enable it with Activation bit
};
/**
Initialization for SIO.
@param FfsHeader FV this PEIM was loaded from.
@param PeiServices General purpose services available to every PEIM.
None
**/
VOID
InitializeSio (
VOID
)
{
UINT16 Index;
UINT16 IndexPort;
UINT16 DataPort;
//
// Super I/O initialization for Winbond WPCN381U
//
IndexPort = WPCN381U_CONFIG_INDEX;
DataPort = WPCN381U_CONFIG_DATA;
//
// Check for Winbond WPCN381U
//
IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond WPCN381U Device ID register is 0x20
if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U Device ID is 0xF4
//
// Configure WPCN381U SIO
//
for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
}
}
if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376 Device ID is 0xF1
//

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/** @file
Header file of Serial port hardware definition.
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as
permitted by such license, no part of this software or
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written
consent of Intel Corporation.
Module Name: PlatformSerialPortLib.h
**/
#ifndef _SIO_INIT_H_
#define _SIO_INIT_H_
#define WPCN381U_CONFIG_INDEX 0x2E
#define WPCN381U_CONFIG_DATA 0x2F
#define WPCN381U_CONFIG_INDEX1 0x164E
#define WPCN381U_CONFIG_DATA1 0x164F
#define WPCN381U_CHIP_ID 0xF4
#define WDCP376_CHIP_ID 0xF1
//
// SIO Logical Devices Numbers
//
#define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller
#define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller
#define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller
#define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller
#define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller
#define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller
#define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source
#define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO
//
// SIO Registers Layout
//
#define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address
#define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address
#define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address
#define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address
#define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address
#define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address
#define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address
#define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address
#define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address
//
// SIO Activation Values
//
#define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device
#define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device
//
// SIO GPIO
//

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/**@file
Common header file shared by all source files.
This file includes package header files, library classes.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __COMMON_HEADER_H_
#define __COMMON_HEADER_H_
#include <Base.h>

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/** @file
Intel ICH9 SMBUS library implementation built upon I/O library.
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CommonHeader.h"
/**
Gets Io port base address of Smbus Host Controller.
This internal function depends on a feature flag named PcdIchSmbusFixedIoPortBaseAddress
to retrieve Smbus Io port base. If that feature flag is true, it will get Smbus Io port base
address from a preset Pcd entry named PcdIchSmbusIoPortBaseAddress; otherwise, it will always
read Pci configuration space to get that value in each Smbus bus transaction.
@return The Io port base address of Smbus host controller.
**/
UINTN
InternalGetSmbusIoPortBaseAddress (
VOID
)
{
UINTN IoPortBaseAddress;
IoPortBaseAddress = (UINTN) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_BASE)) & B_PCH_SMBUS_BASE_BAR;
//
// Make sure that the IO port base address has been properly set.
//
ASSERT (IoPortBaseAddress != 0);
return IoPortBaseAddress;
}
/**
Acquires the ownership of SMBUS.
This internal function reads the host state register.
If the SMBUS is not available, RETURN_TIMEOUT is returned;
Otherwise, it performs some basic initializations and returns
RETURN_SUCCESS.
@param IoPortBaseAddress The Io port base address of Smbus Host controller.
@retval RETURN_SUCCESS The SMBUS command was executed successfully.
@retval RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
**/
RETURN_STATUS
InternalSmBusAcquire (
UINTN IoPortBaseAddress
)
{
UINT8 HostStatus;
HostStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS);
if ((HostStatus & B_PCH_SMBUS_IUS) != 0) {
return RETURN_TIMEOUT;
} else if ((HostStatus & B_PCH_SMBUS_HBSY) != 0) {
//
// Clear host status register and exit.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
return RETURN_TIMEOUT;
}
//
// Clear out any odd status information (Will Not Clear In Use).
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, HostStatus);
return RETURN_SUCCESS;
}
/**
Starts the SMBUS transaction and waits until the end.
This internal function start the SMBUS transaction and waits until the transaction
of SMBUS is over by polling the INTR bit of Host status register.
If the SMBUS is not available, RETURN_TIMEOUT is returned;
Otherwise, it performs some basic initializations and returns
RETURN_SUCCESS.
@param IoPortBaseAddress The Io port base address of Smbus Host controller.
@param HostControl The Host control command to start SMBUS transaction.
@retval RETURN_SUCCESS The SMBUS command was executed successfully.
@retval RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
@retval RETURN_DEVICE_ERROR The request was not completed because a failure reflected
in the Host Status Register bit. Device errors are
a result of a transaction collision, illegal command field,
unclaimed cycle (host initiated), or bus errors (collisions).
**/
RETURN_STATUS
InternalSmBusStart (
IN UINTN IoPortBaseAddress,
IN UINT8 HostControl
)
{
UINT8 HostStatus;
UINT8 AuxiliaryStatus;
//
// Set Host Control Register (Initiate Operation, Interrupt disabled).
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCTL, (UINT8)(HostControl + B_PCH_SMBUS_START));
do {
//
// Poll INTR bit of Host Status Register.
//
HostStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS);
} while ((HostStatus & (B_PCH_SMBUS_INTR | B_PCH_SMBUS_ERRORS | B_PCH_SMBUS_BYTE_DONE_STS)) == 0);
if ((HostStatus & B_PCH_SMBUS_ERRORS) == 0) {
return RETURN_SUCCESS;
}
//
// Clear error bits of Host Status Register.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_ERRORS);
//
// Read Auxiliary Status Register to judge CRC error.
//
AuxiliaryStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS);
if ((AuxiliaryStatus & B_PCH_SMBUS_CRCE) != 0) {
return RETURN_CRC_ERROR;
}
return RETURN_DEVICE_ERROR;
}
/**
Executes an SMBUS quick, byte or word command.
This internal function executes an SMBUS quick, byte or word commond.
If Status is not NULL, then the status of the executed command is returned in Status.
@param HostControl The value of Host Control Register to set.
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Value The byte/word write to the SMBUS.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The byte/word read from the SMBUS.
**/
UINT16
InternalSmBusNonBlock (
IN UINT8 HostControl,
IN UINTN SmBusAddress,
IN UINT16 Value,
OUT RETURN_STATUS *Status
)
{
RETURN_STATUS ReturnStatus;
UINTN IoPortBaseAddress;
UINT8 AuxiliaryControl;
IoPortBaseAddress = InternalGetSmbusIoPortBaseAddress ();
//
// Try to acquire the ownership of ICH SMBUS.
//
ReturnStatus = InternalSmBusAcquire (IoPortBaseAddress);
if (RETURN_ERROR (ReturnStatus)) {
goto Done;
}
//
// Set the appropriate Host Control Register and auxiliary Control Register.
//
AuxiliaryControl = 0;
if (SMBUS_LIB_PEC (SmBusAddress)) {
AuxiliaryControl |= B_PCH_SMBUS_AAC;
HostControl |= B_PCH_SMBUS_PEC_EN;
}
//
// Set Host Command Register.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));
//
// Write value to Host Data 0 and Host Data 1 Registers.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD0, (UINT8) Value);
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD1, (UINT8) (Value >> 8));
//
// Set Auxiliary Control Register.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXC, AuxiliaryControl);
//
// Set SMBUS slave address for the device to send/receive from.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_TSA, (UINT8) SmBusAddress);
//
// Start the SMBUS transaction and wait for the end.
//
ReturnStatus = InternalSmBusStart (IoPortBaseAddress, HostControl);
//
// Read value from Host Data 0 and Host Data 1 Registers.
//
Value = (UINT16)(IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HD1) << 8);
Value = (UINT16)(Value | IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HD0));
//
// Clear Host Status Register and Auxiliary Status Register.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);
Done:
if (Status != NULL) {
*Status = ReturnStatus;
}
return Value;
}
/**
Executes an SMBUS quick read command.
Executes an SMBUS quick read command on the SMBUS device specified by SmBusAddress.
Only the SMBUS slave address field of SmBusAddress is required.
If Status is not NULL, then the status of the executed command is returned in Status.
If PEC is set in SmBusAddress, then ASSERT().
If Command in SmBusAddress is not zero, then ASSERT().
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
**/
VOID
EFIAPI
SmBusQuickRead (
IN UINTN SmBusAddress,
OUT RETURN_STATUS *Status OPTIONAL
)
{
ASSERT (!SMBUS_LIB_PEC (SmBusAddress));
ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_QUICK,
SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
0,
Status
);
}
/**
Executes an SMBUS quick write command.
Executes an SMBUS quick write command on the SMBUS device specified by SmBusAddress.
Only the SMBUS slave address field of SmBusAddress is required.
If Status is not NULL, then the status of the executed command is returned in Status.
If PEC is set in SmBusAddress, then ASSERT().
If Command in SmBusAddress is not zero, then ASSERT().
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
**/
VOID
EFIAPI
SmBusQuickWrite (
IN UINTN SmBusAddress,
OUT RETURN_STATUS *Status OPTIONAL
)
{
ASSERT (!SMBUS_LIB_PEC (SmBusAddress));
ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_QUICK,
SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
0,
Status
);
}
/**
Executes an SMBUS receive byte command.
Executes an SMBUS receive byte command on the SMBUS device specified by SmBusAddress.
Only the SMBUS slave address field of SmBusAddress is required.
The byte received from the SMBUS is returned.
If Status is not NULL, then the status of the executed command is returned in Status.
If Command in SmBusAddress is not zero, then ASSERT().
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The byte received from the SMBUS.
**/
UINT8
EFIAPI
SmBusReceiveByte (
IN UINTN SmBusAddress,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINT8 ValueReturn = 0;
ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
ValueReturn = (UINT8) InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_BYTE,
SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
0,
Status
);
return ValueReturn;
}
/**
Executes an SMBUS send byte command.
Executes an SMBUS send byte command on the SMBUS device specified by SmBusAddress.
The byte specified by Value is sent.
Only the SMBUS slave address field of SmBusAddress is required. Value is returned.
If Status is not NULL, then the status of the executed command is returned in Status.
If Command in SmBusAddress is not zero, then ASSERT().
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Value The 8-bit value to send.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The parameter of Value.
**/
UINT8
EFIAPI
SmBusSendByte (
IN UINTN SmBusAddress,
IN UINT8 Value,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINT8 ValueReturn = 0;
ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
ValueReturn = (UINT8) InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_BYTE,
SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
Value,
Status
);
return ValueReturn;
}
/**
Executes an SMBUS read data byte command.
Executes an SMBUS read data byte command on the SMBUS device specified by SmBusAddress.
Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
The 8-bit value read from the SMBUS is returned.
If Status is not NULL, then the status of the executed command is returned in Status.
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The byte read from the SMBUS.
**/
UINT8
EFIAPI
SmBusReadDataByte (
IN UINTN SmBusAddress,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINT8 ValueReturn = 0;
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
ValueReturn = (UINT8) InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_BYTE_DATA,
SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
0,
Status
);
return ValueReturn;
}
/**
Executes an SMBUS write data byte command.
Executes an SMBUS write data byte command on the SMBUS device specified by SmBusAddress.
The 8-bit value specified by Value is written.
Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
Value is returned.
If Status is not NULL, then the status of the executed command is returned in Status.
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Value The 8-bit value to write.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The parameter of Value.
**/
UINT8
EFIAPI
SmBusWriteDataByte (
IN UINTN SmBusAddress,
IN UINT8 Value,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINT8 ValueReturn = 0;
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
ValueReturn = (UINT8) InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_BYTE_DATA,
SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
Value,
Status
);
return ValueReturn;
}
/**
Executes an SMBUS read data word command.
Executes an SMBUS read data word command on the SMBUS device specified by SmBusAddress.
Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
The 16-bit value read from the SMBUS is returned.
If Status is not NULL, then the status of the executed command is returned in Status.
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The byte read from the SMBUS.
**/
UINT16
EFIAPI
SmBusReadDataWord (
IN UINTN SmBusAddress,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINT16 ValueReturn = 0;
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
ValueReturn = InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_WORD_DATA,
SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
0,
Status
);
return ValueReturn;
}
/**
Executes an SMBUS write data word command.
Executes an SMBUS write data word command on the SMBUS device specified by SmBusAddress.
The 16-bit value specified by Value is written.
Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
Value is returned.
If Status is not NULL, then the status of the executed command is returned in Status.
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Value The 16-bit value to write.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The parameter of Value.
**/
UINT16
EFIAPI
SmBusWriteDataWord (
IN UINTN SmBusAddress,
IN UINT16 Value,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINT16 ValueReturn = 0;
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
ValueReturn = InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_WORD_DATA,
SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
Value,
Status
);
return ValueReturn;
}
/**
Executes an SMBUS process call command.
Executes an SMBUS process call command on the SMBUS device specified by SmBusAddress.
The 16-bit value specified by Value is written.
Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
The 16-bit value returned by the process call command is returned.
If Status is not NULL, then the status of the executed command is returned in Status.
If Length in SmBusAddress is not zero, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Value The 16-bit value to write.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The 16-bit value returned by the process call command.
**/
UINT16
EFIAPI
SmBusProcessCall (
IN UINTN SmBusAddress,
IN UINT16 Value,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINT16 ValueReturn = 0;
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
ValueReturn = InternalSmBusNonBlock (
V_PCH_SMBUS_SMB_CMD_PROCESS_CALL,
SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
Value,
Status
);
return ValueReturn;
}
/**
Executes an SMBUS block command.
Executes an SMBUS block read, block write and block write-block read command
on the SMBUS device specified by SmBusAddress.
Bytes are read from the SMBUS and stored in Buffer.
The number of bytes read is returned, and will never return a value larger than 32-bytes.
If Status is not NULL, then the status of the executed command is returned in Status.
It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.
@param HostControl The value of Host Control Register to set.
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param WriteBuffer Pointer to the buffer of bytes to write to the SMBUS.
@param ReadBuffer Pointer to the buffer of bytes to read from the SMBUS.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The number of bytes read from the SMBUS.
**/
UINTN
InternalSmBusBlock (
IN UINT8 HostControl,
IN UINTN SmBusAddress,
IN UINT8 *WriteBuffer,
OUT UINT8 *ReadBuffer,
OUT RETURN_STATUS *Status
)
{
RETURN_STATUS ReturnStatus;
UINTN Index;
UINTN BytesCount;
UINTN IoPortBaseAddress;
UINT8 AuxiliaryControl;
IoPortBaseAddress = InternalGetSmbusIoPortBaseAddress ();
BytesCount = SMBUS_LIB_LENGTH (SmBusAddress);
//
// Try to acquire the ownership of ICH SMBUS.
//
ReturnStatus = InternalSmBusAcquire (IoPortBaseAddress);
if (RETURN_ERROR (ReturnStatus)) {
goto Done;
}
//
// Set the appropriate Host Control Register and auxiliary Control Register.
//
AuxiliaryControl = B_PCH_SMBUS_E32B;
if (SMBUS_LIB_PEC (SmBusAddress)) {
AuxiliaryControl |= B_PCH_SMBUS_AAC;
HostControl |= B_PCH_SMBUS_PEC_EN;
}
//
// Set Host Command Register.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));
//
// Set Auxiliary Control Regiester.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXC, AuxiliaryControl);
//
// Clear byte pointer of 32-byte buffer.
//
IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HCTL);
if (WriteBuffer != NULL) {
//
// Write the number of block to Host Block Data Byte Register.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD0, (UINT8) BytesCount);
//
// Write data block to Host Block Data Register.
//
for (Index = 0; Index < BytesCount; Index++) {
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HBD, WriteBuffer[Index]);
}
}
//
// Set SMBUS slave address for the device to send/receive from.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_TSA, (UINT8) SmBusAddress);
//
// Start the SMBUS transaction and wait for the end.
//
ReturnStatus = InternalSmBusStart (IoPortBaseAddress, HostControl);
if (RETURN_ERROR (ReturnStatus)) {
goto Done;
}
if (ReadBuffer != NULL) {
//
// Read the number of block from host block data byte register.
//
BytesCount = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HD0);
//
// Write data block from Host Block Data Register.
//
for (Index = 0; Index < BytesCount; Index++) {
ReadBuffer[Index] = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HBD);
}
}
Done:
//
// Clear Host Status Register and Auxiliary Status Register.
//
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);
if (Status != NULL) {
*Status = ReturnStatus;
}
return BytesCount;
}
/**
Executes an SMBUS read block command.
Executes an SMBUS read block command on the SMBUS device specified by SmBusAddress.
Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
Bytes are read from the SMBUS and stored in Buffer.
The number of bytes read is returned, and will never return a value larger than 32-bytes.
If Status is not NULL, then the status of the executed command is returned in Status.
It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.
If Length in SmBusAddress is not zero, then ASSERT().
If Buffer is NULL, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Buffer Pointer to the buffer to store the bytes read from the SMBUS.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The number of bytes read.
**/
UINTN
EFIAPI
SmBusReadBlock (
IN UINTN SmBusAddress,
OUT VOID *Buffer,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINTN BytesCount = 0;
ASSERT (Buffer != NULL);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
BytesCount = InternalSmBusBlock (
V_PCH_SMBUS_SMB_CMD_BLOCK,
SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,
NULL,
Buffer,
Status
);
return BytesCount;
}
/**
Executes an SMBUS write block command.
Executes an SMBUS write block command on the SMBUS device specified by SmBusAddress.
The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.
Bytes are written to the SMBUS from Buffer.
The number of bytes written is returned, and will never return a value larger than 32-bytes.
If Status is not NULL, then the status of the executed command is returned in Status.
If Length in SmBusAddress is zero or greater than 32, then ASSERT().
If Buffer is NULL, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param Buffer Pointer to the buffer to store the bytes read from the SMBUS.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The number of bytes written.
**/
UINTN
EFIAPI
SmBusWriteBlock (
IN UINTN SmBusAddress,
OUT VOID *Buffer,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINTN BytesCount = 0;
ASSERT (Buffer != NULL);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >= 1);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <= 32);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
BytesCount = InternalSmBusBlock (
V_PCH_SMBUS_SMB_CMD_BLOCK,
SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,
Buffer,
NULL,
Status
);
return BytesCount;
}
/**
Executes an SMBUS block process call command.
Executes an SMBUS block process call command on the SMBUS device specified by SmBusAddress.
The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.
Bytes are written to the SMBUS from WriteBuffer. Bytes are then read from the SMBUS into ReadBuffer.
If Status is not NULL, then the status of the executed command is returned in Status.
It is the caller's responsibility to make sure ReadBuffer is large enough for the total number of bytes read.
SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.
If Length in SmBusAddress is zero or greater than 32, then ASSERT().
If WriteBuffer is NULL, then ASSERT().
If ReadBuffer is NULL, then ASSERT().
If any reserved bits of SmBusAddress are set, then ASSERT().
@param SmBusAddress Address that encodes the SMBUS Slave Address,
SMBUS Command, SMBUS Data Length, and PEC.
@param WriteBuffer Pointer to the buffer of bytes to write to the SMBUS.
@param ReadBuffer Pointer to the buffer of bytes to read from the SMBUS.
@param Status Return status for the executed command.
This is an optional parameter and may be NULL.
@return The number of bytes written.
**/
UINTN
EFIAPI
SmBusBlockProcessCall (
IN UINTN SmBusAddress,
IN VOID *WriteBuffer,
OUT VOID *ReadBuffer,
OUT RETURN_STATUS *Status OPTIONAL
)
{
UINTN BytesCount = 0;
ASSERT (WriteBuffer != NULL);
ASSERT (ReadBuffer != NULL);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >= 1);
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <= 32);
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);
BytesCount = InternalSmBusBlock (

51
Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf Normal file
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@@ -0,0 +1,51 @@
## @file
# Component description file for Intel Ich9 Smbus Library.
#
# SMBUS Library that layers on top of the I/O Library to directly
# access a standard SMBUS host controller.
# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SmbusLib
FILE_GUID = 0558CAEA-FEF3-4b6d-915E-8742EFE6DEE1
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = SmbusLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
SmbusLib.c
[Packages]
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
MdePkg/MdePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec

94
Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c Normal file
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@@ -0,0 +1,94 @@
/*++
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
SmmIo.c
Abstract:
SMM I/O access utility implementation file, for Ia32
--*/
//
// Include files
//
#include "Library/StallSmmLib.h"
#include "Pi/PiSmmCis.h"
#include "PiDxe.h"
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include "PchAccess.h"
/**
Delay for at least the request number of microseconds.
Timer used is ACPI time counter, which has 1us granularity.
@param Microseconds Number of microseconds to delay.
@retval None
**/
VOID
SmmStall (
IN UINTN Microseconds
)
{
UINTN Ticks;
UINTN Counts;
UINTN CurrentTick;
UINTN OriginalTick;
UINTN RemainingTick;
UINT16 AcpiBaseAddr;
if (Microseconds == 0) {
return;
}
AcpiBaseAddr = PchLpcPciCfg16 (R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;
OriginalTick = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_TMR);
CurrentTick = OriginalTick;
//
// The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks
//
Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
//
// The loops needed by timer overflow
//
Counts = Ticks / V_PCH_ACPI_PM1_TMR_MAX_VAL;
//
// Remaining clocks within one loop
//
RemainingTick = Ticks % V_PCH_ACPI_PM1_TMR_MAX_VAL;
//
// not intend to use TMROF_STS bit of register PM1_STS, because this adds extra
// one I/O operation, and maybe generate SMI
//
while ((Counts != 0) || (RemainingTick > CurrentTick)) {
CurrentTick = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_TMR);

56
Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf Normal file
View File

@@ -0,0 +1,56 @@
#/*++
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
# Module Name:
#
# SmmStallLib.inf
#
# Abstract:
#
# Component description file for SmmStall library
#
#--*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = StallSmmLib
FILE_GUID = A6A16CCB-91B0-42f4-B4F3-D16D7A8662E6
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = StallSmmLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
StallSmm.c
[Packages]
MdePkg/MdePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec