Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
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287
Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
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287
Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
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/*++
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Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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EfiRegTableLib.c
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Abstract:
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Lib function for table driven register initialization.
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Revision History
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--*/
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#include <Library/EfiRegTableLib.h>
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#include <Library/S3BootScriptLib.h>
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//
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// Local Functions
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//
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/**
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Local worker function to process PCI_WRITE table entries. Performs write and
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may also call BootScriptSave protocol if indicated in the Entry flags
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@param Entry A pointer to the PCI_WRITE entry to process
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@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
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when processing the entry.
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@retval Nothing.
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**/
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STATIC
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VOID
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PciWrite (
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EFI_REG_TABLE_PCI_WRITE *Entry,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
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)
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{
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EFI_STATUS Status;
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Status = PciRootBridgeIo->Pci.Write (
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PciRootBridgeIo,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
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(UINT64) Entry->PciAddress,
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1,
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&Entry->Data
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);
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ASSERT_EFI_ERROR (Status);
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if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
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Status = S3BootScriptSavePciCfgWrite (
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(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
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(UINT64) Entry->PciAddress,
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1,
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&Entry->Data
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);
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ASSERT_EFI_ERROR (Status);
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}
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}
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/**
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Local worker function to process PCI_READ_MODIFY_WRITE table entries.
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Performs RMW write and may also call BootScriptSave protocol if indicated in
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the Entry flags.
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@param Entry A pointer to the PCI_READ_MODIFY_WRITE entry to process.
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@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
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when processing the entry.
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@retval Nothing.
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**/
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STATIC
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VOID
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PciReadModifyWrite (
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EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
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)
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{
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EFI_STATUS Status;
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UINT32 TempData;
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Status = PciRootBridgeIo->Pci.Read (
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PciRootBridgeIo,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
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(UINT64) Entry->PciAddress,
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1,
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&TempData
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);
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ASSERT_EFI_ERROR (Status);
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Entry->OrMask &= Entry->AndMask;
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TempData &= ~Entry->AndMask;
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TempData |= Entry->OrMask;
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Status = PciRootBridgeIo->Pci.Write (
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PciRootBridgeIo,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
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(UINT64) Entry->PciAddress,
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1,
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&TempData
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);
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ASSERT_EFI_ERROR (Status);
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if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
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Status = S3BootScriptSavePciCfgReadWrite (
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(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
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(UINT64) Entry->PciAddress,
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&Entry->OrMask,
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&Entry->AndMask
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);
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ASSERT_EFI_ERROR (Status);
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}
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}
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/**
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Local worker function to process MEM_READ_MODIFY_WRITE table entries.
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Performs RMW write and may also call BootScriptSave protocol if indicated in
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the Entry flags.
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@param Entry A pointer to the MEM_READ_MODIFY_WRITE entry to process.
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@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
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when processing the entry.
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@retval Nothing.
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**/
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STATIC
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VOID
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MemReadModifyWrite (
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EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
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)
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{
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EFI_STATUS Status;
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UINT32 TempData;
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Status = PciRootBridgeIo->Mem.Read (
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PciRootBridgeIo,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
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(UINT64) Entry->MemAddress,
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1,
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&TempData
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);
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ASSERT_EFI_ERROR (Status);
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Entry->OrMask &= Entry->AndMask;
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TempData &= ~Entry->AndMask;
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TempData |= Entry->OrMask;
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Status = PciRootBridgeIo->Mem.Write (
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PciRootBridgeIo,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
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(UINT64) Entry->MemAddress,
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1,
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&TempData
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);
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ASSERT_EFI_ERROR (Status);
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if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
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Status = S3BootScriptSaveMemReadWrite (
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(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
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Entry->MemAddress,
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&Entry->OrMask,
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&Entry->AndMask
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);
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ASSERT_EFI_ERROR (Status);
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}
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}
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//
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// Exported functions
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//
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/**
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Processes register table assuming which may contain PCI, IO, MEM, and STALL
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entries.
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No parameter checking is done so the caller must be careful about omitting
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values for PciRootBridgeIo or CpuIo parameters. If the regtable does
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not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
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NULL). If the regtable does not contain any IO or Mem entries, it is safe to
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omit the CpuIo (supply NULL).
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The RegTableEntry parameter is not checked, but is required.
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gBS is assumed to have been defined and is used when processing stalls.
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The function processes each entry sequentially until an OP_TERMINATE_TABLE
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entry is encountered.
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@param RegTableEntry A pointer to the register table to process
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@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
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when processing PCI table entries
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@param CpuIo A pointer to the instance of CpuIo that is used when processing IO and
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MEM table entries
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@retval Nothing.
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**/
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VOID
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ProcessRegTablePci (
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EFI_REG_TABLE *RegTableEntry,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
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EFI_CPU_IO_PROTOCOL *CpuIo
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)
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{
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while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {
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switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
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case OP_PCI_WRITE:
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PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);
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break;
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case OP_PCI_READ_MODIFY_WRITE:
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PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);
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break;
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case OP_MEM_READ_MODIFY_WRITE:
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MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);
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break;
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default:
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DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));
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ASSERT (0);
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break;
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}
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RegTableEntry++;
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}
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}
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/**
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Processes register table assuming which may contain IO, MEM, and STALL
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entries, but must NOT contain any PCI entries. Any PCI entries cause an
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ASSERT in a DEBUG build and are skipped in a free build.
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No parameter checking is done. Both RegTableEntry and CpuIo parameters are
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required.
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gBS is assumed to have been defined and is used when processing stalls.
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The function processes each entry sequentially until an OP_TERMINATE_TABLE
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entry is encountered.
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@param RegTableEntry A pointer to the register table to process
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@param CpuIo A pointer to the instance of CpuIo that is used when processing IO and
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MEM table entries
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@retval Nothing.
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**/
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VOID
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ProcessRegTableCpu (
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EFI_REG_TABLE *RegTableEntry,
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EFI_CPU_IO_PROTOCOL *CpuIo
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)
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{
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while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {
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switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
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