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Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

Browse Source 
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, 

which are for MinnowBoard MAX open source project.


Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
2015-01-12 09:37:20 +00:00
committed by zwei4
parent 6f785cfcc3
commit 3cbfba02fe
518 changed files with 118538 additions and 0 deletions
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467
Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c Normal file
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/** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/FlashDeviceLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiRuntimeLib.h>
#include <Protocol/SmmBase2.h>
#include <Guid/EventGroup.h>
#include "SpiChipDefinitions.h"
UINTN FlashDeviceBase = FLASH_DEVICE_BASE_ADDRESS;
EFI_SPI_PROTOCOL *mSpiProtocol = NULL;
EFI_STATUS
SpiFlashErase (
UINT8 *BaseAddress,
UINTN NumBytes
)
{
EFI_STATUS Status = EFI_SUCCESS;
UINT32 SectorSize;
UINT32 SpiAddress;
SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;
SectorSize = SECTOR_SIZE_4KB;
while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_SERASE,
SPI_WREN,
FALSE,
TRUE,
FALSE,
(UINT32) SpiAddress,
0,
NULL,
EnumSpiRegionBios
);
if (EFI_ERROR (Status)) {
break;
}
SpiAddress += SectorSize;
NumBytes -= SectorSize;
}
return Status;
}
EFI_STATUS
SpiFlashBlockErase (
UINT8 *BaseAddress,
UINTN NumBytes
)
{
EFI_STATUS Status = EFI_SUCCESS;
UINT32 SectorSize;
UINT32 SpiAddress;
SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;
SectorSize = SECTOR_SIZE_64KB;
while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_BERASE,
SPI_WREN,
FALSE,
TRUE,
FALSE,
(UINT32) SpiAddress,
0,
NULL,
EnumSpiRegionBios
);
if (EFI_ERROR (Status)) {
break;
}
SpiAddress += SectorSize;
NumBytes -= SectorSize;
}
return Status;
}
static
EFI_STATUS
SpiFlashWrite (
UINT8 *DstBufferPtr,
UINT8 *Byte,
IN UINTN Length
)
{
EFI_STATUS Status;
UINT32 NumBytes = (UINT32)Length;
UINT8* pBuf8 = Byte;
UINT32 SpiAddress;
SpiAddress = (UINT32)(UINTN)(DstBufferPtr) - (UINT32)FlashDeviceBase;
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_PROG,
SPI_WREN,
TRUE,
TRUE,
TRUE,
(UINT32)SpiAddress,
NumBytes,
pBuf8,
EnumSpiRegionBios
);
return Status;
}
/**
Read the Serial Flash Status Registers.
@param SpiStatus Pointer to a caller-allocated UINT8. On successful return, it contains the
status data read from the Serial Flash Status Register.
@retval EFI_SUCCESS Operation success, status is returned in SpiStatus.
@retval EFI_DEVICE_ERROR The block device is not functioning correctly and the operation failed.
**/
EFI_STATUS
ReadStatusRegister (
UINT8 *SpiStatus
)
{
EFI_STATUS Status;
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_RDSR,
SPI_WREN,
TRUE,
FALSE,
FALSE,
0,
1,
SpiStatus,
EnumSpiRegionBios
);
return Status;
}
EFI_STATUS
SpiFlashLock (
IN UINT8 *BaseAddress,
IN UINTN NumBytes,
IN BOOLEAN Lock
)
{
EFI_STATUS Status;
UINT8 SpiData;
UINT8 SpiStatus;
if (Lock) {
SpiData = SF_SR_WPE;
} else {
SpiData = 0;
}
//
// Always disable block protection to workaround tool issue.
// Feature may be re-enabled in a future bios.
//
SpiData = 0;
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_WRSR,
SPI_EWSR,
TRUE,
TRUE,
TRUE,
0,
1,
&SpiData,
EnumSpiRegionBios
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = ReadStatusRegister (&SpiStatus);
if (EFI_ERROR (Status)) {
return Status;
}
if ((SpiStatus & SpiData) != SpiData) {
Status = EFI_DEVICE_ERROR;
}
return Status;
}
/**
Read NumBytes bytes of data from the address specified by
PAddress into Buffer.
@param[in] PAddress The starting physical address of the read.
@param[in,out] NumBytes On input, the number of bytes to read. On output, the number
of bytes actually read.
@param[out] Buffer The destination data buffer for the read.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceRead (
IN UINTN PAddress,
IN OUT UINTN *NumBytes,
OUT UINT8 *Buffer
)
{
CopyMem(Buffer, (VOID*)PAddress, *NumBytes);
return EFI_SUCCESS;
}
/**
Write NumBytes bytes of data from Buffer to the address specified by
PAddresss.
@param[in] PAddress The starting physical address of the write.
@param[in,out] NumBytes On input, the number of bytes to write. On output,
the actual number of bytes written.
@param[in] Buffer The source data buffer for the write.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceWrite (
IN UINTN PAddress,
IN OUT UINTN *NumBytes,
IN UINT8 *Buffer
)
{
EFI_STATUS Status;
Status = SpiFlashWrite((UINT8 *)PAddress, Buffer, *NumBytes);
return Status;
}
/**
Erase the block staring at PAddress.
@param[in] PAddress The starting physical address of the block to be erased.
This library assume that caller garantee that the PAddress
is at the starting address of this block.
@param[in] LbaLength The length of the logical block to be erased.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceBlockErase (
IN UINTN PAddress,
IN UINTN LbaLength
)
{
EFI_STATUS Status;
Status = SpiFlashBlockErase((UINT8 *)PAddress, LbaLength);
return Status;
}
/**
Lock or unlock the block staring at PAddress.
@param[in] PAddress The starting physical address of region to be (un)locked.
@param[in] LbaLength The length of the logical block to be erased.
@param[in] Lock TRUE to lock. FALSE to unlock.
@retval EFI_SUCCESS. Opertion is successful.
@retval EFI_DEVICE_ERROR If there is any device errors.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceBlockLock (
IN UINTN PAddress,
IN UINTN LbaLength,
IN BOOLEAN Lock
)
{
EFI_STATUS Status;
Status = SpiFlashLock((UINT8*)PAddress, LbaLength, Lock);
return Status;
}
VOID
EFIAPI
LibFvbFlashDeviceVirtualAddressChangeNotifyEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
gRT->ConvertPointer (0, (VOID **) &mSpiProtocol);
gRT->ConvertPointer (0, (VOID **) &FlashDeviceBase);
}
/**
The library constructuor.
The function does the necessary initialization work for this library
instance. Please put all initialization works in it.
@param[in] ImageHandle The firmware allocated handle for the UEFI image.
@param[in] SystemTable A pointer to the EFI system table.
@retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
It will ASSERT on error for debug version.
@retval EFI_ERROR Please reference LocateProtocol for error code details.
**/
EFI_STATUS
EFIAPI
LibFvbFlashDeviceSupportInit (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_EVENT Event;
UINT8 SfId[3];
UINT8 FlashIndex;
UINT8 SpiReadError;
UINT8 SpiNotMatchError;
EFI_SMM_BASE2_PROTOCOL *SmmBase;
BOOLEAN InSmm;
SpiReadError = 0x00;
SpiNotMatchError = 0x00;
InSmm = FALSE;
Status = gBS->LocateProtocol (
&gEfiSmmBase2ProtocolGuid,
NULL,
(void **)&SmmBase
);
if (!EFI_ERROR(Status)) {
Status = SmmBase->InSmm(SmmBase, &InSmm);
if (EFI_ERROR(Status)) {
InSmm = FALSE;
}
}
if (!InSmm) {
Status = gBS->LocateProtocol (
&gEfiSpiProtocolGuid,
NULL,
(VOID **)&mSpiProtocol
);
ASSERT_EFI_ERROR (Status);
Status = gBS->CreateEventEx (
EVT_NOTIFY_SIGNAL,
TPL_NOTIFY,
LibFvbFlashDeviceVirtualAddressChangeNotifyEvent,
NULL,
&gEfiEventVirtualAddressChangeGuid,
&Event
);
ASSERT_EFI_ERROR (Status);
} else {
Status = gBS->LocateProtocol (
&gEfiSmmSpiProtocolGuid,
NULL,
(VOID **)&mSpiProtocol
);
ASSERT_EFI_ERROR (Status);
}
for (FlashIndex = EnumSpiFlashW25Q64; FlashIndex < EnumSpiFlashMax; FlashIndex++) {
Status = mSpiProtocol->Init (mSpiProtocol, &(mInitTable[FlashIndex]));
if (!EFI_ERROR (Status)) {
//
// Read Vendor/Device IDs to check if the driver supports the Serial Flash device.
//
Status = mSpiProtocol->Execute (
mSpiProtocol,
SPI_READ_ID,
SPI_WREN,
TRUE,
FALSE,
FALSE,
0,
3,
SfId,
EnumSpiRegionAll
);
if (!EFI_ERROR (Status)) {
if ((SfId[0] == mInitTable[FlashIndex].VendorId) &&
(SfId[1] == mInitTable[FlashIndex].DeviceId0) &&
(SfId[2] == mInitTable[FlashIndex].DeviceId1)) {
//
// Found a matching SPI device, FlashIndex now contains flash device.
//
DEBUG ((EFI_D_ERROR, "OK - Found SPI Flash Type in SPI Flash Driver, Device Type ID 0 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId0));
DEBUG ((EFI_D_ERROR, "Device Type ID 1 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId1));
if (mInitTable[FlashIndex].BiosStartOffset == (UINTN) (-1)) {
DEBUG ((EFI_D_ERROR, "ERROR - The size of BIOS image is bigger than SPI Flash device!\n"));
CpuDeadLoop ();
}
break;
} else {
SpiNotMatchError++;
}
} else {
SpiReadError++;
}
}
}
DEBUG ((EFI_D_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 = 0x%X\n", SfId[0], SfId[1], SfId[2]));
if (FlashIndex < EnumSpiFlashMax) {
return EFI_SUCCESS;
} else {
if (SpiReadError != 0) {
DEBUG ((EFI_D_ERROR, "ERROR - SPI Read ID execution failed! Error Count = %d\n", SpiReadError));
}
else {

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Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.inf Normal file
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#
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FlashDeviceLib
FILE_GUID = E38A1C3C-928C-4bf7-B6C1-7F0EF163FAA5
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = FlashDeviceLib | DXE_SMM_DRIVER DXE_RUNTIME_DRIVER
CONSTRUCTOR = LibFvbFlashDeviceSupportInit
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
FlashDeviceLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec

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Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.h Normal file
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/*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Library/SpiFlash.H>
#define FLASH_SIZE 0x300000
#define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1)
//
// Serial Flash device initialization data table provided to the
// Intel(R) SPI Host Controller Compatibility Interface.
//
SPI_INIT_TABLE mInitTable[] = {
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25QXX, // DeviceId 0
SF_DEVICE_ID1_W25Q64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_ATMEL, // VendorId
SF_DEVICE_ID0_AT25DF321A, // DeviceId 0
SF_DEVICE_ID1_AT25DF321A, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_ATMEL, // VendorId
SF_DEVICE_ID0_AT26DF321, // DeviceId 0
SF_DEVICE_ID1_AT26DF321, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_ATMEL, // VendorId
SF_DEVICE_ID0_AT25DF641, // DeviceId 0
SF_DEVICE_ID1_AT25DF641, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25QXX, // DeviceId 0
SF_DEVICE_ID1_W25Q16, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25QXX, // DeviceId 0
SF_DEVICE_ID1_W25Q32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register.
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25XXX, // DeviceId 0
SF_DEVICE_ID1_W25X32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25XXX, // DeviceId 0
SF_DEVICE_ID1_W25X64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_WINBOND, // VendorId
SF_DEVICE_ID0_W25QXX, // DeviceId 0
SF_DEVICE_ID1_W25Q128, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25LXX, // DeviceId 0
SF_DEVICE_ID1_MX25L16, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25LXX, // DeviceId 0
SF_DEVICE_ID1_MX25L32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25LXX, // DeviceId 0
SF_DEVICE_ID1_MX25L64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25LXX, // DeviceId 0
SF_DEVICE_ID1_MX25L128, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_MACRONIX, // VendorId
SF_DEVICE_ID0_MX25UXX, // DeviceId 0
SF_DEVICE_ID1_MX25U6435F, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_SST, // VendorId
SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
SF_DEVICE_ID1_SST25VF016B,// DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_SST, // VendorId
SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
SF_DEVICE_ID1_SST25VF064C,// DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
//
// Minnow2 SPI type
//
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_N25Q064, // DeviceId 0
SF_DEVICE_ID1_N25Q064, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle20MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle20MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle20MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle20MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_M25PXXX, // DeviceId 0
SF_DEVICE_ID1_M25PX16, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_N25QXXX, // DeviceId 0
SF_DEVICE_ID1_N25Q032, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_M25PXXX, // DeviceId 0
SF_DEVICE_ID1_M25PX32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_M25PXXX, // DeviceId 0
SF_DEVICE_ID1_M25PX64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_NUMONYX, // VendorId
SF_DEVICE_ID0_N25QXXX, // DeviceId 0
SF_DEVICE_ID1_N25Q128, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_EON, // VendorId
SF_DEVICE_ID0_EN25QXX, // DeviceId 0
SF_DEVICE_ID1_EN25Q16, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_EON, // VendorId
SF_DEVICE_ID0_EN25QXX, // DeviceId 0
SF_DEVICE_ID1_EN25Q32, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_EON, // VendorId
SF_DEVICE_ID0_EN25QXX, // DeviceId 0
SF_DEVICE_ID1_EN25Q64, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_EON, // VendorId
SF_DEVICE_ID0_EN25QXX, // DeviceId 0
SF_DEVICE_ID1_EN25Q128, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.
//
((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
//
// The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
//
FLASH_SIZE
},
{
SF_VENDOR_ID_AMIC, // VendorId
SF_DEVICE_ID0_A25L016, // DeviceId 0
SF_DEVICE_ID1_A25L016, // DeviceId 1
{
SF_INST_WREN, // Prefix Opcode 0: Write Enable
SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
},
{
{EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
{EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
{EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
{EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
{EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
{EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
{EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
},
//
// The offset of the start of the BIOS image in flash. This value is platform specific
// and depends on the system flash map. If BIOS size is bigger than flash return -1.