Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
@@ -0,0 +1,535 @@
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/** @file
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Gpio setting for multiplatform..
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Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <BoardGpios.h>
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#include <Guid/SetupVariable.h>
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//
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//AlpineValley platform ocde begin
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//
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#define AV_SC_REG_GPIOS_MUXES_SEL0 0x48
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#define AV_SC_REG_GPIOS_MUXES_SEL1 0x4C
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#define AV_SC_REG_GPIOS_MUXES_SEL2 0x50
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#define AV_SC_REG_GPIOS_MUXES_EN0 0x54
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#define AV_SC_REG_GPIOS_MUXES_EN1 0x58
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#define AV_SC_REG_GPIOS_MUXES_EN2 0x5C
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//
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//AlpineValley platform code end
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//
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EFI_GUID gPeiSmbusPpiGuid = EFI_PEI_SMBUS_PPI_GUID;
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/**
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@param None
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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ConfigurePlatformSysCtrlGpio (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *SmbusPpi
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)
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{
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//
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//AlpineValley platform code begin
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//
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// Initialize GPIO Settings:
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//
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UINT32 Status;
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EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
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DEBUG ((EFI_D_INFO, "ConfigurePlatformSysCtrlGpio()...\n"));
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//
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// Obtain Platform Info from HOB.
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//
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Status = GetPlatformInfoHob ((const EFI_PEI_SERVICES **)PeiServices, &PlatformInfoHob);
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ASSERT_EFI_ERROR (Status);
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//
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// The GPIO settings are dependent upon the platform. Obtain the Board ID through
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// the EC to determine the current platform.
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//
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DEBUG ((EFI_D_INFO, "Platform Flavor | Board ID = 0x%X | 0x%X\n", PlatformInfoHob->PlatformFlavor, PlatformInfoHob->BoardId));
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Status = (**PeiServices).LocatePpi (
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(const EFI_PEI_SERVICES **)PeiServices,
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&gPeiSmbusPpiGuid,
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0,
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NULL,
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(void **)&SmbusPpi
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Select/modify the GPIO initialization data based on the Board ID.
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//
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switch (PlatformInfoHob->BoardId)
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{
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default:
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Status = EFI_SUCCESS;
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//
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// Do nothing for other RVP boards.
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//
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break;
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}
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return Status;
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}
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static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiPeiSmbusPpiGuid,
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ConfigurePlatformSysCtrlGpio
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}
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};
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EFI_STATUS
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InstallPlatformSysCtrlGPIONotify (
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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EFI_STATUS Status;
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DEBUG ((EFI_D_INFO, "InstallPlatformSysCtrlGPIONotify()...\n"));
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Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
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/**
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Returns the Correct GPIO table for Mobile/Desktop respectively.
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Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
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@param PeiServices General purpose services available to every PEIM.
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@param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
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@param BoardId BoardId ID as determined through the EC.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_DEVICE_ERROR KSC fails to respond.
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**/
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EFI_STATUS
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MultiPlatformGpioTableInit (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
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)
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{
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EFI_STATUS Status;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
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UINTN VarSize;
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SYSTEM_CONFIGURATION SystemConfiguration;
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DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));
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//
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// Select/modify the GPIO initialization data based on the Board ID.
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//
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switch (PlatformInfoHob->BoardId) {
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case BOARD_ID_MINNOW2: // Minnow2
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Status = (**PeiServices).LocatePpi (
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PeiServices,
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&gEfiPeiReadOnlyVariable2PpiGuid,
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0,
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NULL,
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(void **)&PeiReadOnlyVarPpi
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);
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ASSERT_EFI_ERROR (Status);
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VarSize = sizeof (SYSTEM_CONFIGURATION);
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Status = PeiReadOnlyVarPpi->GetVariable (
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PeiReadOnlyVarPpi,
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PLATFORM_SETUP_VARIABLE_NAME,
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&gEfiSetupVariableGuid,
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NULL,
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&VarSize,
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&SystemConfiguration
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);
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if (SystemConfiguration.GpioWakeCapability == 1) {
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PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData2;
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}
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else {
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PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData;
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}
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PlatformInfoHob->PlatformGpioData_NC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_NC[0];
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PlatformInfoHob->PlatformGpioData_SC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SC[0];
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PlatformInfoHob->PlatformGpioData_SUS = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SUS[0];
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break;
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}
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return EFI_SUCCESS;
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}
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UINT32
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GPIORead32 (
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IN UINT32 mmio_conf
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)
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{
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UINT32 conf_val;
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UINT32 i;
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conf_val = MmioRead32(mmio_conf);
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for(i=0;i<5;i++){
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if(conf_val == 0xffffffff)
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conf_val = MmioRead32(mmio_conf);
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else
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break;
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}
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return conf_val;
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}
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/**
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Set GPIO CONF0 and PAD_VAL registers for NC/SC/SUS GPIO clusters
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@param Gpio_Mmio_Offset GPIO_SCORE_OFFSET or GPIO_NCORE_OFFSET or GPIO_SSUS_OFFSET.
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@param Gpio_Pin_Num Pin numbers to config for each GPIO clusters.
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@param Gpio_Conf_Data GPIO_CONF_PAD_INIT data array for each GPIO clusters.
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**/
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VOID
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InternalGpioConfig (
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IN UINT32 Gpio_Mmio_Offset,
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IN UINT32 Gpio_Pin_Num,
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GPIO_CONF_PAD_INIT* Gpio_Conf_Data
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)
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{
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UINT32 index;
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UINT32 mmio_conf0;
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UINT32 mmio_padval;
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PAD_CONF0 conf0_val;
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PAD_VAL pad_val;
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//
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// GPIO WELL -- Memory base registers
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//
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// A0 BIOS Spec doesn't mention it although X0 does. comment out now.
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// GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
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//
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for(index=0; index < Gpio_Pin_Num; index++)
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{
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//
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// Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
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//
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mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
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mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
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#ifdef EFI_DEBUG
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DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
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#endif
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DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
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Gpio_Conf_Data[index].usage,
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Gpio_Conf_Data[index].func,
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Gpio_Conf_Data[index].int_type,
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Gpio_Conf_Data[index].pull,
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mmio_conf0));
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//
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// Step 1: PadVal Programming.
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//
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pad_val.dw = GPIORead32(mmio_padval);
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//
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// Config PAD_VAL only for GPIO (Non-Native) Pin
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//
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if(Native != Gpio_Conf_Data[index].usage)
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{
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pad_val.dw &= ~0x6; // Clear bits 1:2
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pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
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//
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// set GPO default value
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//
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if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
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{
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pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
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}
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}
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DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
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MmioWrite32(mmio_padval, pad_val.dw);
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//
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// Step 2: CONF0 Programming
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// Read GPIO default CONF0 value, which is assumed to be default value after reset.
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//
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conf0_val.dw = GPIORead32(mmio_conf0);
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//
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// Set Function #
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//
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conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
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if(GPO == Gpio_Conf_Data[index].usage)
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{
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//
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// If used as GPO, then internal pull need to be disabled.
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//
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conf0_val.r.Pull_assign = 0; // Non-pull
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}
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else
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{
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//
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// Set PullUp / PullDown
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//
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if(P_20K_H == Gpio_Conf_Data[index].pull)
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{
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conf0_val.r.Pull_assign = 0x1; // PullUp
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conf0_val.r.Pull_strength = 0x2;// 20K
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}
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else if(P_20K_L == Gpio_Conf_Data[index].pull)
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{
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conf0_val.r.Pull_assign = 0x2; // PullDown
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conf0_val.r.Pull_strength = 0x2;// 20K
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}
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else if(P_10K_H == Gpio_Conf_Data[index].pull)
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{
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conf0_val.r.Pull_assign = 0x1; // PullUp
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conf0_val.r.Pull_strength = 0x1;// 10K
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}
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else if(P_10K_L == Gpio_Conf_Data[index].pull)
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{
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conf0_val.r.Pull_assign = 0x2; // PullDown
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conf0_val.r.Pull_strength = 0x1;// 10K
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}
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else if(P_2K_H == Gpio_Conf_Data[index].pull)
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{
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conf0_val.r.Pull_assign = 0x1; // PullUp
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conf0_val.r.Pull_strength = 0x0;// 2K
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}
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else if(P_2K_L == Gpio_Conf_Data[index].pull)
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{
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conf0_val.r.Pull_assign = 0x2; // PullDown
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conf0_val.r.Pull_strength = 0x0;// 2K
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}
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else if(P_NONE == Gpio_Conf_Data[index].pull)
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{
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conf0_val.r.Pull_assign = 0; // Non-pull
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}
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else
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{
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ASSERT(FALSE); // Invalid value
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}
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}
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//
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// Set INT Trigger Type
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//
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conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
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//
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// Set INT Trigger Type
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//
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if(TRIG_ == Gpio_Conf_Data[index].int_type)
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{
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//
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// Interrupt not capable, clear bits 27:24
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//
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}
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else
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{
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conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
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}
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DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
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|
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//
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||||
// Write back the targeted GPIO config value according to platform (board) GPIO setting.
|
||||
//
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MmioWrite32 (mmio_conf0, conf0_val.dw);
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}
|
||||
|
||||
//
|
||||
// A0 BIOS Spec doesn't mention it although X0 does. comment out now.
|
||||
// GPIO SCORE write 0x01001002 to IOBASE + 0x0900
|
||||
//
|
||||
}
|
||||
|
||||
/**
|
||||
Returns the Correct GPIO table for Mobile/Desktop respectively.
|
||||
Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
|
||||
|
||||
@param PeiServices General purpose services available to every PEIM.
|
||||
@param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
|
||||
@param BoardId BoardId ID as determined through the EC.
|
||||
|
||||
@retval EFI_SUCCESS The function completed successfully.
|
||||
@retval EFI_DEVICE_ERROR KSC fails to respond.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
MultiPlatformGpioProgram (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
|
||||
)
|
||||
{
|
||||
#if !_SIMIC_
|
||||
CFIO_INIT_STRUCT* PlatformCfioDataPtr;
|
||||
|
||||
PlatformCfioDataPtr = (CFIO_INIT_STRUCT *) (UINTN) PlatformInfoHob->PlatformCfioData;
|
||||
DEBUG ((EFI_D_INFO, "MultiPlatformGpioProgram()...\n"));
|
||||
|
||||
//
|
||||
// SCORE GPIO WELL -- IO base registers
|
||||
//
|
||||
|
||||
//
|
||||
// GPIO_USE_SEL Register -> 1 = GPIO 0 = Native
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, PlatformCfioDataPtr->Use_Sel_SC0);
|
||||
|
||||
//
|
||||
// Set GP_LVL Register
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL , PlatformCfioDataPtr->GP_Lvl_SC0);
|
||||
|
||||
//
|
||||
// GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL, PlatformCfioDataPtr->Io_Sel_SC0);
|
||||
|
||||
//
|
||||
// GPIO Triger Positive Edge Enable Register
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE, PlatformCfioDataPtr->TPE_SC0);
|
||||
|
||||
//
|
||||
// GPIO Trigger Negative Edge Enable Register
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE, PlatformCfioDataPtr->TNE_SC0);
|
||||
|
||||
//
|
||||
// GPIO Trigger Status
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS, PlatformCfioDataPtr->TS_SC0);
|
||||
|
||||
//
|
||||
// GPIO_USE_SEL2 Register -> 1 = GPIO 0 = Native
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2, PlatformCfioDataPtr->Use_Sel_SC1);
|
||||
|
||||
//
|
||||
// Set GP_LVL2 Register
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2, PlatformCfioDataPtr->GP_Lvl_SC1);
|
||||
|
||||
//
|
||||
// GP_IO_SEL2 Register -> 1 = Input 0 = Output. If Native Mode don't care
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2, PlatformCfioDataPtr->Io_Sel_SC1);
|
||||
|
||||
//
|
||||
// GPIO_USE_SEL3 Register -> 1 = GPIO 0 = Native
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3, PlatformCfioDataPtr->Use_Sel_SC2);
|
||||
|
||||
//
|
||||
// Set GP_LVL3 Register
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL3, PlatformCfioDataPtr->GP_Lvl_SC2);
|
||||
|
||||
//
|
||||
// GP_IO_SEL3 Register -> 1 = Input 0 = Output if Native Mode don't care
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL3, PlatformCfioDataPtr->Io_Sel_SC2);
|
||||
|
||||
//
|
||||
// SUS GPIO WELL -- IO base registers
|
||||
//
|
||||
|
||||
//
|
||||
// GPIO_USE_SEL Register -> 1 = GPIO 0 = Native
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_USE_SEL, PlatformCfioDataPtr->Use_Sel_SS);
|
||||
|
||||
//
|
||||
// Set GP_LVL Register
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_LVL , PlatformCfioDataPtr->GP_Lvl_SS);
|
||||
|
||||
//
|
||||
// GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care.
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_IO_SEL, PlatformCfioDataPtr->Io_Sel_SS);
|
||||
|
||||
//
|
||||
// GPIO Triger Positive Edge Enable Register.
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TPE, PlatformCfioDataPtr->TPE_SS);
|
||||
|
||||
//
|
||||
// GPIO Trigger Negative Edge Enable Register.
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TNE, PlatformCfioDataPtr->TNE_SS);
|
||||
|
||||
//
|
||||
// GPIO Trigger Status.
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS, PlatformCfioDataPtr->TS_SS);
|
||||
|
||||
//
|
||||
// GPIO Wake Enable.
|
||||
//
|
||||
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN, PlatformCfioDataPtr->WE_SS);
|
||||
|
||||
//
|
||||
// Config SC/NC/SUS GPIO Pins
|
||||
//
|
||||
switch (PlatformInfoHob->BoardId) {
|
||||
case BOARD_ID_MINNOW2:
|
||||
DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));
|
||||
InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SC);
|
||||
InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);
|
||||
InternalGpioConfig(GPIO_SSUS_OFFSET, sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SUS);
|
||||
break;
|
||||
default:
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// configure the CFIO Pnp settings
|
||||
//
|
||||
if (PlatformInfoHob->CfioEnabled) {
|
||||
if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2){
|
||||
Reference in New Issue
Block a user