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Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

Browse Source 
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, 

which are for MinnowBoard MAX open source project.


Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
2015-01-12 09:37:20 +00:00
committed by zwei4
parent 6f785cfcc3
commit 3cbfba02fe
518 changed files with 118538 additions and 0 deletions
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69
Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h Normal file
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/** @file
Header file of Serial port hardware definition.
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as
permitted by such license, no part of this software or
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written
consent of Intel Corporation.
Module Name: PlatformSerialPortLib.h
**/
#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
#define __PLATFORM_SERIAL_PORT_LIB_H_
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/SerialPortLib.h>
//
// UART Register Offsets
//
#define BAUD_LOW_OFFSET 0x00
#define BAUD_HIGH_OFFSET 0x01
#define IER_OFFSET 0x01
#define LCR_SHADOW_OFFSET 0x01
#define FCR_SHADOW_OFFSET 0x02
#define IR_CONTROL_OFFSET 0x02
#define FCR_OFFSET 0x02
#define EIR_OFFSET 0x02
#define BSR_OFFSET 0x03
#define LCR_OFFSET 0x03
#define MCR_OFFSET 0x04
#define LSR_OFFSET 0x05
#define MSR_OFFSET 0x06
//
// UART Register Bit Defines
//
#define LSR_TXRDY 0x20
#define LSR_RXDA 0x01
#define DLAB 0x01
#define UART_DATA 8
#define UART_STOP 1

262
Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c Normal file
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/** @file
Serial I/O Port library functions with no library constructor/destructor
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as
permitted by such license, no part of this software or
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written
consent of Intel Corporation.
Module Name: SerialPortLib.c
**/
#include "PlatformSerialPortLib.h"
UINT16 gComBase = 0x3f8;
UINTN gBps = 115200;
UINT8 gData = 8;
UINT8 gStop = 1;
UINT8 gParity = 0;
UINT8 gBreakSet = 0;
/**
Initialize Serial Port
The Baud Rate Divisor registers are programmed and the LCR
is used to configure the communications format. Hard coded
UART config comes from globals in DebugSerialPlatform lib.
@param None
@retval None
**/
RETURN_STATUS
EFIAPI
UARTInitialize (
VOID
)
{
UINTN Divisor;
UINT8 OutputData;
UINT8 Data;
//
// Map 5..8 to 0..3
//
Data = (UINT8) (gData - (UINT8) 5);
//
// Calculate divisor for baud generator
//
Divisor = 115200 / gBps;
//
// Set communications format
//
OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
IoWrite8 (gComBase + LCR_OFFSET, OutputData);
//
// Configure baud rate
//
IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));
IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
//
// Switch back to bank 0
//
OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
IoWrite8 (gComBase + LCR_OFFSET, OutputData);
return RETURN_SUCCESS;
}
/**
Common function to initialize UART Serial device and USB Serial device.
@param None
@retval None
**/
RETURN_STATUS
EFIAPI
SerialPortInitialize (
VOID
)
{
UARTInitialize ();
return RETURN_SUCCESS;
}
/**
Write data to serial device.
If the buffer is NULL, then return 0;
if NumberOfBytes is zero, then return 0.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device.
**/
UINTN
EFIAPI
UARTDbgOut (
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
UINTN Result;
UINT8 Data;
if (NULL == Buffer) {
return 0;
}
Result = NumberOfBytes;
while (NumberOfBytes--) {
//
// Wait for the serial port to be ready.
//
do {
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
} while ((Data & LSR_TXRDY) == 0);
IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++);
}
return Result;
}
/**
Common function to write data to UART Serial device and USB Serial device.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
**/
UINTN
EFIAPI
SerialPortWrite (
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgOut (Buffer, NumberOfBytes);
}
return RETURN_SUCCESS;
}
/**
Read data from serial device and save the datas in buffer.
If the buffer is NULL, then return 0;
if NumberOfBytes is zero, then return 0.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.
@retval !0 Actual number of bytes raed to serial device.
**/
UINTN
EFIAPI
UARTDbgIn (
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
UINTN Result;
UINT8 Data;
if (NULL == Buffer) {
return 0;
}
Result = NumberOfBytes;
while (NumberOfBytes--) {
//
// Wait for the serial port to be ready.
//
do {
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
} while ((Data & LSR_RXDA) == 0);
*Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase));
}
return Result;
}
/**
Common function to Read data from UART serial device, USB serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
**/
UINTN
EFIAPI
SerialPortRead (
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgIn (Buffer, NumberOfBytes);
}
return RETURN_SUCCESS;
}
/**
Polls a serial device to see if there is any data waiting to be read.
Polls aserial device to see if there is any data waiting to be read.
If there is data waiting to be read from the serial device, then TRUE is returned.
If there is no data waiting to be read from the serial device, then FALSE is returned.
@retval TRUE Data is waiting to be read from the serial device.
@retval FALSE There is no data waiting to be read from the serial device.
**/
BOOLEAN
EFIAPI
SerialPortPoll (
VOID
)
{

57
Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf Normal file
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#/** @file
#
# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SerialPortLib
FILE_GUID = 15B26F43-A389-4bae-BDE3-4BB0719B7D4F
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = SerialPortLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF
#
[Sources]
SerialPortLib.c
SioInit.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
Vlv2TbltDevicePkg/PlatformPkg.dec
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
[LibraryClasses]
BaseLib
PcdLib
IoLib
PciLib
TimerLib

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Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c Normal file
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/** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
SioInit.c
Abstract:
Functions for LpcSio initialization
--*/
#include "PlatformSerialPortLib.h"
#include "SioInit.h"
typedef struct {
UINT8 Register;
UINT8 Value;
} EFI_SIO_TABLE;
EFI_SIO_TABLE mSioTableWpcn381u[] = {
{0x29, 0x0A0},
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{0x21, 0x001}, // Global Device Enable
{0x26, 0x000}
};
EFI_SIO_TABLE mSioTableWdcp376[] = {
{0x29, 0x0A0},
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{0x21, 0x001}, // Global Device Enable
{0x26, 0x000},
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K}, // Select PS2 Keyboard
{WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address MSB
{WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base Address LSB
{WPCN381U_IRQ1_REGISTER, 0x011}, // Set to IRQ1
{0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC Clock Source
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
{WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M}, // Select PS2 Mouse
{WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to IRQ12
{WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE} // Enable it with Activation bit
};
/**
Initialization for SIO.
@param FfsHeader FV this PEIM was loaded from.
@param PeiServices General purpose services available to every PEIM.
None
**/
VOID
InitializeSio (
VOID
)
{
UINT16 Index;
UINT16 IndexPort;
UINT16 DataPort;
//
// Super I/O initialization for Winbond WPCN381U
//
IndexPort = WPCN381U_CONFIG_INDEX;
DataPort = WPCN381U_CONFIG_DATA;
//
// Check for Winbond WPCN381U
//
IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond WPCN381U Device ID register is 0x20
if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U Device ID is 0xF4
//
// Configure WPCN381U SIO
//
for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
}
}
if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376 Device ID is 0xF1
//

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Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h Normal file
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/** @file
Header file of Serial port hardware definition.
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as
permitted by such license, no part of this software or
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written
consent of Intel Corporation.
Module Name: PlatformSerialPortLib.h
**/
#ifndef _SIO_INIT_H_
#define _SIO_INIT_H_
#define WPCN381U_CONFIG_INDEX 0x2E
#define WPCN381U_CONFIG_DATA 0x2F
#define WPCN381U_CONFIG_INDEX1 0x164E
#define WPCN381U_CONFIG_DATA1 0x164F
#define WPCN381U_CHIP_ID 0xF4
#define WDCP376_CHIP_ID 0xF1
//
// SIO Logical Devices Numbers
//
#define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller
#define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller
#define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller
#define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller
#define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller
#define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller
#define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source
#define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO
//
// SIO Registers Layout
//
#define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address
#define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address
#define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address
#define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address
#define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address
#define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address
#define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address
#define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address
#define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address
//
// SIO Activation Values
//
#define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device
#define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device
//
// SIO GPIO
//