Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
517
Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
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517
Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
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@@ -0,0 +1,517 @@
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/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PciDevice.c
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Abstract:
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Platform Initialization Driver.
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Revision History
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--*/
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#include "PlatformDxe.h"
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#include "Library/DxeServicesTableLib.h"
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#include "PciBus.h"
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#include "Guid/PciLanInfo.h"
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extern VOID *mPciLanInfo;
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extern UINTN mPciLanCount;
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extern EFI_HANDLE mImageHandle;
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extern SYSTEM_CONFIGURATION mSystemConfiguration;
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VOID *mPciRegistration;
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#define NCR_VENDOR_ID 0x1000
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#define ATI_VENDOR_ID 0x1002
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#define INTEL_VENDOR_ID 0x8086
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#define ATI_RV423_ID 0x5548
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#define ATI_RV423_ID2 0x5d57
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#define ATI_RV380_ID 0x3e50
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#define ATI_RV370_ID 0x5b60
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#define SI_VENDOR_ID 0x1095
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#define SI_SISATA_ID 0x3114
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#define SI_SIRAID_PCIUNL 0x40
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#define INTEL_82573E_IDER 0x108D
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typedef struct {
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UINT8 ClassCode;
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UINT8 SubClassCode;
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UINT16 VendorId;
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UINT16 DeviceId;
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} BAD_DEVICE_TABLE;
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BAD_DEVICE_TABLE BadDeviceTable[] = {
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{(UINT8)PCI_CLASS_MASS_STORAGE,(UINT8)PCI_CLASS_MASS_STORAGE_SCSI,(UINT16)NCR_VENDOR_ID, (UINT16)0xffff}, // Any NCR cards
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{(UINT8)PCI_CLASS_MASS_STORAGE,(UINT8)PCI_CLASS_MASS_STORAGE_IDE,(UINT16)INTEL_VENDOR_ID, (UINT16)INTEL_82573E_IDER}, // Intel i82573E Tekoa GBit Lan IDE-R
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{(UINT8)0xff,(UINT8)0xff,(UINT16)0xffff,(UINT16)0xffff}
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};
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EFI_STATUS
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PciBusDriverHook (
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)
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{
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EFI_STATUS Status;
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EFI_EVENT FilterEvent;
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//
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// Register for callback to PCI I/O protocol
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//
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Status = gBS->CreateEvent (
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EVT_NOTIFY_SIGNAL,
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TPL_CALLBACK,
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PciBusEvent,
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NULL,
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&FilterEvent
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);
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ASSERT_EFI_ERROR(Status);
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//
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// Register for protocol notifications on this event
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//
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Status = gBS->RegisterProtocolNotify (
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&gEfiPciIoProtocolGuid,
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FilterEvent,
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&mPciRegistration
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);
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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VOID
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InitBadBars(
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT16 VendorId,
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IN UINT16 DeviceId
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)
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{
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EFI_STATUS Status;
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PCI_IO_DEVICE *PciIoDevice;
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UINT64 BaseAddress = 0;
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UINT64 TempBaseAddress = 0;
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UINT8 RevId = 0;
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UINT32 Bar;
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UINT64 IoSize;
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UINT64 MemSize;
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UINTN MemSizeBits;
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PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
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switch ( VendorId) {
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case ATI_VENDOR_ID:
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//
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// ATI fix-ups. At this time all ATI cards in BadDeviceTable
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// have same problem in that OPROM BAR needs to be increased.
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//
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Bar = 0x30 ;
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//
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// Get original BAR address
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//
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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Bar,
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1,
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(VOID *) &BaseAddress
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);
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//
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// Find BAR size
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//
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TempBaseAddress = 0xffffffff;
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Status = PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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Bar,
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1,
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(VOID *) &TempBaseAddress
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);
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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Bar,
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1,
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(VOID *) &TempBaseAddress
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);
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TempBaseAddress &= 0xfffffffe;
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MemSize = 1;
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while ((TempBaseAddress & 0x01) == 0) {
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TempBaseAddress = TempBaseAddress >> 1;
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MemSize = MemSize << 1;
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}
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//
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// Free up allocated memory memory and re-allocate with increased size.
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//
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Status = gDS->FreeMemorySpace (
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BaseAddress,
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MemSize
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);
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//
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// Force new alignment
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//
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MemSize = 0x8000000;
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MemSizeBits = 28;
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Status = gDS->AllocateMemorySpace (
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EfiGcdAllocateAnySearchBottomUp,
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EfiGcdMemoryTypeMemoryMappedIo,
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MemSizeBits, // Alignment
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MemSize,
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&BaseAddress,
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mImageHandle,
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NULL
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);
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Status = PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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Bar,
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1,
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(VOID *) &BaseAddress
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);
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break;
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case NCR_VENDOR_ID:
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#define MIN_NCR_IO_SIZE 0x800
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#define NCR_GRAN 11 // 2**11 = 0x800
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//
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// NCR SCSI cards like 8250S lie about IO needed. Assign as least 0x80.
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//
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for (Bar = 0x10; Bar < 0x28; Bar+= 4) {
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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Bar,
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1,
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(VOID *) &BaseAddress
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);
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if (BaseAddress && 0x01) {
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TempBaseAddress = 0xffffffff;
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Status = PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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Bar,
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1,
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(VOID *) &TempBaseAddress
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);
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TempBaseAddress &= 0xfffffffc;
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IoSize = 1;
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while ((TempBaseAddress & 0x01) == 0) {
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TempBaseAddress = TempBaseAddress >> 1;
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IoSize = IoSize << 1;
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}
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if (IoSize < MIN_NCR_IO_SIZE) {
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Status = gDS->FreeIoSpace (
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BaseAddress,
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IoSize
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);
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Status = gDS->AllocateIoSpace (
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EfiGcdAllocateAnySearchTopDown,
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EfiGcdIoTypeIo,
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NCR_GRAN, // Alignment
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MIN_NCR_IO_SIZE,
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&BaseAddress,
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mImageHandle,
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NULL
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);
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TempBaseAddress = BaseAddress + 1;
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Status = PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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Bar,
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1,
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(VOID *) &TempBaseAddress
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);
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}
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}
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}
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break;
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case INTEL_VENDOR_ID:
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if (DeviceId == INTEL_82573E_IDER) {
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//
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// Tekoa i82573E IDE-R fix-ups. At this time A2 step and earlier parts do not
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// support any BARs except BAR0. Other BARS will actualy map to BAR0 so disable
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// them all for Control Blocks and Bus mastering ops as well as Secondary IDE
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// Controller.
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// All Tekoa A2 or earlier step chips for now.
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//
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint8,
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PCI_REVISION_ID_OFFSET,
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1,
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&RevId
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);
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if (RevId <= 0x02) {
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for (Bar = 0x14; Bar < 0x24; Bar+= 4) {
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//
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// Maybe want to clean this up a bit later but for now just clear out the secondary
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// Bars don't worry aboyut freeing up thge allocs.
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//
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TempBaseAddress = 0x0;
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Status = PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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Bar,
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1,
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(VOID *) &TempBaseAddress
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);
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} // end for
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}
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else
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{
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//
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//Tekoa A3 or above:
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//Clear bus master base address (PCI register 0x20)
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//since Tekoa does not fully support IDE Bus Mastering
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//
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TempBaseAddress = 0x0;
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Status = PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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0x20,
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1,
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(VOID *) &TempBaseAddress
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);
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}
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}
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break;
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default:
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break;
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}
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return;
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}
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VOID
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ProgramPciLatency(
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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EFI_STATUS Status;
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//
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// Program Master Latency Timer
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//
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if (mSystemConfiguration.PciLatency != 0) {
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Status = PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint8,
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PCI_LATENCY_TIMER_OFFSET,
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1,
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&mSystemConfiguration.PciLatency
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);
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}
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return;
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}
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/**
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During S5 shutdown, we need to program PME in all LAN devices.
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Here we identify LAN devices and save their bus/dev/func.
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**/
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VOID
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SavePciLanAddress(
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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EFI_STATUS Status;
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UINTN PciSegment,
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PciBus,
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PciDevice,
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PciFunction;
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VOID *NewBuffer;
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PCI_LAN_INFO *x;
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Status = PciIo->GetLocation (
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PciIo,
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&PciSegment,
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&PciBus,
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&PciDevice,
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&PciFunction
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);
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if (EFI_ERROR (Status)) {
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return;
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}
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mPciLanCount ++;
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Status = gBS->AllocatePool (
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EfiBootServicesData,
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mPciLanCount * sizeof(PCI_LAN_INFO),
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&NewBuffer
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);
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if (EFI_ERROR (Status)) {
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return;
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}
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if (mPciLanCount > 1) {
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//
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// copy old data into new, larger buffer
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//
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gBS->CopyMem (
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NewBuffer,
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mPciLanInfo,
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(mPciLanCount - 1) * sizeof(PCI_LAN_INFO)
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);
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//
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// free the old memory buffer
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//
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gBS->FreePool (mPciLanInfo);
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}
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//
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// init the new entry
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//
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x = (PCI_LAN_INFO *)NewBuffer + (mPciLanCount - 1);
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x->PciBus = (UINT8)PciBus;
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x->PciDevice = (UINT8)PciDevice;
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x->PciFunction = (UINT8)PciFunction;
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mPciLanInfo = NewBuffer;
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return;
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}
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/**
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@param Event the event that is signaled.
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@param Context not used here.
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**/
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VOID
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EFIAPI
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PciBusEvent (
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IN EFI_EVENT Event,
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IN VOID* Context
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)
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{
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EFI_STATUS Status;
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UINTN BufferSize;
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EFI_HANDLE Handle;
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EFI_PCI_IO_PROTOCOL *PciIo;
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PCI_IO_DEVICE *PciIoDevice;
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UINT64 Supports;
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UINTN Index;
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UINT8 mCacheLineSize = 0x10;
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while (TRUE) {
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BufferSize = sizeof (EFI_HANDLE);
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Status = gBS->LocateHandle (
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ByRegisterNotify,
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NULL,
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mPciRegistration,
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&BufferSize,
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&Handle
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);
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if (EFI_ERROR (Status)) {
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//
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// If no more notification events exist
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//
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return;
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}
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Status = gBS->HandleProtocol (
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Handle,
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&gEfiPciIoProtocolGuid,
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(void **)&PciIo
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);
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PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
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//
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// Enable I/O for bridge so port 0x80 codes will come out
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//
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if (PciIoDevice->Pci.Hdr.VendorId == V_PCH_INTEL_VENDOR_ID)
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{
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Status = PciIo->Attributes(
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PciIo,
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EfiPciIoAttributeOperationSupported,
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0,
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&Supports
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);
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Supports &= EFI_PCI_DEVICE_ENABLE;
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Status = PciIo->Attributes (
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PciIo,
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EfiPciIoAttributeOperationEnable,
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Supports,
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NULL
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||||
);
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break;
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}
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//
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// Program PCI Latency Timer
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//
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ProgramPciLatency(PciIo);
|
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//
|
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// Program Cache Line Size to 64 bytes (0x10 DWORDs)
|
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//
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Status = PciIo->Pci.Write (
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PciIo,
|
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EfiPciIoWidthUint8,
|
||||
PCI_CACHELINE_SIZE_OFFSET,
|
||||
1,
|
||||
&mCacheLineSize
|
||||
);
|
||||
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//
|
||||
// If PCI LAN device, save bus/dev/func info
|
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// so we can program PME during S5 shutdown
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//
|
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if (PciIoDevice->Pci.Hdr.ClassCode[2] == PCI_CLASS_NETWORK) {
|
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SavePciLanAddress(PciIo);
|
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break;
|
||||
}
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||||
|
||||
//
|
||||
// Workaround for cards with bad BARs
|
||||
//
|
||||
Index = 0;
|
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while (BadDeviceTable[Index].ClassCode != 0xff) {
|
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if (BadDeviceTable[Index].DeviceId == 0xffff) {
|
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if ((PciIoDevice->Pci.Hdr.ClassCode[2] == BadDeviceTable[Index].ClassCode) &&
|
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(PciIoDevice->Pci.Hdr.ClassCode[1] == BadDeviceTable[Index].SubClassCode) &&
|
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(PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId)) {
|
||||
InitBadBars(PciIo,BadDeviceTable[Index].VendorId,BadDeviceTable[Index].DeviceId);
|
||||
}
|
||||
} else {
|
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if ((PciIoDevice->Pci.Hdr.ClassCode[2] == BadDeviceTable[Index].ClassCode) &&
|
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(PciIoDevice->Pci.Hdr.ClassCode[1] == BadDeviceTable[Index].SubClassCode) &&
|
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(PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId) &&
|
||||
(PciIoDevice->Pci.Hdr.DeviceId == BadDeviceTable[Index].DeviceId)) {
|
||||
|
||||
InitBadBars(PciIo,BadDeviceTable[Index].VendorId,BadDeviceTable[Index].DeviceId);
|
||||
}
|
||||
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Block a user