Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
426
Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c
Normal file
426
Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c
Normal file
@@ -0,0 +1,426 @@
|
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/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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||||
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||||
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||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
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||||
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||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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||||
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Module Name:
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BootMode.c
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Abstract:
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EFI PEIM to provide the platform support functionality on the Thurley.
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--*/
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#include "PlatformEarlyInit.h"
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#define NORMALMODE 0
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#define RECOVERYMODE 1
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#define SAFEMODE 2
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#define MANUFACTURINGMODE 3
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#define GPIO_SSUS_OFFSET 0x2000
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#define PMU_PWRBTN_B_OFFSET 0x88
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EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiBootInRecoveryModePpiGuid,
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NULL
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};
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/**
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Return the setting of the Bios configuration jumper
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@param VOID
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@retval RECOVERYMODE jumper set to recovery mode
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@retval SAFEMODE jumper set to config mode
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@retval NORMALMODE jumper in normal mode
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**/
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UINTN
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GetConfigJumper(
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
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)
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{
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//
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// Do the Forced recovery detection based on logic chart above
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//
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if (IsRecoveryJumper(PeiServices, PlatformInfoHob)) {
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return RECOVERYMODE;
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} else {
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return NORMALMODE;
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}
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}
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BOOLEAN
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CheckIfRecoveryMode(
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
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)
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{
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if (GetConfigJumper(PeiServices, PlatformInfoHob) == RECOVERYMODE) {
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return TRUE;
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}
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return FALSE;
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}
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BOOLEAN
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CheckIfSafeMode(
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
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)
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{
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if (GetConfigJumper(PeiServices, PlatformInfoHob) == SAFEMODE) {
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return TRUE;
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}
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return FALSE;
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}
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BOOLEAN
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CheckIfManufacturingMode (
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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EFI_STATUS Status;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
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UINT32 Attributes;
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UINTN DataSize;
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CHAR16 VarName[] = MFGMODE_VARIABLE_NAME;
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UINT8 MfgMode;
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Status = (*PeiServices)->LocatePpi (
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PeiServices,
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&gEfiPeiReadOnlyVariable2PpiGuid,
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0,
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NULL,
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(void **)&Variable
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Check if SW MMJ mode
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//
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Attributes = (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS);
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DataSize = sizeof (MFG_MODE_VAR);
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Status = Variable->GetVariable (
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Variable,
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VarName,
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&gMfgModeVariableGuid,
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&Attributes,
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&DataSize,
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&MfgMode
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);
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if (!(EFI_ERROR (Status))) {
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return TRUE;
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}
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return FALSE;
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}
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EFI_STATUS
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UpdateBootMode (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
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)
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{
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EFI_STATUS Status;
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EFI_BOOT_MODE BootMode;
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UINT16 SleepType;
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CHAR16 *strBootMode;
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PEI_CAPSULE_PPI *Capsule;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
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SYSTEM_CONFIGURATION SystemConfiguration;
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UINTN VarSize;
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volatile UINT32 GpioValue;
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BOOLEAN IsFirstBoot;
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UINT32 Data32;
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Status = (*PeiServices)->GetBootMode(
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PeiServices,
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&BootMode
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);
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ASSERT_EFI_ERROR (Status);
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if (BootMode == BOOT_IN_RECOVERY_MODE){
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return Status;
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}
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GetWakeupEventAndSaveToHob (PeiServices);
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//
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// Let's assume things are OK if not told otherwise
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//
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BootMode = BOOT_WITH_FULL_CONFIGURATION;
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//
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// When this boot is WDT reset, the system needs booting with CrashDump function eanbled.
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//
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Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS);
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//
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// Check Power Button, click the power button, the system will boot in fast boot mode,
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// if it is pressed and hold for a second, it will boot in FullConfiguration/setup mode.
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//
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GpioValue = MmioRead32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + PMU_PWRBTN_B_OFFSET); // The value of GPIOS_16 (PMU_PWRBTN_B)
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if (((GpioValue & BIT0) != 0)&&((Data32 & B_PCH_TCO_STS_SECOND_TO) != B_PCH_TCO_STS_SECOND_TO)){
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IsFirstBoot = PcdGetBool(PcdBootState);
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if (!IsFirstBoot){
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VarSize = sizeof (SYSTEM_CONFIGURATION);
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ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
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Status = (*PeiServices)->LocatePpi (
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PeiServices,
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&gEfiPeiReadOnlyVariable2PpiGuid,
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0,
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NULL,
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(void **)&Variable
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Use normal setup default from NVRAM variable,
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// the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
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//
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VarSize = sizeof(SYSTEM_CONFIGURATION);
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Status = Variable->GetVariable (
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Variable,
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L"Setup",
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&gEfiSetupVariableGuid,
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NULL,
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&VarSize,
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&SystemConfiguration
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);
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if (SystemConfiguration.FastBoot == 1) {
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BootMode = BOOT_WITH_MINIMAL_CONFIGURATION;
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}
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}
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}
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//
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// Check if we need to boot in forced recovery mode
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//
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if (CheckIfRecoveryMode(PeiServices, PlatformInfoHob)) {
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BootMode = BOOT_IN_RECOVERY_MODE;
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}
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if (BootMode == BOOT_IN_RECOVERY_MODE) {
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Status = (*PeiServices)->InstallPpi (
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PeiServices,
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&mPpiListRecoveryBootMode
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);
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ASSERT_EFI_ERROR (Status);
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} else {
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if (GetSleepTypeAfterWakeup (PeiServices, &SleepType)) {
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switch (SleepType) {
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case V_PCH_ACPI_PM1_CNT_S3:
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BootMode = BOOT_ON_S3_RESUME;
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//
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// Determine if we're in capsule update mode
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//
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Status = (*PeiServices)->LocatePpi (
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PeiServices,
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&gPeiCapsulePpiGuid,
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0,
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NULL,
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(void **)&Capsule
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);
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if (Status == EFI_SUCCESS) {
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if (Capsule->CheckCapsuleUpdate ((EFI_PEI_SERVICES**)PeiServices) == EFI_SUCCESS) {
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BootMode = BOOT_ON_FLASH_UPDATE;
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}
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}
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break;
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case V_PCH_ACPI_PM1_CNT_S4:
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BootMode = BOOT_ON_S4_RESUME;
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break;
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case V_PCH_ACPI_PM1_CNT_S5:
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BootMode = BOOT_ON_S5_RESUME;
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break;
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} // switch (SleepType)
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}
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//
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// Check for Safe Mode
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//
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}
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switch (BootMode) {
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case BOOT_WITH_FULL_CONFIGURATION:
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strBootMode = L"BOOT_WITH_FULL_CONFIGURATION";
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break;
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case BOOT_WITH_MINIMAL_CONFIGURATION:
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strBootMode = L"BOOT_WITH_MINIMAL_CONFIGURATION";
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break;
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case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
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strBootMode = L"BOOT_ASSUMING_NO_CONFIGURATION_CHANGES";
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break;
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case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:
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strBootMode = L"BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS";
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break;
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case BOOT_WITH_DEFAULT_SETTINGS:
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strBootMode = L"BOOT_WITH_DEFAULT_SETTINGS";
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break;
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case BOOT_ON_S4_RESUME:
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strBootMode = L"BOOT_ON_S4_RESUME";
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break;
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case BOOT_ON_S5_RESUME:
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strBootMode = L"BOOT_ON_S5_RESUME";
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break;
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case BOOT_ON_S2_RESUME:
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strBootMode = L"BOOT_ON_S2_RESUME";
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break;
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||||
case BOOT_ON_S3_RESUME:
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strBootMode = L"BOOT_ON_S3_RESUME";
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break;
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case BOOT_ON_FLASH_UPDATE:
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strBootMode = L"BOOT_ON_FLASH_UPDATE";
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break;
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||||
case BOOT_IN_RECOVERY_MODE:
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strBootMode = L"BOOT_IN_RECOVERY_MODE";
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||||
break;
|
||||
default:
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strBootMode = L"Unknown boot mode";
|
||||
} // switch (BootMode)
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||||
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||||
DEBUG ((EFI_D_ERROR, "Setting BootMode to %s\n", strBootMode));
|
||||
Status = (*PeiServices)->SetBootMode(
|
||||
PeiServices,
|
||||
BootMode
|
||||
);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
Get sleep type after wakeup
|
||||
|
||||
@param PeiServices Pointer to the PEI Service Table.
|
||||
@param SleepType Sleep type to be returned.
|
||||
|
||||
@retval TRUE A wake event occured without power failure.
|
||||
@retval FALSE Power failure occured or not a wakeup.
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
GetSleepTypeAfterWakeup (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
OUT UINT16 *SleepType
|
||||
)
|
||||
{
|
||||
UINT16 Pm1Sts;
|
||||
UINT16 Pm1Cnt;
|
||||
UINT16 GenPmCon1;
|
||||
GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
|
||||
|
||||
//
|
||||
// Read the ACPI registers
|
||||
//
|
||||
Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
|
||||
Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
|
||||
|
||||
if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR | B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) ||
|
||||
(Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) {
|
||||
//
|
||||
// If power failure indicator, then don't attempt s3 resume.
|
||||
// Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and memory has
|
||||
// lost already. This is to make sure no one will use PM1_CNT to check for S3 after
|
||||
// power failure.
|
||||
//
|
||||
if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
|
||||
Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) | V_PCH_ACPI_PM1_CNT_S5);
|
||||
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
|
||||
}
|
||||
//
|
||||
// Clear Wake Status (WAK_STS)
|
||||
//
|
||||
IoWrite16 ((ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS), B_PCH_ACPI_PM1_STS_WAK);
|
||||
}
|
||||
//
|
||||
// Get sleep type if a wake event occurred and there is no power failure
|
||||
//
|
||||
if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
|
||||
*SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
|
||||
return TRUE;
|
||||
} else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S4){
|
||||
*SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
|
||||
return TRUE;
|
||||
}
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
VOID
|
||||
SetPlatformBootMode (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
|
||||
)
|
||||
{
|
||||
EFI_PLATFORM_SETUP_ID PlatformSetupId;
|
||||
|
||||
ZeroMem(&PlatformSetupId, sizeof (EFI_PLATFORM_SETUP_ID));
|
||||
|
||||
CopyMem (&PlatformSetupId.SetupGuid,
|
||||
&gEfiNormalSetupGuid,
|
||||
sizeof (EFI_GUID));
|
||||
|
||||
if (CheckIfRecoveryMode(PeiServices, PlatformInfoHob)) {
|
||||
//
|
||||
// Recovery mode
|
||||
//
|
||||
CopyMem (&PlatformSetupId.SetupName,
|
||||
SAFE_SETUP_NAME,
|
||||
StrSize (SAFE_SETUP_NAME));
|
||||
PlatformSetupId.PlatformBootMode = PLATFORM_RECOVERY_MODE;
|
||||
} else if (CheckIfSafeMode(PeiServices, PlatformInfoHob)) {
|
||||
//
|
||||
// Safe mode also called config mode or maintenace mode.
|
||||
//
|
||||
CopyMem (&PlatformSetupId.SetupName,
|
||||
SAFE_SETUP_NAME,
|
||||
StrSize (SAFE_SETUP_NAME));
|
||||
PlatformSetupId.PlatformBootMode = PLATFORM_SAFE_MODE;
|
||||
|
||||
} else if(0) { // else if (CheckIfManufacturingMode(PeiServices)) {
|
||||
//
|
||||
// Manufacturing mode
|
||||
//
|
||||
CopyMem (&PlatformSetupId.SetupName,
|
||||
MANUFACTURE_SETUP_NAME,
|
||||
StrSize (MANUFACTURE_SETUP_NAME));
|
||||
PlatformSetupId.PlatformBootMode = PLATFORM_MANUFACTURING_MODE;
|
||||
|
||||
} else {
|
||||
//
|
||||
// Default to normal mode.
|
||||
//
|
||||
CopyMem (&PlatformSetupId.SetupName,
|
||||
&NORMAL_SETUP_NAME,
|
||||
StrSize (NORMAL_SETUP_NAME));
|
||||
PlatformSetupId.PlatformBootMode = PLATFORM_NORMAL_MODE;
|
||||
49
Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c
Normal file
49
Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c
Normal file
@@ -0,0 +1,49 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
|
||||
CpuInitPeim.c
|
||||
|
||||
Abstract:
|
||||
|
||||
Functions for LpcSio initilization
|
||||
It is needed for early onboard LAN controller disable/enable in platform setup.
|
||||
|
||||
--*/
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
PlatformCpuInit (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration,
|
||||
IN EFI_PLATFORM_CPU_INFO *PlatformCpuInfo
|
||||
)
|
||||
{
|
||||
BOOLEAN ResetRequired;
|
||||
|
||||
//
|
||||
// Variable initialization
|
||||
//
|
||||
324
Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c
Normal file
324
Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c
Normal file
@@ -0,0 +1,324 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
|
||||
Dimm.c
|
||||
|
||||
Abstract:
|
||||
|
||||
PPI for reading SPD modules on DIMMs.
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
//
|
||||
// Header Files
|
||||
//
|
||||
#include "Platformearlyinit.h"
|
||||
|
||||
#define DIMM_SOCKETS 4 // Total number of DIMM sockets allowed on
|
||||
// the platform
|
||||
#define DIMM_SEGMENTS 1 // Total number of Segments Per DIMM.
|
||||
#define MEMORY_CHANNELS 2 // Total number of memory channels
|
||||
// populated on the system board
|
||||
//
|
||||
// Prototypes
|
||||
//
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
GetDimmState (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_DIMM_PPI *This,
|
||||
IN UINT8 Dimm,
|
||||
OUT PEI_PLATFORM_DIMM_STATE *State
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SetDimmState (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_DIMM_PPI *This,
|
||||
IN UINT8 Dimm,
|
||||
IN PEI_PLATFORM_DIMM_STATE *State
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
ReadSpd (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_DIMM_PPI *This,
|
||||
IN UINT8 Dimm,
|
||||
IN UINT8 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT UINT8 *Buffer
|
||||
);
|
||||
|
||||
static PEI_PLATFORM_DIMM_PPI mGchDimmPpi = {
|
||||
DIMM_SOCKETS,
|
||||
DIMM_SEGMENTS,
|
||||
MEMORY_CHANNELS,
|
||||
GetDimmState,
|
||||
SetDimmState,
|
||||
ReadSpd
|
||||
};
|
||||
|
||||
static EFI_PEI_PPI_DESCRIPTOR mPpiPlatformDimm = {
|
||||
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
|
||||
&gPeiPlatformDimmPpiGuid,
|
||||
&mGchDimmPpi
|
||||
};
|
||||
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
/**
|
||||
This function returns the current state of a single DIMM. Present indicates
|
||||
that the DIMM slot is physically populated. Disabled indicates that the DIMM
|
||||
should not be used.
|
||||
|
||||
@param PeiServices PEI services table pointer
|
||||
@param This PPI pointer
|
||||
@param Dimm DIMM to read from
|
||||
@param State Pointer to a return buffer to be updated with the current state
|
||||
of the DIMM
|
||||
|
||||
@retval EFI_SUCCESS The function completed successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
GetDimmState (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_DIMM_PPI *This,
|
||||
IN UINT8 Dimm,
|
||||
OUT PEI_PLATFORM_DIMM_STATE *State
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT8 Buffer;
|
||||
|
||||
PEI_ASSERT (PeiServices, (Dimm < This->DimmSockets));
|
||||
|
||||
//
|
||||
// A failure here does not necessarily mean that no DIMM is present.
|
||||
// Read a single byte. All we care about is the return status.
|
||||
//
|
||||
Status = ReadSpd (
|
||||
PeiServices,
|
||||
This,
|
||||
Dimm,
|
||||
0,
|
||||
1,
|
||||
&Buffer
|
||||
);
|
||||
|
||||
if (EFI_ERROR (Status)) {
|
||||
State->Present = 0;
|
||||
} else {
|
||||
State->Present = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// BUGBUG: Update to check platform variable when it is available
|
||||
//
|
||||
State->Disabled = 0;
|
||||
State->Reserved = 0;
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
This function updates the state of a single DIMM.
|
||||
|
||||
@param PeiServices PEI services table pointer
|
||||
@param This PPI pointer
|
||||
@param Dimm DIMM to set state for
|
||||
@param State Pointer to the state information to set.
|
||||
|
||||
@retval EFI_SUCCESS The function completed successfully.
|
||||
@retval EFI_UNSUPPORTED The function is not supported.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SetDimmState (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_DIMM_PPI *This,
|
||||
IN UINT8 Dimm,
|
||||
IN PEI_PLATFORM_DIMM_STATE *State
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
/**
|
||||
This function reads SPD information from a DIMM.
|
||||
|
||||
PeiServices PEI services table pointer
|
||||
This PPI pointer
|
||||
Dimm DIMM to read from
|
||||
Offset Offset in DIMM
|
||||
Count Number of bytes
|
||||
Buffer Return buffer
|
||||
|
||||
@param EFI_SUCCESS The function completed successfully.
|
||||
@param EFI_DEVICE_ERROR The DIMM being accessed reported a device error,
|
||||
does not have an SPD module, or is not installed in
|
||||
the system.
|
||||
@retval EFI_TIMEOUT Time out trying to read the SPD module.
|
||||
@retval EFI_INVALID_PARAMETER A parameter was outside the legal limits.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
ReadSpd (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_DIMM_PPI *This,
|
||||
IN UINT8 Dimm,
|
||||
IN UINT8 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT UINT8 *Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
PEI_SMBUS_PPI *Smbus;
|
||||
UINTN Index;
|
||||
UINTN Index1;
|
||||
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
|
||||
EFI_SMBUS_DEVICE_COMMAND Command;
|
||||
UINTN Length;
|
||||
|
||||
Status = (**PeiServices).LocatePpi (
|
||||
PeiServices,
|
||||
&gPeiSmbusPpiGuid, // GUID
|
||||
0, // INSTANCE
|
||||
NULL, // EFI_PEI_PPI_DESCRIPTOR
|
||||
&Smbus // PPI
|
||||
);
|
||||
ASSERT_PEI_ERROR (PeiServices, Status);
|
||||
|
||||
switch (Dimm) {
|
||||
case 0:
|
||||
SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_A_1 >> 1;
|
||||
break;
|
||||
case 1:
|
||||
SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_A_2 >> 1;
|
||||
break;
|
||||
case 2:
|
||||
SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_B_1 >> 1;
|
||||
break;
|
||||
case 3:
|
||||
SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_B_2 >> 1;
|
||||
break;
|
||||
default:
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
Index = Count % 4;
|
||||
if (Index != 0) {
|
||||
//
|
||||
// read the first serveral bytes to speed up following reading
|
||||
//
|
||||
for (Index1 = 0; Index1 < Index; Index1++) {
|
||||
Length = 1;
|
||||
Command = Offset + Index1;
|
||||
Status = Smbus->Execute (
|
||||
PeiServices,
|
||||
Smbus,
|
||||
SlaveAddress,
|
||||
Command,
|
||||
EfiSmbusReadByte,
|
||||
FALSE,
|
||||
&Length,
|
||||
&Buffer[Index1]
|
||||
);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Now collect all the remaining bytes on 4 bytes block
|
||||
//
|
||||
for (; Index < Count; Index += 2) {
|
||||
Command = Index + Offset;
|
||||
Length = 2;
|
||||
Status = Smbus->Execute (
|
||||
PeiServices,
|
||||
Smbus,
|
||||
SlaveAddress,
|
||||
Command,
|
||||
EfiSmbusReadWord,
|
||||
FALSE,
|
||||
&Length,
|
||||
&Buffer[Index]
|
||||
);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Index += 2;
|
||||
Command = Index + Offset;
|
||||
Length = 2;
|
||||
Status = Smbus->Execute (
|
||||
PeiServices,
|
||||
Smbus,
|
||||
SlaveAddress,
|
||||
Command,
|
||||
EfiSmbusReadWord,
|
||||
FALSE,
|
||||
&Length,
|
||||
&Buffer[Index]
|
||||
);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
}
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
This function initializes the PEIM. It simply installs the DIMM PPI.
|
||||
|
||||
@param FfsHeader Not used by this function
|
||||
@param PeiServices Pointer to PEI services table
|
||||
|
||||
@retval EFI_SUCCESS The function completed successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PeimInitializeDimm (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
|
||||
IN VOID *SmbusPpi
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
148
Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c
Normal file
148
Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c
Normal file
@@ -0,0 +1,148 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
FlashMap.c
|
||||
|
||||
Abstract:
|
||||
|
||||
Build GUIDed HOBs for platform specific flash map.
|
||||
|
||||
--*/
|
||||
|
||||
#include "Efi.h"
|
||||
#include "Pei.h"
|
||||
#include "PeiLib.h"
|
||||
#include "PeiLib.h"
|
||||
#include "EfiFlashMap.h"
|
||||
#include EFI_PROTOCOL_CONSUMER (FirmwareVolumeBlock)
|
||||
#include EFI_GUID_DEFINITION (FlashMapHob)
|
||||
#include EFI_GUID_DEFINITION (SystemNvDataGuid)
|
||||
#include EFI_GUID_DEFINITION (FirmwareFileSystem)
|
||||
|
||||
EFI_GUID mFvBlockGuid = EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID;
|
||||
EFI_GUID mFfsGuid = EFI_FIRMWARE_FILE_SYSTEM_GUID;
|
||||
EFI_GUID mSystemDataGuid = EFI_SYSTEM_NV_DATA_HOB_GUID;
|
||||
|
||||
static EFI_FLASH_AREA_DATA mFlashAreaData[] = {
|
||||
//
|
||||
// Variable area
|
||||
//
|
||||
{ FixedPcdGet32 (PcdFlashNvStorageVariableBase),
|
||||
FixedPcdGet32 (PcdFlashNvStorageVariableSize),
|
||||
EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV,
|
||||
EFI_FLASH_AREA_EFI_VARIABLES },
|
||||
|
||||
//
|
||||
// Boot block 2nd part
|
||||
//
|
||||
{ FixedPcdGet32 (PcdFlashFvRecovery2Base),
|
||||
FixedPcdGet32 (PcdFlashFvRecovery2Size),
|
||||
EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV,
|
||||
EFI_FLASH_AREA_FTW_BACKUP },
|
||||
|
||||
//
|
||||
// Recovery FV
|
||||
//
|
||||
{ FixedPcdGet32 (PcdFlashFvRecoveryBase),
|
||||
FixedPcdGet32 (PcdFlashFvRecoverySize),
|
||||
EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV,
|
||||
EFI_FLASH_AREA_RECOVERY_BIOS },
|
||||
|
||||
//
|
||||
// Main FV
|
||||
//
|
||||
{ FixedPcdGet32 (PcdFlashFvMainBase),
|
||||
FixedPcdGet32 (PcdFlashFvMainSize),
|
||||
EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV,
|
||||
EFI_FLASH_AREA_MAIN_BIOS }
|
||||
|
||||
};
|
||||
|
||||
#define NUM_FLASH_AREA_DATA (sizeof (mFlashAreaData) / sizeof (mFlashAreaData[0]))
|
||||
|
||||
/**
|
||||
Build GUID HOBs for platform specific flash map.
|
||||
|
||||
@param FfsHeader Pointer this FFS file header.
|
||||
@param PeiServices General purpose services available to every PEIM.
|
||||
|
||||
@retval EFI_SUCCESS Guid HOBs for platform flash map is built.
|
||||
@retval Otherwise Failed to build the Guid HOB data.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
PeimInitializeFlashMap (
|
||||
IN EFI_FFS_FILE_HEADER *FfsHeader,
|
||||
IN EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
UINTN Index;
|
||||
EFI_FLASH_AREA_HOB_DATA FlashHobData;
|
||||
|
||||
//
|
||||
// Build flash area entries as GUIDed HOBs.
|
||||
//
|
||||
for (Index = 0; Index < NUM_FLASH_AREA_DATA; Index++) {
|
||||
ZeroMem(&FlashHobData, sizeof (EFI_FLASH_AREA_HOB_DATA));
|
||||
|
||||
FlashHobData.AreaType = mFlashAreaData[Index].AreaType;
|
||||
FlashHobData.NumberOfEntries = 1;
|
||||
FlashHobData.SubAreaData.Attributes = mFlashAreaData[Index].Attributes;
|
||||
FlashHobData.SubAreaData.Base = (EFI_PHYSICAL_ADDRESS) (UINTN) mFlashAreaData[Index].Base;
|
||||
FlashHobData.SubAreaData.Length = (EFI_PHYSICAL_ADDRESS) (UINTN) mFlashAreaData[Index].Length;
|
||||
|
||||
switch (FlashHobData.AreaType) {
|
||||
case EFI_FLASH_AREA_RECOVERY_BIOS:
|
||||
case EFI_FLASH_AREA_MAIN_BIOS:
|
||||
CopyMem (
|
||||
&FlashHobData.AreaTypeGuid,
|
||||
&mFfsGuid,
|
||||
sizeof (EFI_GUID)
|
||||
);
|
||||
CopyMem (
|
||||
&FlashHobData.SubAreaData.FileSystem,
|
||||
&mFvBlockGuid,
|
||||
sizeof (EFI_GUID)
|
||||
);
|
||||
break;
|
||||
|
||||
case EFI_FLASH_AREA_GUID_DEFINED:
|
||||
CopyMem (
|
||||
&FlashHobData.AreaTypeGuid,
|
||||
&mSystemDataGuid,
|
||||
sizeof (EFI_GUID)
|
||||
);
|
||||
CopyMem (
|
||||
&FlashHobData.SubAreaData.FileSystem,
|
||||
&mFvBlockGuid,
|
||||
sizeof (EFI_GUID)
|
||||
);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
173
Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c
Normal file
173
Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c
Normal file
@@ -0,0 +1,173 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
|
||||
LegacySpeaker.c
|
||||
|
||||
Abstract:
|
||||
|
||||
This file implements PEIM for Legacy Speaker. This file is valid for platforms both
|
||||
on IA32 and Itanium Product Family
|
||||
|
||||
--*/
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
EFI_STATUS
|
||||
OutputBeep (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN UINTN NumberOfBeep,
|
||||
IN UINTN BeepDuration,
|
||||
IN UINTN TimerInterval
|
||||
);
|
||||
|
||||
/**
|
||||
This function will enable the speaker to generate beep
|
||||
|
||||
@param PeiServices PeiServices to locate PPI
|
||||
|
||||
@retval EFI_STATUS
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
TurnOnSpeaker (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
UINT8 Data;
|
||||
Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);
|
||||
Data |= 0x03;
|
||||
IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
This function will stop beep from speaker.
|
||||
|
||||
@param PeiServices PeiServices to locate PPI
|
||||
|
||||
@retval Status
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
TurnOffSpeaker (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
UINT8 Data;
|
||||
|
||||
Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);
|
||||
Data &= 0xFC;
|
||||
IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
OutputBeep (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN UINTN NumberOfBeep,
|
||||
IN UINTN BeepDuration,
|
||||
IN UINTN TimeInterval
|
||||
)
|
||||
{
|
||||
UINTN Num;
|
||||
EFI_PEI_STALL_PPI* StallPpi;
|
||||
|
||||
(**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0, NULL, (void **)&StallPpi);
|
||||
|
||||
for (Num=0; Num < NumberOfBeep; Num++) {
|
||||
TurnOnSpeaker (PeiServices);
|
||||
StallPpi->Stall(PeiServices, StallPpi, BeepDuration);
|
||||
TurnOffSpeaker(PeiServices);
|
||||
StallPpi->Stall(PeiServices, StallPpi, TimeInterval);
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
This function will program the speaker tone frequency. The value should be with 64k
|
||||
boundary since it takes only 16 bit value which gets programmed in two step IO opearattion
|
||||
|
||||
Frequency - A value which should be 16 bit only.
|
||||
|
||||
EFI_SUCESS
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
ProgramToneFrequency (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN UINT16 Frequency
|
||||
)
|
||||
{
|
||||
UINT8 Data;
|
||||
|
||||
Data = 0xB6;
|
||||
IoWrite8(EFI_TIMER_CONTROL_PORT, Data);
|
||||
|
||||
Data = (UINT8)(Frequency & 0x00FF);
|
||||
IoWrite8(EFI_TIMER_2_PORT, Data);
|
||||
Data = (UINT8)((Frequency & 0xFF00) >> 8);
|
||||
IoWrite8(EFI_TIMER_2_PORT, Data);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
This function will generate the beep for specified duration.
|
||||
|
||||
@param PeiServices PeiServices to locate various PPIs
|
||||
@param NumberOfBeeps Number of beeps which user want to produce
|
||||
@param BeepDuration Duration for speaker gate need to be enabled
|
||||
@param TimeInterval Interval between each beep
|
||||
|
||||
@retval EFI_STATUS
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
GenerateBeepTone (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN UINTN NumberOfBeeps,
|
||||
IN UINTN BeepDuration,
|
||||
IN UINTN TimeInterval
|
||||
)
|
||||
{
|
||||
|
||||
if ((NumberOfBeeps == 1) && (BeepDuration == 0) && (TimeInterval == 0)) {
|
||||
TurnOnSpeaker (PeiServices);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
if ((NumberOfBeeps == 0) && (BeepDuration == 0) && (TimeInterval == 0)) {
|
||||
TurnOffSpeaker (PeiServices);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
if (BeepDuration == 0) {
|
||||
BeepDuration = EFI_DEFAULT_SHORT_BEEP_DURATION;
|
||||
}
|
||||
|
||||
if (TimeInterval == 0) {
|
||||
76
Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h
Normal file
76
Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
LegacySpeaker.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Speaker enabling related data
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PEI_LEGACY_SPEAKER_H
|
||||
#define _PEI_LEGACY_SPEAKER_H
|
||||
|
||||
|
||||
//
|
||||
// Speaker Related Port Information
|
||||
//
|
||||
#define EFI_TIMER_COUNTER_PORT 0x40
|
||||
#define EFI_TIMER_CONTROL_PORT 0x43
|
||||
#define EFI_TIMER_2_PORT 0x42
|
||||
#define EFI_SPEAKER_CONTROL_PORT 0x61
|
||||
|
||||
#define EFI_SPEAKER_OFF_MASK 0xFC
|
||||
|
||||
#define EFI_DEFAULT_BEEP_FREQUENCY 0x500
|
||||
|
||||
//
|
||||
// Default Intervals/Beep Duration
|
||||
//
|
||||
#define EFI_DEFAULT_LONG_BEEP_DURATION 0x70000
|
||||
#define EFI_DEFAULT_SHORT_BEEP_DURATION 0x50000
|
||||
#define EFI_DEFAULT_BEEP_TIME_INTERVAL 0x20000
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
ProgramToneFrequency (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN UINT16 Frequency
|
||||
);
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
GenerateBeepTone (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN UINTN NumberOfBeeps,
|
||||
IN UINTN BeepDuration,
|
||||
IN UINTN TimeInterval
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
TurnOnSpeaker (
|
||||
77
Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c
Normal file
77
Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c
Normal file
@@ -0,0 +1,77 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
|
||||
MchInit.c
|
||||
|
||||
Abstract:
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
#define PSE_PAGE_SIZE 0x400000 // 4MB
|
||||
|
||||
extern BOOLEAN ImageInMemory;
|
||||
|
||||
|
||||
VOID
|
||||
EfiCommonLibEnablePsePaging (
|
||||
IN UINT32 PDBR
|
||||
);
|
||||
|
||||
VOID
|
||||
EfiCommonLibDisablePsePaging (
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
Initialize the MCH Thermal Sensor
|
||||
|
||||
**/
|
||||
VOID
|
||||
InitMchThermalSensor()
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
Programs and enables the CRID for MCH and ICH
|
||||
|
||||
**/
|
||||
VOID
|
||||
ProgramMchCRID(
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers
|
||||
|
||||
**/
|
||||
VOID
|
||||
345
Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c
Normal file
345
Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c
Normal file
@@ -0,0 +1,345 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
MemoryCallback.c
|
||||
|
||||
Abstract:
|
||||
|
||||
EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.
|
||||
|
||||
--*/
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
|
||||
VOID
|
||||
UpdateDefaultSetupValue (
|
||||
IN EFI_PLATFORM_INFO_HOB *PlatformInfo
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
PEI termination callback.
|
||||
|
||||
@param PeiServices General purpose services available to every PEIM.
|
||||
@param NotifyDescriptor Not uesed.
|
||||
@param Ppi Not uesed.
|
||||
|
||||
@retval EFI_SUCCESS If the interface could be successfully
|
||||
installed.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
EndOfPeiPpiNotifyCallback (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
|
||||
IN VOID *Ppi
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT64 MemoryTop;
|
||||
UINT64 LowUncableBase;
|
||||
EFI_PLATFORM_INFO_HOB *PlatformInfo;
|
||||
UINT32 HecBaseHigh;
|
||||
EFI_BOOT_MODE BootMode;
|
||||
EFI_PEI_HOB_POINTERS Hob;
|
||||
|
||||
Status = (*PeiServices)->GetBootMode(
|
||||
PeiServices,
|
||||
&BootMode
|
||||
);
|
||||
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
//
|
||||
// Set the some PCI and chipset range as UC
|
||||
// And align to 1M at leaset
|
||||
//
|
||||
Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
|
||||
ASSERT (Hob.Raw != NULL);
|
||||
PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
|
||||
|
||||
UpdateDefaultSetupValue (PlatformInfo);
|
||||
|
||||
DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));
|
||||
DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));
|
||||
DEBUG (
|
||||
(EFI_D_ERROR,
|
||||
"PCIE BASE: %lX Size : %X\n",
|
||||
PlatformInfo->PciData.PciExpressBase,
|
||||
PlatformInfo->PciData.PciExpressSize)
|
||||
);
|
||||
DEBUG (
|
||||
(EFI_D_ERROR,
|
||||
"PCI32 BASE: %X Limit: %X\n",
|
||||
PlatformInfo->PciData.PciResourceMem32Base,
|
||||
PlatformInfo->PciData.PciResourceMem32Limit)
|
||||
);
|
||||
DEBUG (
|
||||
(EFI_D_ERROR,
|
||||
"PCI64 BASE: %lX Limit: %lX\n",
|
||||
PlatformInfo->PciData.PciResourceMem64Base,
|
||||
PlatformInfo->PciData.PciResourceMem64Limit)
|
||||
);
|
||||
DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));
|
||||
|
||||
LowUncableBase = PlatformInfo->MemData.MemMaxTolm;
|
||||
LowUncableBase &= (0x0FFF00000);
|
||||
MemoryTop = (0x100000000);
|
||||
|
||||
if (BootMode != BOOT_ON_S3_RESUME) {
|
||||
//
|
||||
// In BIOS, HECBASE will be always below 4GB
|
||||
//
|
||||
HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);
|
||||
ASSERT (HecBaseHigh < 16);
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
Install Firmware Volume Hob's once there is main memory
|
||||
|
||||
@param PeiServices General purpose services available to every PEIM.
|
||||
@param NotifyDescriptor Notify that this module published.
|
||||
@param Ppi PPI that was installed.
|
||||
|
||||
@retval EFI_SUCCESS The function completed successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
MemoryDiscoveredPpiNotifyCallback (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
|
||||
IN VOID *Ppi
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_BOOT_MODE BootMode;
|
||||
EFI_CPUID_REGISTER FeatureInfo;
|
||||
UINT8 CpuAddressWidth;
|
||||
UINT16 Pm1Cnt;
|
||||
EFI_PEI_HOB_POINTERS Hob;
|
||||
EFI_PLATFORM_INFO_HOB *PlatformInfo;
|
||||
UINT32 RootComplexBar;
|
||||
UINT32 PmcBase;
|
||||
UINT32 IoBase;
|
||||
UINT32 IlbBase;
|
||||
UINT32 SpiBase;
|
||||
UINT32 MphyBase;
|
||||
|
||||
//
|
||||
// Get Platform Info HOB
|
||||
//
|
||||
Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
|
||||
ASSERT (Hob.Raw != NULL);
|
||||
PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
|
||||
|
||||
Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
|
||||
|
||||
//
|
||||
// Check if user wants to turn off in PEI phase
|
||||
//
|
||||
if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
|
||||
CheckPowerOffNow();
|
||||
} else {
|
||||
Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
|
||||
Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
|
||||
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
|
||||
}
|
||||
|
||||
#ifndef MINNOW2_FSP_BUILD
|
||||
//
|
||||
// Set PEI cache mode here
|
||||
//
|
||||
SetPeiCacheMode (PeiServices);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Pulish memory tyoe info
|
||||
//
|
||||
PublishMemoryTypeInfo ();
|
||||
|
||||
//
|
||||
// Work done if on a S3 resume
|
||||
//
|
||||
if (BootMode == BOOT_ON_S3_RESUME) {
|
||||
//
|
||||
//Program the side band packet register to send a sideband message to Punit
|
||||
//To indicate that DRAM has been initialized and PUNIT FW base address in memory.
|
||||
//
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
RootComplexBar,
|
||||
0x1000
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar));
|
||||
|
||||
PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
PmcBase,
|
||||
0x1000
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase));
|
||||
|
||||
IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
IoBase,
|
||||
0x4000
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));
|
||||
|
||||
IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
IlbBase,
|
||||
0x1000
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase));
|
||||
|
||||
SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
SpiBase,
|
||||
0x1000
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase));
|
||||
|
||||
MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
MphyBase,
|
||||
0x100000
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase));
|
||||
|
||||
//
|
||||
// Local APIC
|
||||
//
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
LOCAL_APIC_ADDRESS,
|
||||
0x1000
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));
|
||||
|
||||
//
|
||||
// IO APIC
|
||||
//
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
IO_APIC_ADDRESS,
|
||||
0x1000
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS));
|
||||
|
||||
//
|
||||
// Adding the PCIE Express area to the E820 memory table as type 2 memory.
|
||||
//
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
PlatformInfo->PciData.PciExpressBase,
|
||||
PlatformInfo->PciData.PciExpressSize
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "PciExpressBase : 0x%x\n", PlatformInfo->PciData.PciExpressBase));
|
||||
|
||||
//
|
||||
// Adding the Flashpart to the E820 memory table as type 2 memory.
|
||||
//
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_FIRMWARE_DEVICE,
|
||||
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
|
||||
FixedPcdGet32 (PcdFlashAreaBaseAddress),
|
||||
FixedPcdGet32 (PcdFlashAreaSize)
|
||||
);
|
||||
DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));
|
||||
|
||||
//
|
||||
// Create a CPU hand-off information
|
||||
//
|
||||
CpuAddressWidth = 32;
|
||||
AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
|
||||
if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {
|
||||
AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
|
||||
CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);
|
||||
}
|
||||
|
||||
BuildCpuHob(CpuAddressWidth, 16);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
return Status;
|
||||
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
ValidateFvHeader (
|
||||
IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader
|
||||
)
|
||||
{
|
||||
UINT16 *Ptr;
|
||||
UINT16 HeaderLength;
|
||||
UINT16 Checksum;
|
||||
|
||||
//
|
||||
// Verify the header revision, header signature, length
|
||||
// Length of FvBlock cannot be 2**64-1
|
||||
// HeaderLength cannot be an odd number
|
||||
//
|
||||
if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||
|
||||
(FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
|
||||
(FwVolHeader->FvLength == ((UINT64) -1)) ||
|
||||
((FwVolHeader->HeaderLength & 0x01) != 0)
|
||||
) {
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
|
||||
//
|
||||
// Verify the header checksum
|
||||
//
|
||||
HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);
|
||||
Ptr = (UINT16 *) FwVolHeader;
|
||||
Checksum = 0;
|
||||
while (HeaderLength > 0) {
|
||||
Checksum = *Ptr++;
|
||||
369
Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c
Normal file
369
Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c
Normal file
@@ -0,0 +1,369 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
|
||||
MemoryPeim.c
|
||||
|
||||
Abstract:
|
||||
|
||||
Tiano PEIM to provide the platform support functionality.
|
||||
This file implements the Platform Memory Range PPI
|
||||
|
||||
--*/
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
//
|
||||
// Need min. of 48MB PEI phase
|
||||
//
|
||||
#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)
|
||||
#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)
|
||||
|
||||
//
|
||||
// This is the memory needed for PEI to start up DXE.
|
||||
//
|
||||
// Over-estimating this size will lead to higher fragmentation
|
||||
// of main memory. Under-estimation of this will cause catastrophic
|
||||
// failure of PEI to load DXE. Generally, the failure may only be
|
||||
// realized during capsule updates.
|
||||
//
|
||||
#define PRERESERVED_PEI_MEMORY ( \
|
||||
EFI_SIZE_TO_PAGES (3 * 0x800000) /* PEI Core memory based stack */ \
|
||||
)
|
||||
|
||||
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
|
||||
{ EfiACPIReclaimMemory, 0x40 }, // 0x40 pages = 256k for ASL
|
||||
{ EfiACPIMemoryNVS, 0x100 }, // 0x100 pages = 1 MB for S3, SMM, HII, etc
|
||||
{ EfiReservedMemoryType, 0x600 }, // 48k for BIOS Reserved
|
||||
{ EfiMemoryMappedIO, 0 },
|
||||
{ EfiMemoryMappedIOPortSpace, 0 },
|
||||
{ EfiPalCode, 0 },
|
||||
{ EfiRuntimeServicesCode, 0x200 },
|
||||
{ EfiRuntimeServicesData, 0x100 },
|
||||
{ EfiLoaderCode, 0x100 },
|
||||
{ EfiLoaderData, 0x100 },
|
||||
{ EfiBootServicesCode, 0x800 },
|
||||
{ EfiBootServicesData, 0x2500},
|
||||
{ EfiConventionalMemory, 0 },
|
||||
{ EfiUnusableMemory, 0 },
|
||||
{ EfiMaxMemoryType, 0 }
|
||||
};
|
||||
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
GetMemorySize (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
OUT UINT64 *LowMemoryLength,
|
||||
OUT UINT64 *HighMemoryLength
|
||||
);
|
||||
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SetPeiCacheMode (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
PEI_CACHE_PPI *CachePpi;
|
||||
|
||||
EFI_BOOT_MODE BootMode;
|
||||
UINT64 MemoryLength;
|
||||
UINT64 MemOverflow;
|
||||
UINT64 MemoryLengthUc;
|
||||
UINT64 MaxMemoryLength;
|
||||
UINT64 LowMemoryLength;
|
||||
UINT64 HighMemoryLength;
|
||||
UINT8 Index;
|
||||
MTRR_SETTINGS MtrrSetting;
|
||||
|
||||
//
|
||||
// Load Cache PPI
|
||||
//
|
||||
Status = (**PeiServices).LocatePpi (
|
||||
PeiServices,
|
||||
&gPeiCachePpiGuid, // GUID
|
||||
0, // Instance
|
||||
NULL, // EFI_PEI_PPI_DESCRIPTOR
|
||||
(void **)&CachePpi // PPI
|
||||
);
|
||||
if (!EFI_ERROR(Status)) {
|
||||
//
|
||||
// Clear the CAR Settings (Default Cache Type => UC)
|
||||
//
|
||||
DEBUG ((EFI_D_INFO, "Reset cache attribute and disable CAR. \n"));
|
||||
CachePpi->ResetCache(
|
||||
(EFI_PEI_SERVICES**)PeiServices,
|
||||
CachePpi
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Variable initialization
|
||||
//
|
||||
LowMemoryLength = 0;
|
||||
HighMemoryLength = 0;
|
||||
MemoryLengthUc = 0;
|
||||
|
||||
Status = (*PeiServices)->GetBootMode (
|
||||
PeiServices,
|
||||
&BootMode
|
||||
);
|
||||
|
||||
//
|
||||
// Determine memory usage
|
||||
//
|
||||
GetMemorySize (
|
||||
PeiServices,
|
||||
&LowMemoryLength,
|
||||
&HighMemoryLength
|
||||
);
|
||||
|
||||
LowMemoryLength = (EFI_PHYSICAL_ADDRESS)MmPci32( 0, 0, 2, 0, 0x70);
|
||||
LowMemoryLength &= 0xFFF00000ULL;
|
||||
|
||||
MaxMemoryLength = LowMemoryLength;
|
||||
|
||||
//
|
||||
// Round up to nearest 256MB with high memory and 64MB w/o high memory
|
||||
//
|
||||
if (HighMemoryLength != 0 ) {
|
||||
MemOverflow = (LowMemoryLength & 0x0fffffff);
|
||||
if (MemOverflow != 0) {
|
||||
MaxMemoryLength = LowMemoryLength + (0x10000000 - MemOverflow);
|
||||
}
|
||||
} else {
|
||||
MemOverflow = (LowMemoryLength & 0x03ffffff);
|
||||
if (MemOverflow != 0) {
|
||||
MaxMemoryLength = LowMemoryLength + (0x4000000 - MemOverflow);
|
||||
}
|
||||
}
|
||||
|
||||
ZeroMem (&MtrrSetting, sizeof(MTRR_SETTINGS));
|
||||
for (Index = 0; Index < 2; Index++) {
|
||||
MtrrSetting.Fixed.Mtrr[Index]=0x0606060606060606;
|
||||
}
|
||||
for (Index = 2; Index < 11; Index++) {
|
||||
MtrrSetting.Fixed.Mtrr[Index]=0x0505050505050505;
|
||||
}
|
||||
|
||||
//
|
||||
// Cache the flash area to improve the boot performance in PEI phase
|
||||
//
|
||||
Index = 0;
|
||||
MtrrSetting.Variables.Mtrr[0].Base = (FixedPcdGet32 (PcdFlashAreaBaseAddress) | CacheWriteProtected);
|
||||
MtrrSetting.Variables.Mtrr[0].Mask = ((~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
|
||||
Index ++;
|
||||
|
||||
MemOverflow =0;
|
||||
while (MaxMemoryLength > MemOverflow){
|
||||
MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack;
|
||||
MemoryLength = MaxMemoryLength - MemOverflow;
|
||||
MemoryLength = GetPowerOfTwo64 (MemoryLength);
|
||||
MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
|
||||
|
||||
MemOverflow += MemoryLength;
|
||||
Index++;
|
||||
}
|
||||
|
||||
MemoryLength = LowMemoryLength;
|
||||
|
||||
while (MaxMemoryLength != MemoryLength) {
|
||||
MemoryLengthUc = GetPowerOfTwo64 (MaxMemoryLength - MemoryLength);
|
||||
|
||||
MtrrSetting.Variables.Mtrr[Index].Base = ((MaxMemoryLength - MemoryLengthUc) & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheUncacheable;
|
||||
MtrrSetting.Variables.Mtrr[Index].Mask= ((~(MemoryLengthUc - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
|
||||
MaxMemoryLength -= MemoryLengthUc;
|
||||
Index++;
|
||||
}
|
||||
|
||||
MemOverflow =0x100000000;
|
||||
while (HighMemoryLength > 0) {
|
||||
MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack;
|
||||
MemoryLength = HighMemoryLength;
|
||||
MemoryLength = GetPowerOfTwo64 (MemoryLength);
|
||||
|
||||
if (MemoryLength > MemOverflow){
|
||||
MemoryLength = MemOverflow;
|
||||
}
|
||||
|
||||
MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
|
||||
|
||||
MemOverflow += MemoryLength;
|
||||
HighMemoryLength -= MemoryLength;
|
||||
Index++;
|
||||
}
|
||||
|
||||
|
||||
for (Index = 0; Index < MTRR_NUMBER_OF_VARIABLE_MTRR; Index++) {
|
||||
if (MtrrSetting.Variables.Mtrr[Index].Base == 0){
|
||||
break;
|
||||
}
|
||||
DEBUG ((EFI_D_INFO, "Base=%lx, Mask=%lx\n",MtrrSetting.Variables.Mtrr[Index].Base ,MtrrSetting.Variables.Mtrr[Index].Mask));
|
||||
}
|
||||
|
||||
//
|
||||
// set FE/E bits for IA32_MTRR_DEF_TYPE
|
||||
//
|
||||
MtrrSetting.MtrrDefType |= 3 <<10;
|
||||
|
||||
MtrrSetAllMtrrs(&MtrrSetting);
|
||||
|
||||
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SetDxeCacheMode (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
//
|
||||
// This is not needed for now.
|
||||
//
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
GetMemorySize (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
OUT UINT64 *LowMemoryLength,
|
||||
OUT UINT64 *HighMemoryLength
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PEI_HOB_POINTERS Hob;
|
||||
|
||||
*HighMemoryLength = 0;
|
||||
*LowMemoryLength = 0x100000;
|
||||
|
||||
//
|
||||
// Get the HOB list for processing
|
||||
//
|
||||
Status = (*PeiServices)->GetHobList (PeiServices, (void **)&Hob.Raw);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Collect memory ranges
|
||||
//
|
||||
while (!END_OF_HOB_LIST (Hob)) {
|
||||
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
|
||||
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
|
||||
//
|
||||
// Need memory above 1MB to be collected here
|
||||
//
|
||||
if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 &&
|
||||
Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) {
|
||||
*LowMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);
|
||||
} else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) {
|
||||
*HighMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);
|
||||
}
|
||||
}
|
||||
}
|
||||
Hob.Raw = GET_NEXT_HOB (Hob);
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Publish Memory Type Information.
|
||||
|
||||
@param NULL
|
||||
|
||||
@retval EFI_SUCCESS Success.
|
||||
@retval Others Errors have occurred.
|
||||
**/
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PublishMemoryTypeInfo (
|
||||
void
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
|
||||
UINTN DataSize;
|
||||
EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
|
||||
|
||||
Status = PeiServicesLocatePpi (
|
||||
&gEfiPeiReadOnlyVariable2PpiGuid,
|
||||
0,
|
||||
NULL,
|
||||
(void **)&Variable
|
||||
);
|
||||
if (EFI_ERROR(Status)) {
|
||||
DEBUG((EFI_D_ERROR, "WARNING: Locating Pei variable failed 0x%x \n", Status));
|
||||
DEBUG((EFI_D_ERROR, "Build Hob from default\n"));
|
||||
//
|
||||
// Build the default GUID'd HOB for DXE
|
||||
//
|
||||
BuildGuidDataHob (
|
||||
&gEfiMemoryTypeInformationGuid,
|
||||
mDefaultMemoryTypeInformation,
|
||||
sizeof (mDefaultMemoryTypeInformation)
|
||||
);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
DataSize = sizeof (MemoryData);
|
||||
|
||||
//
|
||||
// This variable is saved in BDS stage. Now read it back
|
||||
//
|
||||
Status = Variable->GetVariable (
|
||||
Variable,
|
||||
EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
|
||||
&gEfiMemoryTypeInformationGuid,
|
||||
NULL,
|
||||
&DataSize,
|
||||
&MemoryData
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
//
|
||||
//build default
|
||||
//
|
||||
DEBUG((EFI_D_ERROR, "Build Hob from default\n"));
|
||||
BuildGuidDataHob (
|
||||
&gEfiMemoryTypeInformationGuid,
|
||||
mDefaultMemoryTypeInformation,
|
||||
sizeof (mDefaultMemoryTypeInformation)
|
||||
);
|
||||
|
||||
} else {
|
||||
//
|
||||
// Build the GUID'd HOB for DXE from variable
|
||||
//
|
||||
DEBUG((EFI_D_ERROR, "Build Hob from variable \n"));
|
||||
BuildGuidDataHob (
|
||||
813
Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
Normal file
813
Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
Normal file
@@ -0,0 +1,813 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PchInitPeim.c
|
||||
|
||||
Abstract:
|
||||
|
||||
Do Early PCH platform initialization.
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
#include "Ppi/PchPlatformPolicy.h"
|
||||
#include "PchRegs.h"
|
||||
#include <Ppi/PchUsbPolicy.h>
|
||||
#include "Ppi/PchInit.h"
|
||||
#include <Library/PcdLib.h>
|
||||
|
||||
EFI_GUID gPchPlatformPolicyPpiGuid = PCH_PLATFORM_POLICY_PPI_GUID;
|
||||
|
||||
#define MC_PMSTS_OFFSET 0xC
|
||||
|
||||
#define DEFAULT_BUS_INFO 0x2020
|
||||
|
||||
|
||||
#define PCI_LPC_BASE (0x8000F800)
|
||||
#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
|
||||
#define PCIEX_BASE_ADDRESS 0xE0000000
|
||||
#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
|
||||
|
||||
VOID
|
||||
PchPolicySetupInit (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
);
|
||||
|
||||
VOID
|
||||
PchInitInterrupt (
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
);
|
||||
|
||||
#ifndef __GNUC__
|
||||
#pragma warning (push)
|
||||
#pragma warning (disable : 4245)
|
||||
#pragma warning (pop)
|
||||
#endif
|
||||
|
||||
UINT8
|
||||
ReadCmosBank1Byte (
|
||||
IN UINT8 Address
|
||||
)
|
||||
{
|
||||
UINT8 Data;
|
||||
|
||||
IoWrite8(R_PCH_RTC_EXT_INDEX, Address);
|
||||
Data = IoRead8 (R_PCH_RTC_EXT_TARGET);
|
||||
return Data;
|
||||
}
|
||||
|
||||
VOID
|
||||
WriteCmosBank1Byte (
|
||||
IN UINT8 Address,
|
||||
IN UINT8 Data
|
||||
)
|
||||
{
|
||||
IoWrite8(R_PCH_RTC_EXT_INDEX, Address);
|
||||
IoWrite8(R_PCH_RTC_EXT_TARGET, Data);
|
||||
}
|
||||
|
||||
/**
|
||||
Turn off system if needed.
|
||||
|
||||
@param PeiServices Pointer to PEI Services
|
||||
@param CpuIo Pointer to CPU I/O Protocol
|
||||
|
||||
@retval None.
|
||||
|
||||
**/
|
||||
VOID
|
||||
CheckPowerOffNow (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT16 Pm1Sts;
|
||||
|
||||
//
|
||||
// Read and check the ACPI registers
|
||||
//
|
||||
Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
|
||||
if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) {
|
||||
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);
|
||||
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);
|
||||
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN);
|
||||
|
||||
//
|
||||
// Should not return
|
||||
//
|
||||
CpuDeadLoop();
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
ClearPowerState (
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
)
|
||||
{
|
||||
UINT8 Data8;
|
||||
UINT16 Data16;
|
||||
UINT32 Data32;
|
||||
|
||||
//
|
||||
// Check for PowerState option for AC power loss and program the chipset
|
||||
//
|
||||
|
||||
//
|
||||
// Clear PWROK (Set to Clear)
|
||||
//
|
||||
MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_PWROK_FLR);
|
||||
|
||||
//
|
||||
// Clear Power Failure Bit (Set to Clear)
|
||||
//
|
||||
// TODO: Check if it is OK to clear here
|
||||
//
|
||||
|
||||
MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR);
|
||||
|
||||
//
|
||||
// Clear the GPE and PM enable
|
||||
//
|
||||
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_EN, (UINT16) 0x00);
|
||||
IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_EN, (UINT32) 0x00);
|
||||
|
||||
//
|
||||
// Halt the TCO timer
|
||||
//
|
||||
Data16 = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT);
|
||||
Data16 |= B_PCH_TCO_CNT_TMR_HLT;
|
||||
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT, Data16);
|
||||
|
||||
//
|
||||
// if NMI_NOW_STS is set
|
||||
// NMI NOW bit is "Write '1' to clear"
|
||||
//
|
||||
Data8 = MmioRead8(ILB_BASE_ADDRESS + R_PCH_ILB_GNMI);
|
||||
if ((Data8 & B_PCH_ILB_GNMI_NMINS) == B_PCH_ILB_GNMI_NMINS) {
|
||||
MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_GNMI, B_PCH_ILB_GNMI_NMIN);
|
||||
}
|
||||
|
||||
//
|
||||
// Before we clear the TO status bit here we need to save the results in a CMOS bit for later use.
|
||||
//
|
||||
Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS);
|
||||
if ((Data32 & B_PCH_TCO_STS_SECOND_TO) == B_PCH_TCO_STS_SECOND_TO)
|
||||
{
|
||||
#if (defined(HW_WATCHDOG_TIMER_SUPPORT) && (HW_WATCHDOG_TIMER_SUPPORT != 0))
|
||||
WriteCmosBank1Byte (
|
||||
EFI_CMOS_PERFORMANCE_FLAGS,
|
||||
ReadCmosBank1Byte (EFI_CMOS_PERFORMANCE_FLAGS) | B_CMOS_TCO_WDT_RESET
|
||||
);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/*++
|
||||
|
||||
Clear any SMI status or wake status left over from boot.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ClearSmiAndWake (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT16 Pm1Sts;
|
||||
UINT32 Gpe0Sts;
|
||||
UINT32 SmiSts;
|
||||
|
||||
//
|
||||
// Read the ACPI registers
|
||||
//
|
||||
Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
|
||||
Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
|
||||
SmiSts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS);
|
||||
|
||||
//
|
||||
// Register Wake up reason for S4. This information is used to notify
|
||||
// WinXp of wake up reason because S4 wake up path doesn't keep SCI.
|
||||
// This is important for Viiv(Quick resume) platform.
|
||||
//
|
||||
|
||||
//
|
||||
// First Clear CMOS S4 Wake up flag.
|
||||
//
|
||||
WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 0);
|
||||
|
||||
//
|
||||
// Check wake up reason and set CMOS accordingly. Currently checks
|
||||
// Power button, USB, PS/2.
|
||||
// Note : PS/2 wake up is using GPI13 (IO_PME). This must be changed depending
|
||||
// on board design.
|
||||
//
|
||||
if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) || (Gpe0Sts & (B_PCH_ACPI_GPE0a_STS_CORE_GPIO | B_PCH_ACPI_GPE0a_STS_SUS_GPIO))) {
|
||||
WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 1);
|
||||
}
|
||||
|
||||
//
|
||||
// Clear any SMI or wake state from the boot
|
||||
//
|
||||
Pm1Sts = (B_PCH_ACPI_PM1_STS_PRBTNOR | B_PCH_ACPI_PM1_STS_PWRBTN);
|
||||
|
||||
Gpe0Sts |=
|
||||
(
|
||||
B_PCH_ACPI_GPE0a_STS_CORE_GPIO |
|
||||
B_PCH_ACPI_GPE0a_STS_SUS_GPIO |
|
||||
B_PCH_ACPI_GPE0a_STS_PME_B0 |
|
||||
B_PCH_ACPI_GPE0a_STS_BATLOW |
|
||||
B_PCH_ACPI_GPE0a_STS_PCI_EXP |
|
||||
B_PCH_ACPI_GPE0a_STS_GUNIT_SCI |
|
||||
B_PCH_ACPI_GPE0a_STS_PUNIT_SCI |
|
||||
B_PCH_ACPI_GPE0a_STS_SWGPE |
|
||||
B_PCH_ACPI_GPE0a_STS_HOT_PLUG
|
||||
);
|
||||
|
||||
SmiSts |=
|
||||
(
|
||||
B_PCH_SMI_STS_SMBUS |
|
||||
B_PCH_SMI_STS_PERIODIC |
|
||||
B_PCH_SMI_STS_TCO |
|
||||
B_PCH_SMI_STS_SWSMI_TMR |
|
||||
B_PCH_SMI_STS_APM |
|
||||
B_PCH_SMI_STS_ON_SLP_EN |
|
||||
B_PCH_SMI_STS_BIOS
|
||||
);
|
||||
|
||||
//
|
||||
// Write them back
|
||||
//
|
||||
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, Pm1Sts);
|
||||
IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS, Gpe0Sts);
|
||||
IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS, SmiSts);
|
||||
}
|
||||
|
||||
/**
|
||||
Issue PCI-E Secondary Bus Reset
|
||||
|
||||
@param Bus Bus number of the bridge
|
||||
@param Dev Devices number of the bridge
|
||||
@param Fun Function number of the bridge
|
||||
|
||||
@retval EFI_SUCCESS
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
PcieSecondaryBusReset (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN UINT8 Bus,
|
||||
IN UINT8 Dev,
|
||||
IN UINT8 Fun
|
||||
)
|
||||
{
|
||||
EFI_PEI_STALL_PPI *PeiStall;
|
||||
EFI_STATUS Status;
|
||||
|
||||
Status = (**PeiServices).LocatePpi (
|
||||
PeiServices,
|
||||
&gEfiPeiStallPpiGuid,
|
||||
0,
|
||||
NULL,
|
||||
(void **)&PeiStall
|
||||
);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
//
|
||||
// Issue secondary bus reset
|
||||
//
|
||||
MmPci16Or(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS);
|
||||
|
||||
//
|
||||
// Wait 1ms
|
||||
//
|
||||
PeiStall->Stall (PeiServices, PeiStall, 1000);
|
||||
|
||||
|
||||
//
|
||||
// Clear the reset bit
|
||||
// Note: The PCIe spec suggests 100ms delay between clearing this bit and accessing
|
||||
// the device's config space. Since we will not access the config space until we enter DXE
|
||||
// we don't put delay expressly here.
|
||||
//
|
||||
MmPci16And(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, ~(EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS));
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Provide hard reset PPI service.
|
||||
To generate full hard reset, write 0x0E to ICH RESET_GENERATOR_PORT (0xCF9).
|
||||
|
||||
@param PeiServices General purpose services available to every PEIM.
|
||||
|
||||
@retval Not return System reset occured.
|
||||
@retval EFI_DEVICE_ERROR Device error, could not reset the system.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
IchReset (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
IoWrite8 (
|
||||
R_PCH_RST_CNT,
|
||||
V_PCH_RST_CNT_HARDSTARTSTATE
|
||||
);
|
||||
|
||||
IoWrite8 (
|
||||
R_PCH_RST_CNT,
|
||||
V_PCH_RST_CNT_HARDRESET
|
||||
);
|
||||
|
||||
//
|
||||
// System reset occured, should never reach at this line.
|
||||
//
|
||||
ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
|
||||
CpuDeadLoop();
|
||||
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
VOID
|
||||
PchPlatformLpcInit (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
)
|
||||
{
|
||||
EFI_BOOT_MODE BootMode;
|
||||
UINT8 Data8;
|
||||
UINT16 Data16;
|
||||
|
||||
(*PeiServices)->GetBootMode(PeiServices, &BootMode);
|
||||
|
||||
if ((BootMode != BOOT_ON_S3_RESUME)) {
|
||||
|
||||
//
|
||||
// Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI
|
||||
//
|
||||
ClearSmiAndWake ();
|
||||
}
|
||||
|
||||
ClearPowerState (SystemConfiguration);
|
||||
|
||||
//
|
||||
// Need to set and clear SET bit (RTC_REGB Bit 7) as requested by the ICH EDS
|
||||
// early in POST after each power up directly after coin-cell battery insertion.
|
||||
// This is to avoid the UIP bit (RTC_REGA Bit 7) from stuck at "1".
|
||||
// The UIP bit status may be polled by software (i.e ME FW) during POST.
|
||||
//
|
||||
if (MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) {
|
||||
//
|
||||
// Set and clear SET bit in RTC_REGB
|
||||
//
|
||||
IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB);
|
||||
Data8 = IoRead8(R_PCH_RTC_TARGET);
|
||||
Data8 |= B_PCH_RTC_REGISTERB_SET;
|
||||
IoWrite8(R_PCH_RTC_TARGET, Data8);
|
||||
|
||||
IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB);
|
||||
Data8 &= (~B_PCH_RTC_REGISTERB_SET);
|
||||
IoWrite8(R_PCH_RTC_TARGET, Data8);
|
||||
|
||||
//
|
||||
// Clear the UIP bit in RTC_REGA
|
||||
//
|
||||
IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERA);
|
||||
IoWrite8(R_PCH_RTC_TARGET, 0x00);
|
||||
}
|
||||
|
||||
//
|
||||
// Disable SERR NMI and IOCHK# NMI in port 61
|
||||
//
|
||||
Data8 = IoRead8 (R_PCH_NMI_SC);
|
||||
IoWrite8(R_PCH_NMI_SC, (UINT8) (Data8 | B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN));
|
||||
|
||||
//
|
||||
// Enable Bus Master, I/O, Mem, and SERR on LPC bridge
|
||||
//
|
||||
Data16 = PchLpcPciCfg16 (R_PCH_LPC_COMMAND);
|
||||
MmioWrite16 (
|
||||
MmPciAddress (0,
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH,
|
||||
PCI_DEVICE_NUMBER_PCH_LPC,
|
||||
PCI_FUNCTION_NUMBER_PCH_LPC,
|
||||
R_PCH_LPC_COMMAND
|
||||
),
|
||||
(Data16 |
|
||||
B_PCH_LPC_COMMAND_IOSE |
|
||||
B_PCH_LPC_COMMAND_MSE |
|
||||
B_PCH_LPC_COMMAND_BME |
|
||||
B_PCH_LPC_COMMAND_SERR_EN)
|
||||
);
|
||||
|
||||
//
|
||||
// Set Stretch S4 to 1-2s per marketing request.
|
||||
// Note: This register is powered by RTC well.
|
||||
//
|
||||
MmioAndThenOr8 (
|
||||
PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 ,
|
||||
(UINT8) (~B_PCH_PMC_GEN_PMCON_SLP_S4_MAW),
|
||||
(UINT8) (B_PCH_PMC_GEN_PMCON_SLP_S4_ASE | V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
|
||||
|
||||
VOID
|
||||
UARTInit (
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
)
|
||||
{
|
||||
if (0) { // for fix cr4 issue
|
||||
//
|
||||
// Program and enable PMC Base.
|
||||
//
|
||||
IoWrite32 (0xCF8, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
|
||||
IoWrite32 (0xCFC, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
|
||||
|
||||
if( (SystemConfiguration->PcuUart1 == 1) &&
|
||||
(SystemConfiguration->LpssHsuart0Enabled == 0)){
|
||||
//
|
||||
// Enable COM1 for debug message output.
|
||||
//
|
||||
MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, BIT24);
|
||||
|
||||
//
|
||||
//Enable internal UART3 port(COM1)
|
||||
//
|
||||
MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
|
||||
MmioOr32 (IO_BASE_ADDRESS + 0x0520, 0x01); // UART3_RXD-L
|
||||
MmioOr32 (IO_BASE_ADDRESS + 0x0530, 0x01); // UART3_TXD-0
|
||||
MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);
|
||||
} else {
|
||||
//
|
||||
//Disable UART3(COM1)
|
||||
//
|
||||
MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
|
||||
MmioAnd32 (IO_BASE_ADDRESS + 0x0520, ~(UINT32)0x07);
|
||||
MmioAnd32 (IO_BASE_ADDRESS + 0x0530, ~(UINT32)0x07);
|
||||
MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) ~B_PCH_LPC_UART_CTRL_COM1_EN);
|
||||
|
||||
|
||||
if (SystemConfiguration->LpssHsuart0Enabled == 1){
|
||||
//
|
||||
//Valleyview BIOS Specification Vol2,17.2
|
||||
//LPSS_UART1 <20>C set each pad PAD_CONF0.Func_Pin_Mux to function 1:
|
||||
//
|
||||
MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);
|
||||
MmioOr8 (IO_BASE_ADDRESS + 0x0090, 0x01);
|
||||
MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);
|
||||
MmioOr8 (IO_BASE_ADDRESS + 0x00D0, 0x01);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
DEBUG ((EFI_D_ERROR, "EnableInternalUart\n"));
|
||||
} else {
|
||||
//
|
||||
// If SIO UART interface selected
|
||||
//Disable internal UART port(COM1)
|
||||
//
|
||||
if (0) {; // For fix CR4 issue
|
||||
MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
|
||||
MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);
|
||||
MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);
|
||||
MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) ~B_PCH_LPC_UART_CTRL_COM1_EN);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
IchRcrbInit (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
)
|
||||
{
|
||||
UINT8 LpcRevisionID;
|
||||
EFI_PLATFORM_CPU_INFO *PlatformCpuInfo;
|
||||
EFI_PEI_HOB_POINTERS Hob;
|
||||
EFI_BOOT_MODE BootMode;
|
||||
|
||||
//
|
||||
// Get Platform Info HOB
|
||||
//
|
||||
Hob.Raw = GetFirstGuidHob (&gEfiPlatformCpuInfoGuid);
|
||||
ASSERT (Hob.Raw != NULL);
|
||||
PlatformCpuInfo = GET_GUID_HOB_DATA(Hob.Raw);
|
||||
|
||||
(*PeiServices)->GetBootMode(PeiServices, &BootMode);
|
||||
|
||||
//
|
||||
// If not recovery or flash update boot path. set the BIOS interface lock down bit.
|
||||
// It locks the top swap bit and BIOS boot strap bits from being changed.
|
||||
//
|
||||
if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
|
||||
MmioOr8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS, B_PCH_RCRB_GCS_BILD);
|
||||
}
|
||||
|
||||
//
|
||||
// Disable the Watchdog timer expiration from causing a system reset
|
||||
//
|
||||
MmioOr8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, B_PCH_PMC_PM_CFG_NO_REBOOT);
|
||||
|
||||
//
|
||||
// Initial RCBA according to the PeiRCBA table
|
||||
//
|
||||
LpcRevisionID = PchLpcPciCfg8 (R_PCH_LPC_RID_CC);
|
||||
|
||||
if ((BootMode == BOOT_ON_S3_RESUME)) {
|
||||
//
|
||||
// We are resuming from S3
|
||||
// Enable HPET if enabled in Setup
|
||||
// ICH Config register Offset 0x3404 bit 7 (Enable) = 1,
|
||||
// Bit 1:0 (Mem I/O address) = 0 (0xFED00000)
|
||||
//
|
||||
MmioOr8 (R_PCH_PCH_HPET + R_PCH_PCH_HPET_GCFG, B_PCH_PCH_HPET_GCFG_EN);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
PlatformPchInit (
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration,
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN UINT16 PlatformType
|
||||
)
|
||||
{
|
||||
IchRcrbInit (PeiServices, SystemConfiguration);
|
||||
|
||||
//
|
||||
// PCH Policy Initialization based on Setup variable.
|
||||
//
|
||||
PchPolicySetupInit (PeiServices, SystemConfiguration);
|
||||
|
||||
UARTInit(SystemConfiguration);
|
||||
|
||||
PchPlatformLpcInit (PeiServices, SystemConfiguration);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
Returns the state of A16 inversion
|
||||
|
||||
@retval TRUE A16 is inverted
|
||||
@retval FALSE A16 is not inverted
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
IsA16Inverted (
|
||||
)
|
||||
{
|
||||
UINT8 Data;
|
||||
Data = MmioRead8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS);
|
||||
return (Data & B_PCH_RCRB_GCS_TS) ? TRUE : FALSE;
|
||||
}
|
||||
|
||||
VOID
|
||||
PchPolicySetupInit (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PEI_PPI_DESCRIPTOR *PchPlatformPolicyPpiDesc;
|
||||
PCH_PLATFORM_POLICY_PPI *PchPlatformPolicyPpi;
|
||||
PCH_HPET_CONFIG *HpetConfig;
|
||||
PCH_PCIE_CONFIG *PcieConfig;
|
||||
UINT8 Index;
|
||||
PCH_IOAPIC_CONFIG *IoApicConfig;
|
||||
PCH_LPSS_CONFIG *LpssConfig;
|
||||
UINT32 SpiHsfsReg;
|
||||
UINT32 SpiFdodReg;
|
||||
|
||||
//
|
||||
// Disable codec ALC-262
|
||||
//
|
||||
UINT32 IoBase;
|
||||
|
||||
//
|
||||
// Install Pch Platform Policy PPI. As we depend on Pch Init PPI so we are executed after
|
||||
// PchInit PEIM. Thus we can insure PCH Initialization is performed when we install the Pch Platform Policy PPI,
|
||||
// as PchInit PEIM registered a notification function on our policy PPI.
|
||||
//
|
||||
// --cr-- For better code structure / modularity, we should use a notification function on Pch Init PPI to perform
|
||||
// actions that depend on PchInit PEIM's initialization.
|
||||
//
|
||||
//Todo: confirm if we need update to PCH_PLATFORM_POLICY_PPI_REVISION_5
|
||||
//
|
||||
DEBUG ((EFI_D_ERROR, "PchPolicySetupInit() - Start\n"));
|
||||
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), (void **)&PchPlatformPolicyPpiDesc);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PLATFORM_POLICY_PPI), (void **)&PchPlatformPolicyPpi);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_HPET_CONFIG), (void **)&HpetConfig);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PCIE_CONFIG), (void **)&PcieConfig);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_IOAPIC_CONFIG), (void **)&IoApicConfig);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_LPSS_CONFIG), (void **)&LpssConfig);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
PchPlatformPolicyPpi->Revision = PCH_PLATFORM_POLICY_PPI_REVISION_1;
|
||||
PchPlatformPolicyPpi->BusNumber = DEFAULT_PCI_BUS_NUMBER_PCH;
|
||||
PchPlatformPolicyPpi->SpiBase = SPI_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->PmcBase = PMC_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->IoBase = IO_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->IlbBase = ILB_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->PUnitBase = PUNIT_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->MphyBase = MPHY_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->Rcba = RCBA_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->AcpiBase = ACPI_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->GpioBase = GPIO_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->SataMode = SystemConfiguration->SataType;
|
||||
PchPlatformPolicyPpi->EnableRmh = SystemConfiguration->PchUsbRmh;
|
||||
|
||||
PchPlatformPolicyPpi->EhciPllCfgEnable = SystemConfiguration->EhciPllCfgEnable;
|
||||
|
||||
|
||||
PchPlatformPolicyPpi->HpetConfig = HpetConfig;
|
||||
PchPlatformPolicyPpi->PcieConfig = PcieConfig;
|
||||
PchPlatformPolicyPpi->IoApicConfig = IoApicConfig;
|
||||
|
||||
PchPlatformPolicyPpi->HpetConfig->Enable = SystemConfiguration->Hpet;
|
||||
PchPlatformPolicyPpi->HpetConfig->Base = HPET_BASE_ADDRESS;
|
||||
PchPlatformPolicyPpi->IoApicConfig->IoApicId = 0x01;
|
||||
|
||||
//
|
||||
// Set LPSS configuration according to setup value.
|
||||
//
|
||||
PchPlatformPolicyPpi->LpssConfig->LpssPciModeEnabled = SystemConfiguration->LpssPciModeEnabled;
|
||||
|
||||
PchPlatformPolicyPpi->LpssConfig->Dma1Enabled = SystemConfiguration->LpssDma1Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->I2C0Enabled = SystemConfiguration->LpssI2C0Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->I2C1Enabled = SystemConfiguration->LpssI2C1Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->I2C2Enabled = SystemConfiguration->LpssI2C2Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->I2C3Enabled = SystemConfiguration->LpssI2C3Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->I2C4Enabled = SystemConfiguration->LpssI2C4Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->I2C5Enabled = SystemConfiguration->LpssI2C5Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->I2C6Enabled = SystemConfiguration->LpssI2C6Enabled;
|
||||
|
||||
PchPlatformPolicyPpi->LpssConfig->Dma0Enabled = SystemConfiguration->LpssDma0Enabled;;
|
||||
PchPlatformPolicyPpi->LpssConfig->Pwm0Enabled = SystemConfiguration->LpssPwm0Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->Pwm1Enabled = SystemConfiguration->LpssPwm1Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->Hsuart0Enabled = SystemConfiguration->LpssHsuart0Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->Hsuart1Enabled = SystemConfiguration->LpssHsuart1Enabled;
|
||||
PchPlatformPolicyPpi->LpssConfig->SpiEnabled = SystemConfiguration->LpssSpiEnabled;
|
||||
|
||||
|
||||
for (Index = 0; Index < PCH_PCIE_MAX_ROOT_PORTS; Index++) {
|
||||
PchPlatformPolicyPpi->PcieConfig->PcieSpeed[Index] = SystemConfiguration->PcieRootPortSpeed[Index];
|
||||
}
|
||||
|
||||
SpiHsfsReg = MmioRead32 (SPI_BASE_ADDRESS + R_PCH_SPI_HSFS);
|
||||
if ((SpiHsfsReg & B_PCH_SPI_HSFS_FDV) == B_PCH_SPI_HSFS_FDV) {
|
||||
MmioWrite32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOC, V_PCH_SPI_FDOC_FDSS_FSDM);
|
||||
SpiFdodReg = MmioRead32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOD);
|
||||
if (SpiFdodReg == V_PCH_SPI_FDBAR_FLVALSIG) {
|
||||
}
|
||||
//
|
||||
// Disable codec ALC-262
|
||||
//
|
||||
if (SystemConfiguration->DisableCodec262 == 1) {
|
||||
IoBase = MmioRead32 (MmPciAddress (0,
|
||||
PchPlatformPolicyPpi->BusNumber,
|
||||
PCI_DEVICE_NUMBER_PCH_LPC,
|
||||
PCI_FUNCTION_NUMBER_PCH_LPC,
|
||||
0
|
||||
) + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;
|
||||
MmioAnd32 ((UINTN) (IoBase + 0x270), (UINT32) (~0x07));
|
||||
}
|
||||
}
|
||||
|
||||
PchPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
|
||||
PchPlatformPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid;
|
||||
PchPlatformPolicyPpiDesc->Ppi = PchPlatformPolicyPpi;
|
||||
|
||||
//
|
||||
// Install PCH Platform Policy PPI
|
||||
//
|
||||
Status = (**PeiServices).InstallPpi (
|
||||
PeiServices,
|
||||
PchPlatformPolicyPpiDesc
|
||||
);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
DEBUG ((EFI_D_ERROR, "PchPolicySetupInit() - End\n"));
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
InstallPeiPchUsbPolicy (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
|
||||
EFI_PEI_PPI_DESCRIPTOR *PeiPchUsbPolicyPpiDesc;
|
||||
PCH_USB_POLICY_PPI *PeiPchUsbPolicyPpi;
|
||||
PCH_USB_CONFIG *UsbConfig;
|
||||
EFI_PLATFORM_INFO_HOB PlatformInfo;
|
||||
|
||||
//
|
||||
// Allocate descriptor and PPI structures. Since these are dynamically updated
|
||||
// we cannot do a global variable PPI.
|
||||
//
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), (void **)&PeiPchUsbPolicyPpiDesc);
|
||||
|
||||
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_USB_POLICY_PPI), (void **)&PeiPchUsbPolicyPpi);
|
||||
|
||||
|
||||
|
||||
Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_USB_CONFIG), (void **)&UsbConfig);
|
||||
|
||||
|
||||
//
|
||||
// Initiate PCH USB policy.
|
||||
//
|
||||
PeiPchUsbPolicyPpi->Revision = PCH_USB_POLICY_PPI_REVISION_1;
|
||||
UsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_ENABLE;
|
||||
UsbConfig->UsbPerPortCtl = PCH_DEVICE_DISABLE;
|
||||
UsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE;
|
||||
|
||||
//
|
||||
// Initialize PlatformInfo HOB
|
||||
//
|
||||
ZeroMem (&PlatformInfo, sizeof(PlatformInfo));
|
||||
MultiPlatformInfoInit(PeiServices, &PlatformInfo);
|
||||
|
||||
UsbConfig->Usb20OverCurrentPins[0] = PchUsbOverCurrentPin0;
|
||||
|
||||
UsbConfig->Usb20OverCurrentPins[1] = PchUsbOverCurrentPin0;
|
||||
|
||||
UsbConfig->Usb20OverCurrentPins[2] = PchUsbOverCurrentPin1;
|
||||
|
||||
UsbConfig->Usb20OverCurrentPins[3] = PchUsbOverCurrentPin1;
|
||||
|
||||
|
||||
//
|
||||
// Enable USB Topology control and program the topology setting for every USB port
|
||||
// See Platform Design Guide for description of topologies
|
||||
//
|
||||
//
|
||||
// Port 0: ~10.9", Port 1: ~10.1", Port 2: ~11.2", Port 3: ~11.5", Port 4: ~3.7", Port 5: ~2.7", Port 6: ~4.1"
|
||||
// Port 7: ~4.5", Port 8: ~10.7", Port 9: ~10.5", Port 10: ~4.2", Port 11: ~4.3", Port 12: ~3.1", Port 13: ~2.9"
|
||||
//
|
||||
|
||||
//
|
||||
// Port 0: ~3.5", Port 1: ~4.1", Port 2: ~4.6", Port 3: ~4.6", Port 4: ~12.5", Port 5: ~12", Port 6: ~5.1"
|
||||
// Port 7: ~5.1", Port 8: ~4.1", Port 9: ~4.1", Port 10: ~14.5", Port 11: ~12.8", Port 12: ~12.9", Port 13: ~14.6"
|
||||
//
|
||||
UsbConfig->Usb20PortLength[0] = 0x53;
|
||||
UsbConfig->Usb20PortLength[1] = 0x49;
|
||||
UsbConfig->Usb20PortLength[2] = 0x47;
|
||||
UsbConfig->Usb20PortLength[3] = 0x80;
|
||||
|
||||
PeiPchUsbPolicyPpi->Mode = EHCI_MODE;
|
||||
|
||||
PeiPchUsbPolicyPpi->EhciMemBaseAddr = PcdGet32(PcdPeiIchEhciControllerMemoryBaseAddress);
|
||||
|
||||
PeiPchUsbPolicyPpi->EhciMemLength = (UINT32) 0x400 * PchEhciControllerMax;
|
||||
|
||||
PeiPchUsbPolicyPpi->UsbConfig = UsbConfig;
|
||||
|
||||
PeiPchUsbPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
|
||||
|
||||
PeiPchUsbPolicyPpiDesc->Guid = &gPchUsbPolicyPpiGuid;
|
||||
|
||||
1034
Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
Normal file
1034
Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
Normal file
File diff suppressed because it is too large
Load Diff
1502
Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h
Normal file
1502
Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h
Normal file
File diff suppressed because it is too large
Load Diff
186
Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c
Normal file
186
Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c
Normal file
@@ -0,0 +1,186 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PlatformInfoInit.c
|
||||
|
||||
Abstract:
|
||||
Platform Info Driver.
|
||||
|
||||
--*/
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
#define LEN_64M 0x4000000
|
||||
|
||||
//
|
||||
// Default PCI32 resource size
|
||||
//
|
||||
#define RES_MEM32_MIN_LEN 0x38000000
|
||||
|
||||
#define RES_IO_BASE 0x0D00
|
||||
#define RES_IO_LIMIT 0xFFFF
|
||||
|
||||
#define MemoryCeilingVariable L"MemCeil."
|
||||
|
||||
EFI_STATUS
|
||||
CheckOsSelection (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
|
||||
UINTN VariableSize;
|
||||
EFI_OS_SELECTION_HOB *OsSelectionHob;
|
||||
UINT8 OsSelection;
|
||||
UINT8 *LpssDataHobPtr;
|
||||
UINT8 *LpssDataVarPtr;
|
||||
UINTN i;
|
||||
|
||||
Status = (*PeiServices)->LocatePpi (
|
||||
PeiServices,
|
||||
&gEfiPeiReadOnlyVariable2PpiGuid,
|
||||
0,
|
||||
NULL,
|
||||
(void **)&Variable
|
||||
);
|
||||
if (!EFI_ERROR(Status)) {
|
||||
VariableSize = sizeof (OsSelection);
|
||||
Status = Variable->GetVariable (
|
||||
Variable,
|
||||
L"OsSelection",
|
||||
&gOsSelectionVariableGuid,
|
||||
NULL,
|
||||
&VariableSize,
|
||||
&OsSelection
|
||||
);
|
||||
|
||||
if (!EFI_ERROR(Status) && (SystemConfiguration->ReservedO != OsSelection)) {
|
||||
//
|
||||
// Build HOB for OsSelection
|
||||
//
|
||||
OsSelectionHob = BuildGuidHob (&gOsSelectionVariableGuid, sizeof (EFI_OS_SELECTION_HOB));
|
||||
ASSERT (OsSelectionHob != NULL);
|
||||
|
||||
OsSelectionHob->OsSelectionChanged = TRUE;
|
||||
OsSelectionHob->OsSelection = OsSelection;
|
||||
SystemConfiguration->ReservedO = OsSelectionHob->OsSelection;
|
||||
|
||||
//
|
||||
// Load LPSS and SCC defalut configurations
|
||||
//
|
||||
OsSelectionHob->LpssData.LpsseMMCEnabled = FALSE;
|
||||
OsSelectionHob->LpssData.LpssSdioEnabled = TRUE;
|
||||
OsSelectionHob->LpssData.LpssSdcardEnabled = TRUE;
|
||||
OsSelectionHob->LpssData.LpssSdCardSDR25Enabled = FALSE;
|
||||
OsSelectionHob->LpssData.LpssSdCardDDR50Enabled = TRUE;
|
||||
OsSelectionHob->LpssData.LpssMipiHsi = FALSE;
|
||||
OsSelectionHob->LpssData.LpsseMMC45Enabled = TRUE;
|
||||
OsSelectionHob->LpssData.LpsseMMC45DDR50Enabled = TRUE;
|
||||
OsSelectionHob->LpssData.LpsseMMC45HS200Enabled = FALSE;
|
||||
OsSelectionHob->LpssData.LpsseMMC45RetuneTimerValue = 8;
|
||||
OsSelectionHob->LpssData.eMMCBootMode = 1; // Auto Detect
|
||||
|
||||
|
||||
SystemConfiguration->Lpe = OsSelectionHob->Lpe;
|
||||
SystemConfiguration->PchAzalia = SystemConfiguration->PchAzalia;
|
||||
LpssDataHobPtr = &OsSelectionHob->LpssData.LpssPciModeEnabled;
|
||||
LpssDataVarPtr = &SystemConfiguration->LpssPciModeEnabled;
|
||||
|
||||
for (i = 0; i < sizeof(EFI_PLATFORM_LPSS_DATA); i++) {
|
||||
*LpssDataVarPtr = *LpssDataHobPtr;
|
||||
LpssDataVarPtr++;
|
||||
LpssDataHobPtr++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
PlatformInfoUpdate (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob,
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
|
||||
UINTN VariableSize;
|
||||
UINT32 MemoryCeiling;
|
||||
|
||||
//
|
||||
// Checking PCI32 resource from previous boot to determine the memory ceiling
|
||||
//
|
||||
Status = (*PeiServices)->LocatePpi (
|
||||
PeiServices,
|
||||
&gEfiPeiReadOnlyVariable2PpiGuid,
|
||||
0,
|
||||
NULL,
|
||||
(void **)&Variable
|
||||
);
|
||||
if (!EFI_ERROR(Status)) {
|
||||
//
|
||||
// Get the memory ceiling
|
||||
//
|
||||
VariableSize = sizeof(MemoryCeiling);
|
||||
Status = Variable->GetVariable (
|
||||
Variable,
|
||||
MemoryCeilingVariable,
|
||||
&gEfiGlobalVariableGuid,
|
||||
NULL,
|
||||
&VariableSize,
|
||||
&MemoryCeiling
|
||||
);
|
||||
if(!EFI_ERROR(Status)) {
|
||||
//
|
||||
// Set the new PCI32 resource Base if the variable available
|
||||
//
|
||||
PlatformInfoHob->PciData.PciResourceMem32Base = MemoryCeiling;
|
||||
PlatformInfoHob->MemData.MemMaxTolm = MemoryCeiling;
|
||||
PlatformInfoHob->MemData.MemTolm = MemoryCeiling;
|
||||
|
||||
//
|
||||
// Platform PCI MMIO Size in unit of 1MB
|
||||
//
|
||||
PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
|
||||
}
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Initialize the platform related info hob according to the
|
||||
pre-determine value or setup option
|
||||
|
||||
@retval EFI_SUCCESS Memory initialization completed successfully.
|
||||
@retval Others All other error conditions encountered result in an ASSERT.
|
||||
**/
|
||||
EFI_STATUS
|
||||
InitializePlatform (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob,
|
||||
122
Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf
Normal file
122
Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf
Normal file
@@ -0,0 +1,122 @@
|
||||
#
|
||||
#
|
||||
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
#
|
||||
|
||||
# This program and the accompanying materials are licensed and made available under
|
||||
|
||||
# the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
# The full text of the license may be found at
|
||||
|
||||
# http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
#
|
||||
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
#
|
||||
|
||||
#
|
||||
#
|
||||
# Module Name:
|
||||
#
|
||||
# PlatformEarlyInit.inf
|
||||
#
|
||||
# Abstract:
|
||||
#
|
||||
# Component description file for PlatformEarlyInit module
|
||||
#
|
||||
#--*/
|
||||
|
||||
[defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = PlatformEarlyInit
|
||||
FILE_GUID = 0A5EA2E1-BE0B-44a0-A775-F429C9A018A0
|
||||
MODULE_TYPE = PEIM
|
||||
VERSION_STRING = 1.0
|
||||
PI_SPECIFICATION_VERSION = 0x0001000A
|
||||
ENTRY_POINT = PlatformEarlyInitEntry
|
||||
|
||||
[sources.common]
|
||||
BootMode.c
|
||||
CpuInitPeim.c
|
||||
PchInitPeim.c
|
||||
MchInit.c
|
||||
MemoryCallback.c
|
||||
MemoryPeim.c
|
||||
PlatformEarlyInit.c
|
||||
PlatformEarlyInit.h
|
||||
PlatformInfoInit.c
|
||||
LegacySpeaker.c
|
||||
LegacySpeaker.h
|
||||
Stall.c
|
||||
PlatformSsaInitPeim.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
Vlv2TbltDevicePkg/PlatformPkg.dec
|
||||
IntelFrameworkPkg/IntelFrameworkPkg.dec
|
||||
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
|
||||
IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec
|
||||
UefiCpuPkg/UefiCpuPkg.dec
|
||||
Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
|
||||
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
PeimEntryPoint
|
||||
DebugLib
|
||||
HobLib
|
||||
IoLib
|
||||
# PeiKscLib
|
||||
MultiPlatformLib
|
||||
PcdLib
|
||||
PchPlatformLib
|
||||
MtrrLib
|
||||
|
||||
[Ppis]
|
||||
gEfiPeiStallPpiGuid
|
||||
gPeiSpeakerInterfacePpiGuid
|
||||
gEfiPeiMemoryDiscoveredPpiGuid
|
||||
gVlvPolicyPpiGuid
|
||||
gEfiPeiReadOnlyVariable2PpiGuid
|
||||
gEfiPeiResetPpiGuid
|
||||
gEfiEndOfPeiSignalPpiGuid
|
||||
gPeiSmbusPolicyPpiGuid
|
||||
gEfiFindFvPpiGuid
|
||||
gPeiCapsulePpiGuid
|
||||
gEfiPeiBootInRecoveryModePpiGuid
|
||||
gEfiPeiRecoveryModulePpiGuid
|
||||
gEfiPeiDeviceRecoveryModulePpiGuid
|
||||
gPeiCachePpiGuid
|
||||
gEfiPeiMasterBootModePpiGuid
|
||||
gEfiPeiSmbusPpiGuid
|
||||
gPchInitPpiGuid
|
||||
gPchUsbPolicyPpiGuid
|
||||
|
||||
[Guids]
|
||||
gEfiSetupVariableGuid
|
||||
gEfiPlatformInfoGuid
|
||||
gEfiPlatformBootModeGuid
|
||||
gEfiPlatformCpuInfoGuid
|
||||
gEfiGlobalVariableGuid
|
||||
gRecoveryOnFatFloppyDiskGuid
|
||||
gRecoveryOnFatUsbDiskGuid
|
||||
gRecoveryOnFatIdeDiskGuid
|
||||
gRecoveryOnDataCdGuid
|
||||
gMfgModeVariableGuid
|
||||
gEfiNormalSetupGuid
|
||||
gEfiMemoryTypeInformationGuid
|
||||
gOsSelectionVariableGuid
|
||||
|
||||
[Pcd.common]
|
||||
gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
|
||||
gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
|
||||
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
|
||||
gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress
|
||||
|
||||
gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
|
||||
gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize
|
||||
63
Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c
Normal file
63
Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c
Normal file
@@ -0,0 +1,63 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
|
||||
PlatformSsaInitPeim.c
|
||||
|
||||
Abstract:
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
/**
|
||||
Perform SSA related platform initialization.
|
||||
|
||||
**/
|
||||
VOID
|
||||
PlatformSsaInit (
|
||||
IN SYSTEM_CONFIGURATION *SystemConfiguration,
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
|
||||
DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Start\n"));
|
||||
DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - SystemConfiguration->ISPDevSel 0x%x\n",SystemConfiguration->ISPDevSel));
|
||||
if(SystemConfiguration->ISPDevSel == 0x02)
|
||||
{
|
||||
//
|
||||
// Device 3 Interrupt Route
|
||||
//
|
||||
MmioWrite16 (
|
||||
(ILB_BASE_ADDRESS + R_PCH_ILB_D3IR),
|
||||
V_PCH_ILB_DXXIR_IAR_PIRQH // For IUNIT
|
||||
);
|
||||
MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D3IR); // Read Posted Writes Register
|
||||
DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 3 Interrupt Route Done\n"));
|
||||
}
|
||||
|
||||
//
|
||||
// Device 2 Interrupt Route
|
||||
//
|
||||
366
Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c
Normal file
366
Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c
Normal file
@@ -0,0 +1,366 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
|
||||
Recovery.c
|
||||
|
||||
Abstract:
|
||||
|
||||
Tiano PEIM to provide the platform recovery functionality.
|
||||
|
||||
--*/
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
#define PEI_FVMAIN_COMPACT_GUID \
|
||||
{0x4A538818, 0x5AE0, 0x4eb2, 0xB2, 0xEB, 0x48, 0x8b, 0x23, 0x65, 0x70, 0x22};
|
||||
|
||||
EFI_GUID FvMainCompactFileGuid = PEI_FVMAIN_COMPACT_GUID;
|
||||
|
||||
//
|
||||
// Required Service
|
||||
//
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PlatformRecoveryModule (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN EFI_PEI_RECOVERY_MODULE_PPI *This
|
||||
);
|
||||
|
||||
//
|
||||
// Module globals
|
||||
//
|
||||
|
||||
typedef struct {
|
||||
EFI_GUID CapsuleGuid;
|
||||
UINT32 HeaderSize;
|
||||
UINT32 Flags;
|
||||
UINT32 CapsuleImageSize;
|
||||
UINT32 SequenceNumber;
|
||||
EFI_GUID InstanceId;
|
||||
UINT32 OffsetToSplitInformation;
|
||||
UINT32 OffsetToCapsuleBody;
|
||||
UINT32 OffsetToOemDefinedHeader;
|
||||
UINT32 OffsetToAuthorInformation;
|
||||
UINT32 OffsetToRevisionInformation;
|
||||
UINT32 OffsetToShortDescription;
|
||||
UINT32 OffsetToLongDescription;
|
||||
UINT32 OffsetToApplicableDevices;
|
||||
} OLD_EFI_CAPSULE_HEADER;
|
||||
|
||||
|
||||
static EFI_PEI_RECOVERY_MODULE_PPI mRecoveryPpi = {
|
||||
PlatformRecoveryModule
|
||||
};
|
||||
|
||||
static EFI_PEI_PPI_DESCRIPTOR mRecoveryPpiList = {
|
||||
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
|
||||
&gEfiPeiRecoveryModulePpiGuid,
|
||||
&mRecoveryPpi
|
||||
};
|
||||
|
||||
/**
|
||||
Provide the functionality of the Recovery Module.
|
||||
|
||||
@param PeiServices General purpose services available to every PEIM.
|
||||
|
||||
@retval Status EFI_SUCCESS if the interface could be successfully
|
||||
installed
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PeimInitializeRecovery (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
Status = (*PeiServices)->InstallPpi (
|
||||
PeiServices,
|
||||
&mRecoveryPpiList
|
||||
);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
Provide the functionality of the Ea Recovery Module.
|
||||
|
||||
@param PeiServices General purpose services available to every PEIM.
|
||||
@param This Pointer to PEI_RECOVERY_MODULE_INTERFACE.
|
||||
|
||||
@retval EFI_SUCCESS If the interface could be successfully
|
||||
installed.
|
||||
@retval EFI_UNSUPPORTED Not supported.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PlatformRecoveryModule (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN EFI_PEI_RECOVERY_MODULE_PPI *This
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *DeviceRecoveryModule;
|
||||
UINTN NumberOfImageProviders;
|
||||
BOOLEAN ProviderAvailable;
|
||||
UINTN NumberRecoveryCapsules;
|
||||
UINTN RecoveryCapsuleSize;
|
||||
EFI_GUID DeviceId;
|
||||
BOOLEAN ImageFound;
|
||||
EFI_PHYSICAL_ADDRESS Address;
|
||||
VOID *Buffer;
|
||||
OLD_EFI_CAPSULE_HEADER *CapsuleHeader;
|
||||
EFI_PEI_HOB_POINTERS Hob;
|
||||
EFI_PEI_HOB_POINTERS HobOld;
|
||||
EFI_HOB_CAPSULE_VOLUME *CapsuleHob;
|
||||
BOOLEAN HobUpdate;
|
||||
EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
|
||||
UINTN Index;
|
||||
BOOLEAN FoundFvMain;
|
||||
BOOLEAN FoundCapsule;
|
||||
static EFI_GUID mEfiCapsuleHeaderGuid = EFI_CAPSULE_GUID;
|
||||
EFI_PEI_STALL_PPI *StallPpi;
|
||||
|
||||
(*PeiServices)->ReportStatusCode (
|
||||
PeiServices,
|
||||
EFI_PROGRESS_CODE,
|
||||
EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_BEGIN,
|
||||
0,
|
||||
NULL,
|
||||
NULL
|
||||
);
|
||||
|
||||
Status = (**PeiServices).LocatePpi (
|
||||
PeiServices,
|
||||
&gEfiPeiStallPpiGuid,
|
||||
0,
|
||||
NULL,
|
||||
&StallPpi
|
||||
);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
StallPpi->Stall(
|
||||
PeiServices,
|
||||
StallPpi,
|
||||
5000000
|
||||
);
|
||||
|
||||
|
||||
Index = 0;
|
||||
|
||||
Status = EFI_SUCCESS;
|
||||
HobUpdate = FALSE;
|
||||
|
||||
ProviderAvailable = TRUE;
|
||||
ImageFound = FALSE;
|
||||
NumberOfImageProviders = 0;
|
||||
|
||||
DeviceRecoveryModule = NULL;
|
||||
|
||||
FoundCapsule = FALSE;
|
||||
FoundFvMain = FALSE;
|
||||
|
||||
DEBUG ((EFI_D_ERROR | EFI_D_LOAD, "Recovery Entry\n"));
|
||||
|
||||
//
|
||||
// Search the platform for some recovery capsule if the DXE IPL
|
||||
// discovered a recovery condition and has requested a load.
|
||||
//
|
||||
while (ProviderAvailable == TRUE) {
|
||||
|
||||
Status = (*PeiServices)->LocatePpi (
|
||||
PeiServices,
|
||||
&gEfiPeiDeviceRecoveryModulePpiGuid,
|
||||
Index,
|
||||
NULL,
|
||||
&DeviceRecoveryModule
|
||||
);
|
||||
|
||||
if (!EFI_ERROR (Status)) {
|
||||
DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Device Recovery PPI located\n"));
|
||||
NumberOfImageProviders++;
|
||||
|
||||
Status = DeviceRecoveryModule->GetNumberRecoveryCapsules (
|
||||
(EFI_PEI_SERVICES**)PeiServices,
|
||||
DeviceRecoveryModule,
|
||||
&NumberRecoveryCapsules
|
||||
);
|
||||
|
||||
DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Number Of Recovery Capsules: %d\n", NumberRecoveryCapsules));
|
||||
|
||||
if (NumberRecoveryCapsules == 0) {
|
||||
Index++;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
ProviderAvailable = FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// If there is an image provider, get the capsule ID
|
||||
//
|
||||
if (ProviderAvailable) {
|
||||
RecoveryCapsuleSize = 0;
|
||||
|
||||
Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo (
|
||||
(EFI_PEI_SERVICES**)PeiServices,
|
||||
DeviceRecoveryModule,
|
||||
0,
|
||||
&RecoveryCapsuleSize,
|
||||
&DeviceId
|
||||
);
|
||||
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule Size: %d\n", RecoveryCapsuleSize));
|
||||
|
||||
//
|
||||
// Only support the 2 capsule types known
|
||||
// Future enhancement is to rank-order the selection
|
||||
//
|
||||
if ((!CompareGuid (&DeviceId, &gRecoveryOnFatIdeDiskGuid)) &&
|
||||
(!CompareGuid (&DeviceId, &gRecoveryOnFatFloppyDiskGuid)) &&
|
||||
(!CompareGuid (&DeviceId, &gRecoveryOnDataCdGuid)) &&
|
||||
(!CompareGuid (&DeviceId, &gRecoveryOnFatUsbDiskGuid))
|
||||
) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
Buffer = NULL;
|
||||
Status = (*PeiServices)->AllocatePages (
|
||||
PeiServices,
|
||||
EfiBootServicesCode,
|
||||
(RecoveryCapsuleSize - 1) / 0x1000 + 1,
|
||||
&Address
|
||||
);
|
||||
|
||||
DEBUG ((EFI_D_INFO | EFI_D_LOAD, "AllocatePage Returns: %r\n", Status));
|
||||
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Buffer = (UINT8 *) (UINTN) Address;
|
||||
|
||||
(*PeiServices)->ReportStatusCode (
|
||||
PeiServices,
|
||||
EFI_PROGRESS_CODE,
|
||||
EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD,
|
||||
0,
|
||||
NULL,
|
||||
NULL
|
||||
);
|
||||
|
||||
Status = DeviceRecoveryModule->LoadRecoveryCapsule (
|
||||
(EFI_PEI_SERVICES**)PeiServices,
|
||||
DeviceRecoveryModule,
|
||||
0,
|
||||
Buffer
|
||||
);
|
||||
|
||||
DEBUG ((EFI_D_INFO | EFI_D_LOAD, "LoadRecoveryCapsule Returns: %r\n", Status));
|
||||
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Update FV Hob if found
|
||||
//
|
||||
Status = (*PeiServices)->GetHobList (PeiServices, &Hob.Raw);
|
||||
HobOld.Raw = Hob.Raw;
|
||||
while (!END_OF_HOB_LIST (Hob)) {
|
||||
if (Hob.Header->HobType == EFI_HOB_TYPE_FV) {
|
||||
DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob FV Length: %x\n", Hob.FirmwareVolume->Length));
|
||||
//
|
||||
// BUGBUG Why is it a FV hob if it is greater than 0x50000?
|
||||
//
|
||||
if (Hob.FirmwareVolume->Length > 0x50000) {
|
||||
HobUpdate = TRUE;
|
||||
//
|
||||
// This looks like the Hob we are interested in
|
||||
//
|
||||
DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob Updated\n"));
|
||||
Hob.FirmwareVolume->BaseAddress = (UINTN) Buffer;
|
||||
Hob.FirmwareVolume->Length = RecoveryCapsuleSize;
|
||||
}
|
||||
}
|
||||
Hob.Raw = GET_NEXT_HOB (Hob);
|
||||
}
|
||||
|
||||
FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Buffer;
|
||||
CapsuleHeader = (OLD_EFI_CAPSULE_HEADER *)Buffer;
|
||||
|
||||
//
|
||||
// Check if top of file is a capsule
|
||||
//
|
||||
if (CompareGuid ((EFI_GUID *)CapsuleHeader, &mEfiCapsuleHeaderGuid)) {
|
||||
FoundCapsule = TRUE;
|
||||
} else if (FvHeader->Signature == EFI_FVH_SIGNATURE) {
|
||||
//
|
||||
// Assume the Firmware volume is a "FVMAIN" image
|
||||
//
|
||||
FoundFvMain = TRUE;
|
||||
}
|
||||
|
||||
if (FoundFvMain) {
|
||||
//
|
||||
// build FV Hob if it is not built before
|
||||
//
|
||||
if (!HobUpdate) {
|
||||
DEBUG ((EFI_D_INFO | EFI_D_LOAD, "FV Hob is not found, Build FV Hob then..\n"));
|
||||
|
||||
BuildFvHob (
|
||||
(UINTN)FvHeader,
|
||||
FvHeader->FvLength
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
if (FoundCapsule) {
|
||||
//
|
||||
// Build capsule hob
|
||||
//
|
||||
Status = (*PeiServices)->CreateHob (
|
||||
PeiServices,
|
||||
EFI_HOB_TYPE_CV,
|
||||
sizeof (EFI_HOB_CAPSULE_VOLUME),
|
||||
&CapsuleHob
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
CapsuleHob->BaseAddress = (UINT64)((UINTN)CapsuleHeader + (UINTN)CapsuleHeader->OffsetToCapsuleBody);
|
||||
CapsuleHob->Length = (UINT64)((UINTN)CapsuleHeader->CapsuleImageSize -(UINTN)CapsuleHeader->OffsetToCapsuleBody);
|
||||
(*PeiServices)->ReportStatusCode (
|
||||
PeiServices,
|
||||
EFI_PROGRESS_CODE,
|
||||
EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_START,
|
||||
96
Vlv2TbltDevicePkg/PlatformInitPei/Stall.c
Normal file
96
Vlv2TbltDevicePkg/PlatformInitPei/Stall.c
Normal file
@@ -0,0 +1,96 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
|
||||
The full text of the license may be found at
|
||||
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
Stall.c
|
||||
|
||||
Abstract:
|
||||
|
||||
Produce Stall Ppi.
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
#include "PlatformEarlyInit.h"
|
||||
|
||||
|
||||
/**
|
||||
|
||||
Waits for at least the given number of microseconds.
|
||||
|
||||
@param PeiServices General purpose services available to every PEIM.
|
||||
@param This PPI instance structure.
|
||||
@param Microseconds Desired length of time to wait.
|
||||
|
||||
@retval EFI_SUCCESS If the desired amount of time was passed.
|
||||
|
||||
*/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
Stall (
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices,
|
||||
IN CONST EFI_PEI_STALL_PPI *This,
|
||||
IN UINTN Microseconds
|
||||
)
|
||||
{
|
||||
UINTN Ticks;
|
||||
UINTN Counts;
|
||||
UINT32 CurrentTick;
|
||||
UINT32 OriginalTick;
|
||||
UINT32 RemainingTick;
|
||||
|
||||
if (Microseconds == 0) {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
OriginalTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR);
|
||||
OriginalTick &= (V_PCH_ACPI_PM1_TMR_MAX_VAL - 1);
|
||||
CurrentTick = OriginalTick;
|
||||
|
||||
//
|
||||
// The timer frequency is 3.579545MHz, so 1 ms corresponds to 3.58 clocks
|
||||
//
|
||||
Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
|
||||
|
||||
//
|
||||
// The loops needed for timer overflow
|
||||
//
|
||||
Counts = (UINTN)RShiftU64((UINT64)Ticks, 24);
|
||||
|
||||
//
|
||||
// Remaining clocks within one loop
|
||||
//
|
||||
RemainingTick = Ticks & 0xFFFFFF;
|
||||
|
||||
//
|
||||
// Do not intend to use TMROF_STS bit of register PM1_STS, because this add extra
|
||||
// one I/O operation, and may generate SMI
|
||||
//
|
||||
while (Counts != 0) {
|
||||
CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;
|
||||
if (CurrentTick <= OriginalTick) {
|
||||
Counts--;
|
||||
}
|
||||
OriginalTick = CurrentTick;
|
||||
Reference in New Issue
Block a user