Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
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202
Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFunction.c
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202
Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFunction.c
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/*++
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Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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MiscProcessorCacheFunction.c
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Abstract:
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BIOS processor cache details.
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Misc. subclass type 7.
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SMBIOS type 7.
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--*/
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#include "CommonHeader.h"
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#include "MiscSubclassDriver.h"
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#include <Protocol/DataHub.h>
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#include <Guid/DataHubRecords.h>
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extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL1;
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extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL2;
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extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL3;
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UINT32
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ConvertBase2ToRaw (
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IN EFI_EXP_BASE2_DATA *Data)
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{
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UINTN Index;
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UINT32 RawData;
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RawData = Data->Value;
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for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {
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RawData <<= 1;
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}
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return RawData;
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}
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MISC_SMBIOS_TABLE_FUNCTION(MiscProcessorCache)
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{
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EFI_SMBIOS_HANDLE SmbiosHandle;
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SMBIOS_TABLE_TYPE7 *SmbiosRecordL1;
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SMBIOS_TABLE_TYPE7 *SmbiosRecordL2;
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EFI_CACHE_SRAM_TYPE_DATA CacheSramType;
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CHAR16 *SocketDesignation;
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CHAR8 *OptionalStrStart;
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UINTN SocketStrLen;
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STRING_REF TokenToGet;
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EFI_DATA_HUB_PROTOCOL *DataHub;
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UINT64 MonotonicCount;
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EFI_DATA_RECORD_HEADER *Record;
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EFI_SUBCLASS_TYPE1_HEADER *DataHeader;
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UINT8 *SrcData;
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UINT32 SrcDataSize;
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EFI_STATUS Status;
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//
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// Memory Device LOcator
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//
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DEBUG ((EFI_D_ERROR, "type 7\n"));
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TokenToGet = STRING_TOKEN (STR_SOCKET_DESIGNATION);
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SocketDesignation = SmbiosMiscGetString (TokenToGet);
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SocketStrLen = StrLen(SocketDesignation);
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if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {
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return EFI_UNSUPPORTED;
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}
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SmbiosRecordL1 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);
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ASSERT (SmbiosRecordL1 != NULL);
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ZeroMem(SmbiosRecordL1, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);
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SmbiosRecordL2 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);
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ASSERT (SmbiosRecordL2 != NULL);
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ZeroMem(SmbiosRecordL2, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);
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//
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// Get the Data Hub Protocol. Assume only one instance
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//
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Status = gBS->LocateProtocol (
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&gEfiDataHubProtocolGuid,
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NULL,
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(VOID **)&DataHub
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);
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ASSERT_EFI_ERROR(Status);
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MonotonicCount = 0;
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Record = NULL;
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do {
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Status = DataHub->GetNextRecord (
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DataHub,
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&MonotonicCount,
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NULL,
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&Record
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);
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if (!EFI_ERROR(Status)) {
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if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {
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DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);
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SrcData = (UINT8 *)(DataHeader + 1);
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SrcDataSize = Record->RecordSize - Record->HeaderSize - sizeof (EFI_SUBCLASS_TYPE1_HEADER);
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if (CompareGuid(&Record->DataRecordGuid, &gEfiCacheSubClassGuid) && (DataHeader->RecordType == CacheSizeRecordType)) {
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if (DataHeader->SubInstance == EFI_CACHE_L1) {
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SmbiosRecordL1->InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10);
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SmbiosRecordL1->MaximumCacheSize = SmbiosRecordL1->InstalledSize;
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}
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else if (DataHeader->SubInstance == EFI_CACHE_L2) {
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SmbiosRecordL2->InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10);
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SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2->InstalledSize;
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} else {
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continue;
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}
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}
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}
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}
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} while (!EFI_ERROR(Status) && (MonotonicCount != 0));
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//
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//Filling SMBIOS type 7 information for different cache levels.
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//
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SmbiosRecordL1->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;
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SmbiosRecordL1->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);
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SmbiosRecordL1->Hdr.Handle = 0;
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SmbiosRecordL1->Associativity = CacheAssociativity8Way;
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SmbiosRecordL1->SystemCacheType = CacheTypeUnknown;
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SmbiosRecordL1->SocketDesignation = 0x01;
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SmbiosRecordL1->CacheSpeed = 0;
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SmbiosRecordL1->CacheConfiguration = 0x0180;
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ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));
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CacheSramType.Synchronous = 1;
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CopyMem(&SmbiosRecordL1->SupportedSRAMType, &CacheSramType, 2);
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CopyMem(&SmbiosRecordL1->CurrentSRAMType, &CacheSramType, 2);
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SmbiosRecordL1->ErrorCorrectionType = EfiCacheErrorSingleBit;
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SmbiosRecordL2->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;
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SmbiosRecordL2->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);
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SmbiosRecordL2->Hdr.Handle = 0;
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SmbiosRecordL2->Associativity = CacheAssociativity16Way;
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SmbiosRecordL2->SystemCacheType = CacheTypeInstruction;
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SmbiosRecordL2->SocketDesignation = 0x01;
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SmbiosRecordL2->CacheSpeed = 0;
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SmbiosRecordL2->CacheConfiguration = 0x0281;
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ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));
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CacheSramType.Synchronous = 1;
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CopyMem(&SmbiosRecordL2->SupportedSRAMType, &CacheSramType, 2);
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CopyMem(&SmbiosRecordL2->CurrentSRAMType, &CacheSramType, 2);
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SmbiosRecordL2->ErrorCorrectionType = EfiCacheErrorSingleBit;
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//
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//Adding SMBIOS type 7 records to SMBIOS table.
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//
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SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
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OptionalStrStart = (CHAR8 *)(SmbiosRecordL1 + 1);
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UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);
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Smbios-> Add(
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Smbios,
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NULL,
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&SmbiosHandle,
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(EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL1
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);
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//
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//VLV2 incorporates two SLM modules (quad cores) in the SoC. 2 cores share BIU/L2 cache
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//
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SmbiosRecordL2->InstalledSize = (SmbiosRecordL2->InstalledSize)/2;
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SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2->InstalledSize;
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SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
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OptionalStrStart = (CHAR8 *)(SmbiosRecordL2 + 1);
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UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);
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