Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
292
Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
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292
Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
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/*++
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Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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VlvPlatformInit.c
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Abstract:
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This is the driver that initializes the Intel ValleyView.
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--*/
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#include "VlvPlatformInit.h"
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#include <Protocol/VlvPlatformPolicy.h>
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extern DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;
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UINT64 GTTMMADR;
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DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy;
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/**
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"Poll Status" for GT Readiness
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@param Base Base address of MMIO
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@param Offset MMIO Offset
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@param Mask Mask
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@param Result Value to wait for
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@retval None
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**/
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VOID
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PollGtReady_hang (
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UINT64 Base,
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UINT32 Offset,
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UINT32 Mask,
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UINT32 Result
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)
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{
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UINT32 GtStatus;
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//
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// Register read
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//
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GtStatus = MmioRead32 ((UINTN)Base+ Offset);
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while (((GtStatus & Mask) != Result)) {
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GtStatus = MmioRead32 ((UINTN)Base + Offset);
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}
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}
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/**
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Do Post GT PM Init Steps after VBIOS Initialization.
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@param Event A pointer to the Event that triggered the callback.
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@param Context A pointer to private data registered with the callback function.
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@retval EFI_SUCCESS GC_TODO
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**/
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EFI_STATUS
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EFIAPI
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PostPmInitCallBack (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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UINT64 OriginalGTTMMADR;
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UINT32 LoGTBaseAddress;
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UINT32 HiGTBaseAddress;
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//
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// Enable Bus Master, I/O and Memory access on 0:2:0
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//
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PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));
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//
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// only 32bit read/write is legal for device 0:2:0
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//
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OriginalGTTMMADR = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR));
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OriginalGTTMMADR = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);
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//
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// 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase
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// Program temporarily 32bits GTTMMADR for POST and S3 resume
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//
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LoGTBaseAddress = (UINT32) (GTTMMADR & 0xFFFFFFFF);
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HiGTBaseAddress = (UINT32) RShiftU64 ((GTTMMADR & 0xFFFFFFFF00000000), 32);
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S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
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S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
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//
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// Restore original GTTMMADR
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//
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LoGTBaseAddress = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);
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HiGTBaseAddress = (UINT32) RShiftU64 ((OriginalGTTMMADR & 0xFFFFFFFF00000000), 32);
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S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
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S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
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//
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// Lock the following registers, GGC, BDSM, BGSM
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//
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PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);
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PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);
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PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);
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gBS->CloseEvent (Event);
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//
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// Return final status
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//
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return EFI_SUCCESS;
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}
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/**
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Routine Description:
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Initialize GT Post Routines.
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@param ImageHandle Handle for the image of this driver
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@param DxePlatformSaPolicy SA DxePlatformPolicy protocol
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@retval EFI_SUCCESS GT POST initialization complete
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**/
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EFI_STATUS
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IgdPmHook (
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IN EFI_HANDLE ImageHandle,
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IN DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy
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)
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{
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EFI_EVENT mConOutEvent;
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VOID *gConOutNotifyReg;
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS MemBaseAddress;
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UINT32 LoGTBaseAddress;
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UINT32 HiGTBaseAddress;
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GTTMMADR = 0;
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Status = EFI_SUCCESS;
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//
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// If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,
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//
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if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_VID)) != 0xFFFF) {
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ASSERT (gDS!=NULL);
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//
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// Enable Bus Master, I/O and Memory access on 0:2:0
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//
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PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 | BIT0));
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//
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// Means Allocate 4MB for GTTMADDR
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//
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MemBaseAddress = 0x0ffffffff;
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Status = gDS->AllocateMemorySpace (
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EfiGcdAllocateMaxAddressSearchBottomUp,
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EfiGcdMemoryTypeMemoryMappedIo,
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GTT_MEM_ALIGN,
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GTTMMADR_SIZE_4MB,
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&MemBaseAddress,
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ImageHandle,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Program GT PM Settings if GTTMMADR allocation is Successful
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//
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GTTMMADR = (UINTN) MemBaseAddress;
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LoGTBaseAddress = (UINT32) (MemBaseAddress & 0xFFFFFFFF);
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HiGTBaseAddress = (UINT32) RShiftU64 ((MemBaseAddress & 0xFFFFFFFF00000000), 32);
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PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR), LoGTBaseAddress);
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PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR+4), HiGTBaseAddress);
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S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR));
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S3MmioRead32(IGD_R_GTTMMADR + 4);
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S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD));
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//
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// Do POST GT PM Init Steps after VBIOS Initialization in DoPostPmInitCallBack
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//
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Status = gBS->CreateEvent (
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EVT_NOTIFY_SIGNAL,
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TPL_CALLBACK,
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(EFI_EVENT_NOTIFY)PostPmInitCallBack,
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NULL,
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&mConOutEvent
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);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = gBS->RegisterProtocolNotify (
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&gEfiGraphicsOutputProtocolGuid,
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mConOutEvent,
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&gConOutNotifyReg
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);
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MmioWrite64 (IGD_R_GTTMMADR, 0);
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//
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// Free allocated resources
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//
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gDS->FreeMemorySpace (
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MemBaseAddress,
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GTTMMADR_SIZE_4MB
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);
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}
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return EFI_SUCCESS;
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}
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/**
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This is the standard EFI driver point that detects
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whether there is an ICH southbridge in the system
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and if so, initializes the chip.
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@param ImageHandle Handle for the image of this driver
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@param SystemTable Pointer to the EFI System Table
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@retval EFI_SUCCESS The function completed successfully
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**/
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EFI_STATUS
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EFIAPI
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VlvPlatformInitEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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Status = gBS->LocateProtocol (&gDxeVlvPlatformPolicyGuid, NULL, (void **)&DxePlatformSaPolicy);
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ASSERT_EFI_ERROR (Status);
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//
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// GtPostInit Initialization
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//
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DEBUG ((EFI_D_ERROR, "Initializing GT PowerManagement and other GT POST related\n"));
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IgdPmHook (ImageHandle, DxePlatformSaPolicy);
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