MdePkg: Add CPU RdRand access APIs for random number generation

Add AsmRdRand16/32/64 APIs for RdRand instruction access to generate
high-quality random number.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qin Long <qin.long@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18518 6f19259b-4bc3-4df7-8a09-765794883524

MdePkg/Library/BaseLib/BaseLib.inf

@@ -159,6 +159,7 @@
   Ia32/EnablePaging64.asm | MSFT
   Ia32/EnableCache.c | MSFT
   Ia32/DisableCache.c | MSFT
+  Ia32/RdRand.asm | MSFT
 
   Ia32/Wbinvd.asm | INTEL 
   Ia32/WriteMm7.asm | INTEL 
@@ -252,6 +253,7 @@
   Ia32/EnablePaging64.asm | INTEL
   Ia32/EnableCache.asm | INTEL
   Ia32/DisableCache.asm | INTEL
+  Ia32/RdRand.asm | INTEL
 
   Ia32/GccInline.c | GCC
   Ia32/Thunk16.nasm | GCC 
@@ -279,6 +281,7 @@
   Ia32/LShiftU64.S | GCC 
   Ia32/EnableCache.S | GCC
   Ia32/DisableCache.S | GCC
+  Ia32/RdRand.S | GCC
 
   Ia32/DivS64x64Remainder.c
   Ia32/InternalSwitchStack.c | MSFT
@@ -383,10 +386,12 @@
   X64/CpuBreakpoint.c | MSFT 
   X64/WriteMsr64.c | MSFT 
   X64/ReadMsr64.c | MSFT 
+  X64/RdRand.asm | MSFT
 
   X64/CpuBreakpoint.asm | INTEL 
   X64/WriteMsr64.asm | INTEL 
   X64/ReadMsr64.asm | INTEL 
+  X64/RdRand.asm | INTEL
 
   X64/Non-existing.c
   Math64.c
@@ -417,6 +422,7 @@
   X64/CpuIdEx.S | GCC 
   X64/EnableCache.S | GCC
   X64/DisableCache.S | GCC
+  X64/RdRand.S | GCC
   ChkStkGcc.c  | GCC 
 
 [Sources.IPF]