IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916 Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM. For backward compatibility, new INF are created for new modules. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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Chasel Chiu
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mergify[bot]
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5eeb088ad6
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IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm
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303
IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm
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;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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SECTION .text
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%include "PushPopRegsNasm.inc"
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;
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; Following are fixed PCDs
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;
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extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
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struc FSPM_UPD_COMMON_FSP24
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; FSP_UPD_HEADER {
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.FspUpdHeader: resd 8
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; }
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; FSPM_ARCH2_UPD {
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.Revision: resb 1
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.Reserved: resb 3
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.Length resd 1
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.StackBase: resq 1
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.StackSize: resq 1
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.BootLoaderTolumSize: resd 1
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.BootMode: resd 1
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.FspEventHandler resq 1
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.Reserved1: resb 24
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; }
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.size:
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endstruc
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;
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; Following functions will be provided in C
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;
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extern ASM_PFX(SecStartup)
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extern ASM_PFX(FspApiCommon)
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;
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; Following functions will be provided in PlatformSecLib
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;
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extern ASM_PFX(AsmGetFspBaseAddress)
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extern ASM_PFX(AsmGetFspInfoHeader)
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extern ASM_PFX(FspMultiPhaseMemInitApiHandler)
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STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose register * rax index
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FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
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FSP_HEADER_CFGREG_OFFSET EQU 24h
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;----------------------------------------------------------------------------
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; FspMemoryInit API
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;
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; This FSP API is called after TempRamInit and initializes the memory.
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspMemoryInitApi)
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ASM_PFX(FspMemoryInitApi):
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mov rax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex
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jmp ASM_PFX(FspApiCommon)
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;----------------------------------------------------------------------------
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; FspMultiPhaseMemoryInitApi API
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;
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; This FSP API provides multi-phase Memory initialization, which brings greater
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; modularity beyond the existing FspMemoryInit() API.
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; Increased modularity is achieved by adding an extra API to FSP-M.
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; This allows the bootloader to add board specific initialization steps throughout
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; the MemoryInit flow as needed.
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspMultiPhaseMemoryInitApi)
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ASM_PFX(FspMultiPhaseMemoryInitApi):
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mov rax, 8 ; FSP_API_INDEX.FspMultiPhaseMemInitApiIndex
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jmp ASM_PFX(FspApiCommon)
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;----------------------------------------------------------------------------
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; TempRamExitApi API
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;
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; This API tears down temporary RAM
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(TempRamExitApi)
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ASM_PFX(TempRamExitApi):
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mov rax, 4 ; FSP_API_INDEX.TempRamExitApiIndex
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jmp ASM_PFX(FspApiCommon)
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;----------------------------------------------------------------------------
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; FspApiCommonContinue API
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;
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; This is the FSP API common entry point to resume the FSP execution
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspApiCommonContinue)
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ASM_PFX(FspApiCommonContinue):
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;
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; Handle FspMultiPhaseMemoInitApiIndex API
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;
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push rdx ; Push a QWORD data for stack alignment
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cmp rax, 8 ; FspMultiPhaseMemInitApiIndex
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jnz NotMultiPhaseMemoryInitApi
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PUSHA_64
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mov rdx, rcx ; move ApiParam to rdx
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mov rcx, rax ; move ApiIdx to rcx
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sub rsp, 0x20 ; calling C function may need shadow space
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call ASM_PFX(FspMultiPhaseMemInitApiHandler)
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add rsp, 0x20 ; restore shadow space
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mov qword [rsp + STACK_SAVED_RAX_OFFSET], rax
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POPA_64
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add rsp, 0x08
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ret
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NotMultiPhaseMemoryInitApi:
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; Push RDX and RCX to form CONTEXT_STACK_64
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push rdx ; Push API Parameter2 on stack
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push rcx ; Push API Parameter1 on stack
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;
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; FspMemoryInit API setup the initial stack frame
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;
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;
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; Place holder to store the FspInfoHeader pointer
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;
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push rax
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;
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; Update the FspInfoHeader pointer
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;
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push rax
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call ASM_PFX(AsmGetFspInfoHeader)
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mov [rsp + 8], rax
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pop rax
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;
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; Create a Task Frame in the stack for the Boot Loader
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;
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pushfq
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cli
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PUSHA_64
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; Reserve 16 bytes for IDT save/restore
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sub rsp, 16
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sidt [rsp]
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; Get Stackbase and StackSize from FSPM_UPD Param
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mov rdx, rcx ; Put FSPM_UPD Param to rdx
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cmp rdx, 0
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jnz FspStackSetup
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; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null
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xchg rbx, rax
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call ASM_PFX(AsmGetFspInfoHeader)
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mov edx, [rax + FSP_HEADER_IMGBASE_OFFSET]
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add edx, [rax + FSP_HEADER_CFGREG_OFFSET]
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xchg rbx, rax
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FspStackSetup:
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mov cl, [rdx + FSPM_UPD_COMMON_FSP24.Revision]
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cmp cl, 3
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jae FspmUpdCommonFsp24
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mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER
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sub rsp, 0b8h
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ret
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FspmUpdCommonFsp24:
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;
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; StackBase = temp memory base, StackSize = temp memory size
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;
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mov rdi, [rdx + FSPM_UPD_COMMON_FSP24.StackBase]
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mov ecx, [rdx + FSPM_UPD_COMMON_FSP24.StackSize]
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;
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; Keep using bootloader stack if heap size % is 0
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;
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mov rbx, ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
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mov bl, BYTE [rbx]
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cmp bl, 0
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jz SkipStackSwitch
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;
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; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't equal 0
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;
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add rdi, rcx
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;
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; Switch to new FSP stack
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;
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xchg rdi, rsp ; Exchange rdi and rsp, rdi will be assigned to the current rsp pointer and rsp will be Stack base + Stack size
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SkipStackSwitch:
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;
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; If heap size % is 0:
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; EDI is FSPM_UPD_COMMON_FSP24.StackBase and will hold ESP later (boot loader stack pointer)
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; ECX is FSPM_UPD_COMMON_FSP24.StackSize
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; ESP is boot loader stack pointer (no stack switch)
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; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON_FSP24.StackBase later)
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;
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; If heap size % is not 0
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; EDI is boot loader stack pointer
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; ECX is FSPM_UPD_COMMON_FSP24.StackSize
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; ESP is new stack (FSPM_UPD_COMMON_FSP24.StackBase + FSPM_UPD_COMMON_FSP24.StackSize)
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; BL is NOT 0 to indicate stack has switched
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;
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cmp bl, 0
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jnz StackHasBeenSwitched
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mov rbx, rdi ; Put FSPM_UPD_COMMON_FSP24.StackBase to rbx as temp memory base
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mov rdi, rsp ; Put boot loader stack pointer to rdi
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jmp StackSetupDone
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StackHasBeenSwitched:
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mov rbx, rsp ; Put Stack base + Stack size in ebx
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sub rbx, rcx ; Stack base + Stack size - Stack size as temp memory base
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StackSetupDone:
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;
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; Per X64 calling convention, make sure RSP is 16-byte aligned.
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;
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mov rdx, rsp
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and rdx, 0fh
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sub rsp, rdx
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;
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; Pass the API Idx to SecStartup
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;
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push rax
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;
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; Pass the BootLoader stack to SecStartup
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;
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push rdi
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;
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; Pass BFV into the PEI Core
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; It uses relative address to calculate the actual boot FV base
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; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
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; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,
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; they are different. The code below can handle both cases.
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;
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call ASM_PFX(AsmGetFspBaseAddress)
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mov r8, rax
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;
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; Pass entry point of the PEI core
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;
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call ASM_PFX(AsmGetPeiCoreOffset)
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lea r9, [r8 + rax]
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;
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; Pass stack base and size into the PEI Core
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;
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mov rcx, rcx
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mov rdx, rbx
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;
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; Pass Control into the PEI Core
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; RCX = SizeOfRam, RDX = TempRamBase, R8 = BFV, R9 = PeiCoreEntry, Last 1 Stack = BL stack, Last 2 Stack = API index
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; According to X64 calling convention, caller has to allocate 32 bytes as a shadow store on call stack right before
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; calling the function.
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;
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sub rsp, 20h
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call ASM_PFX(SecStartup)
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add rsp, 20h
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exit:
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ret
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global ASM_PFX(FspPeiCoreEntryOff)
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ASM_PFX(FspPeiCoreEntryOff):
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;
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; This value will be patched by the build script
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;
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DD 0x12345678
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global ASM_PFX(AsmGetPeiCoreOffset)
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ASM_PFX(AsmGetPeiCoreOffset):
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push rbx
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mov rbx, ASM_PFX(FspPeiCoreEntryOff)
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mov eax, dword[ebx]
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pop rbx
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ret
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;----------------------------------------------------------------------------
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; TempRamInit API
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;
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; Empty function for WHOLEARCHIVE build option
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(TempRamInitApi)
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ASM_PFX(TempRamInitApi):
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jmp $
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ret
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;----------------------------------------------------------------------------
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; Module Entrypoint API
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;----------------------------------------------------------------------------
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global ASM_PFX(_ModuleEntryPoint)
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ASM_PFX(_ModuleEntryPoint):
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jmp $
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