UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 We scan the SMM code with ROPgadget. http://shell-storm.org/project/ROPgadget/ https://github.com/JonathanSalwan/ROPgadget/tree/master This tool reports the gadget in SMM driver. This patch enabled CET ShadowStack for X86 SMM. If CET is supported, SMM will enable CET ShadowStack. SMM CET will save the OS CET context at SmmEntry and restore OS CET context at SmmExit. Test: 1) test Intel internal platform (x64 only, CET enabled/disabled) Boot test: CET supported or not supported CPU on CET supported platform CET enabled/disabled PcdCpuSmmCetEnable enabled/disabled Single core/Multiple core PcdCpuSmmStackGuard enabled/disabled PcdCpuSmmProfileEnable enabled/disabled PcdCpuSmmStaticPageTable enabled/disabled CET exception test: #CF generated with PcdCpuSmmStackGuard enabled/disabled. Other exception test: #PF for normal stack overflow #PF for NX protection #PF for RO protection CET env test: Launch SMM in CET enabled/disabled environment (DXE) - no impact to DXE The test case can be found at https://github.com/jyao1/SecurityEx/tree/master/ControlFlowPkg 2) test ovmf (both IA32 and X64 SMM, CET disabled only) test OvmfIa32/Ovmf3264, with -D SMM_REQUIRE. qemu-system-x86_64.exe -machine q35,smm=on -smp 4 -serial file:serial.log -drive if=pflash,format=raw,unit=0,file=OVMF_CODE.fd,readonly=on -drive if=pflash,format=raw,unit=1,file=OVMF_VARS.fd QEMU emulator version 3.1.0 (v3.1.0-11736-g7a30e7adb0-dirty) 3) not tested IA32 CET enabled platform Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
@@ -1,7 +1,7 @@
|
||||
/** @file
|
||||
Library that provides CPU specific functions to support the PiSmmCpuDxeSmm module.
|
||||
|
||||
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
@@ -160,14 +160,33 @@ SmmCpuFeaturesGetSmiHandlerSize (
|
||||
than zero and is called by the CPU that was elected as monarch during System
|
||||
Management Mode initialization.
|
||||
|
||||
//
|
||||
// Append Shadow Stack after normal stack
|
||||
//
|
||||
// |= SmiStack
|
||||
// +--------------------------------------------------+---------------------------------------------------------------+
|
||||
// | Known Good Stack | Guard Page | SMM Stack | Known Good Shadow Stack | Guard Page | SMM Shadow Stack |
|
||||
// +--------------------------------------------------+---------------------------------------------------------------+
|
||||
// | |PcdCpuSmmStackSize| |PcdCpuSmmShadowStackSize|
|
||||
// |<-------------------- StackSize ----------------->|<------------------------- ShadowStackSize ------------------->|
|
||||
// | |
|
||||
// |<-------------------------------------------- Processor N ------------------------------------------------------->|
|
||||
// | low address (bottom) high address (top) |
|
||||
//
|
||||
|
||||
@param[in] CpuIndex The index of the CPU to install the custom SMI handler.
|
||||
The value must be between 0 and the NumberOfCpus field
|
||||
in the System Management System Table (SMST).
|
||||
@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
|
||||
@param[in] SmiStack The stack to use when an SMI is processed by the
|
||||
@param[in] SmiStack The bottom of stack to use when an SMI is processed by the
|
||||
the CPU specified by CpuIndex.
|
||||
@param[in] StackSize The size, in bytes, if the stack used when an SMI is
|
||||
processed by the CPU specified by CpuIndex.
|
||||
StackSize should be PcdCpuSmmStackSize, with 2 more pages
|
||||
if PcdCpuSmmStackGuard is true.
|
||||
If ShadowStack is enabled, the shadow stack is allocated
|
||||
after the normal Stack. The size is PcdCpuSmmShadowStackSize.
|
||||
with 2 more pages if PcdCpuSmmStackGuard is true.
|
||||
@param[in] GdtBase The base address of the GDT to use when an SMI is
|
||||
processed by the CPU specified by CpuIndex.
|
||||
@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
|
||||
|
Reference in New Issue
Block a user