Add in the 1st version of ECP.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2832 6f19259b-4bc3-4df7-8a09-765794883524

EdkCompatibilityPkg/Foundation/Include/Ebc/EfiBind.h

@@ -0,0 +1,129 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiBind.h
+
+Abstract:
+
+  Processor or compiler specific defines and types for EBC.
+
+--*/
+
+#ifndef _EFI_BIND_H_
+#define _EFI_BIND_H_
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+//
+// Disable warning that make it impossible to compile at /W3
+// This only works for Intel EBC Compiler tools
+//
+
+//
+// Disabling argument of type "TYPE **" is incompatible with parameter of type "void **"
+//
+#pragma warning ( disable : 167 )
+
+//
+// Disabling pointless comparison of unsigned integer with zero
+//
+#pragma warning ( disable : 186 )
+
+//
+// Disabling enumerated type mixed with another type
+//
+#pragma warning ( disable : 188 )
+
+//
+// Native integer types
+//
+typedef char                  int8_t;
+typedef unsigned char         uint8_t;
+
+typedef short                 int16_t;
+typedef unsigned short        uint16_t;
+
+typedef int                   int32_t;
+typedef unsigned int          uint32_t;
+
+typedef __int64               int64_t;
+typedef unsigned __int64      uint64_t;
+
+//
+// "long" type scales to the processor native size with EBC compiler
+//
+typedef long                  intn_t;
+typedef unsigned long         uintn_t;
+
+//
+// Scalable macro to set the most significant bit in a natural number
+//
+#define EFI_MAX_BIT           ((UINTN)0x01 << ((sizeof (char *) * 8) - 1))
+#define MAX_2_BITS            (EFI_MAX_BIT | (EFI_MAX_BIT >> 1))
+
+//
+// Maximum legal EBC address
+//
+#define EFI_MAX_ADDRESS   (UINTN)~0
+
+//
+//  Bad pointer value to use in check builds.
+//  if you see this value you are using uninitialized or free'ed data
+//
+#define EFI_BAD_POINTER          (UINTN)0xAFAFAFAFAFAFAFAF
+#define EFI_BAD_POINTER_AS_BYTE  (UINTN)0xAF
+
+//
+// _break() is an EBC compiler intrinsic function
+//
+extern 
+uint64_t 
+_break (
+  unsigned char BreakCode
+  );
+
+//
+// Macro to inject a break point in the code to assist debugging.
+//
+#define EFI_BREAKPOINT()  _break ( 3 )
+#define EFI_DEADLOOP()    while (TRUE)
+
+//
+// Memory Fence forces serialization, and is needed to support out of order
+//  memory transactions. The Memory Fence is mainly used to make sure IO
+//  transactions complete in a deterministic sequence, and to syncronize locks
+//  an other MP code. Currently no memory fencing is required.
+//
+#define MEMORY_FENCE()
+
+//
+// Some compilers don't support the forward reference construct:
+//  typedef struct XXXXX. The forward reference is required for 
+//  ANSI compatibility.
+//
+// The following macro provide a workaround for such cases.
+//
+
+
+#ifdef EFI_NO_INTERFACE_DECL
+  #define EFI_FORWARD_DECLARATION(x)
+#else
+  #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#endif
+
+
+#define _EFIAPI       
+
+#endif // ifndef _EFI_BIND_H_
+

EdkCompatibilityPkg/Foundation/Include/Ebc/EfiPeOptionalHeader.h

@@ -0,0 +1,46 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiPeOptionalHeader.h
+
+Abstract:
+  Defines the optional header in the PE image per the PE specification.  This
+  file must be included only from within EfiImage.h since 
+  EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
+  there.
+
+--*/
+
+#ifndef _EFI_PE_OPTIONAL_HEADER_H_
+#define _EFI_PE_OPTIONAL_HEADER_H_
+
+//
+// This is just to make sure you can cross compile with the EBC compiiler.
+// It does not make sense to have a PE loader coded in EBC. You need to 
+// understand the basic 
+//
+#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_EBC)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) 
+
+//
+// BUGBUG: Is this the correct magic for EBC?
+//
+#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC
+
+typedef EFI_IMAGE_OPTIONAL_HEADER32 EFI_IMAGE_OPTIONAL_HEADER;
+typedef EFI_IMAGE_NT_HEADERS32      EFI_IMAGE_NT_HEADERS;
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Ebc/TianoBind.h

@@ -0,0 +1,30 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  TianoBind.h
+
+Abstract:
+
+  Tiano's Processor or Compiler specific defines and types for EBC 
+  besides EfiBind.h.
+
+--*/
+
+#ifndef _TIANO_BIND_H_
+#define _TIANO_BIND_H_
+
+#include "EfiBind.h"
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/EfiCommon.h

@@ -0,0 +1,53 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+  
+  EfiCommon.h
+
+Abstract:
+
+--*/
+
+#ifndef _EFI_COMMON_H_
+#define _EFI_COMMON_H_
+
+#include "EfiBind.h"
+#include "EfiTypes.h"
+#include "EfiStdArg.h"
+#include "EfiError.h"
+
+//
+// Define macros for including Protocols and Guids.
+//
+#define EFI_STRINGIZE(a)            #a
+#define EFI_PROTOCOL_DEFINITION(a)  EFI_STRINGIZE (Protocol/a/a.h)
+#define EFI_GUID_DEFINITION(a)      EFI_STRINGIZE (Guid/a/a.h)
+
+//
+// These should be used to include protocols.  If they are followed,
+// intelligent build tools can be created to check dependencies at build
+// time.
+//
+#define EFI_PROTOCOL_PRODUCER(a)    EFI_PROTOCOL_DEFINITION (a)
+#define EFI_PROTOCOL_CONSUMER(a)    EFI_PROTOCOL_DEFINITION (a)
+#define EFI_PROTOCOL_DEPENDENCY(a)  EFI_PROTOCOL_DEFINITION (a)
+
+//
+// Mechanism to associate a short and long ascii string with a GUID.
+// For normal builds the strings are not included. A build utility
+// can be constructed to extract the strings and build a table. It may
+// be possible to add a build opption to automatically generate a GUID
+// string table for a GUID to string utility build.
+//
+#define EFI_GUID_STRING(guidpointer, shortstring, longstring)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/EfiDebug.h

@@ -0,0 +1,170 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiDebug.h
+
+Abstract:
+
+  EFI Debug macros. The work needs tobe done in library. The Debug
+  macros them selves are standard for all files, including the core.
+  
+  There needs to be code linked in that produces the following macros:
+  
+  EfiDebugAssert(file, linenumber, assertion string) - worker function for 
+      ASSERT. filename and line number of where this ASSERT() is located
+      is passed in along with the stringized version of the assertion.
+  
+  EfiDebugPrint - Worker function for debug print
+
+  _DEBUG_SET_MEM(address, length, value) - Set memory at address to value
+    for legnth bytes. This macro is used to initialzed uninitialized memory
+    or memory that is free'ed, so it will not be used by mistake. 
+
+--*/
+
+#ifndef _EFI_DEBUG_H_
+#define _EFI_DEBUG_H_
+
+#ifdef EFI_DEBUG
+
+  VOID
+  EfiDebugAssert (
+    IN CHAR8    *FileName,
+    IN INTN     LineNumber,
+    IN CHAR8    *Description
+    );
+
+  VOID
+  EfiDebugPrint (
+    IN  UINTN ErrorLevel,
+    IN  CHAR8 *Format,
+    ...
+    );
+
+  VOID
+  EfiDebugVPrint (
+    IN  UINTN   ErrorLevel,
+    IN  CHAR8   *Format,
+    IN  VA_LIST Marker
+    );
+
+  //
+  // Define macros for the above functions so we can make them go away
+  // in non-debug builds.
+  //
+  #define EFI_DEBUG_VPRINT(ErrorLevel, Format, Marker) \
+                      EfiDebugVPrint(ErrorLevel, Format, Marker) 
+
+  #define EFI_DEBUG_ASSERT(FileName, LineNumber, Description)  \
+                      EfiDebugAssert (FileName, LineNumber, Description)
+
+  #define _DEBUG_ASSERT(assertion)  \
+            EfiDebugAssert (__FILE__, __LINE__, #assertion)
+
+  #define _DEBUG(arg) DebugPrint arg
+
+  //
+  // Define ASSERT() macro, if assertion is FALSE trigger the ASSERT
+  //
+  #define ASSERT(assertion)   if(!(assertion))  \
+                                _DEBUG_ASSERT(assertion)
+    
+  #define ASSERT_LOCKED(l)    if(!(l)->Lock) _DEBUG_ASSERT(l not locked)
+
+  //
+  // DEBUG((DebugLevel, "format string", ...)) - if DebugLevel is active do 
+  //   the a debug print.
+  //
+  #define DEBUG(arg)        EfiDebugPrint arg
+
+  #define DEBUG_CODE(code)  code
+
+  #define CR(record, TYPE, field, signature)                    \
+            _CR(record, TYPE, field)->Signature != signature ?  \
+            (TYPE *) (_DEBUG_ASSERT("CR has Bad Signature"), record) :                        \
+            _CR(record, TYPE, field)
+
+  #define _DEBUG_SET_MEM(address, length, data) EfiCommonLibSetMem(address, length, data)
+
+  //
+  // Generate an ASSERT if the protocol specified by GUID is already installed on Handle.
+  // If Handle is NULL, then an ASSERT is generated if the protocol specified by GUID 
+  // is present anywhere in the handle database
+  //
+  #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid)               \
+    DEBUG_CODE ( {                                                      \
+    VOID  *Instance;                                                    \
+    if (Handle == NULL) {                                               \
+      ASSERT(EFI_ERROR(gBS->LocateProtocol (Guid, NULL, &Instance)));   \
+    } else {                                                            \
+      ASSERT(EFI_ERROR(gBS->HandleProtocol (Handle, Guid, &Instance))); \
+    } } ) 
+
+#else
+  #define ASSERT(a)               
+  #define ASSERT_LOCKED(l)    
+  #define DEBUG(arg) 
+  #define DEBUG_CODE(code)  
+  #define CR(Record, TYPE, Field, Signature)   \
+            _CR(Record, TYPE, Field)                           
+  #define _DEBUG_SET_MEM(address, length, data) 
+  #define EFI_DEBUG_VPRINT(ErrorLevel, Format, Marker) 
+  #define EFI_DEBUG_ASSERT(FileName, LineNumber, Description)  
+  #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid)
+#endif
+
+//
+// Generate an ASSERT if Status is an error code
+//
+//#define ASSERT_EFI_ERROR(status)  ASSERT(!EFI_ERROR(status))
+#define ASSERT_EFI_ERROR(status)  if (EFI_ERROR(status))                \
+    DEBUG_CODE ( {                                                      \
+      DEBUG((EFI_D_ERROR, "\nASSERT!Status = 0x%x Info :",status));     \
+      ASSERT(!EFI_ERROR(status));                                \
+    } ) 
+    
+#ifdef EFI_DEBUG_CLEAR_MEMORY
+  #define DEBUG_SET_MEMORY(address,length)  \
+            _DEBUG_SET_MEM(address, length, EFI_BAD_POINTER_AS_BYTE)
+#else
+  #define DEBUG_SET_MEMORY(address,length)
+#endif
+
+#define EFI_D_INIT        0x00000001          // Initialization style messages
+#define EFI_D_WARN        0x00000002          // Warnings
+#define EFI_D_LOAD        0x00000004          // Load events
+#define EFI_D_FS          0x00000008          // EFI File system
+#define EFI_D_POOL        0x00000010          // Alloc & Free's
+#define EFI_D_PAGE        0x00000020          // Alloc & Free's
+#define EFI_D_INFO        0x00000040          // Verbose
+#define EFI_D_VARIABLE    0x00000100          // Variable
+#define EFI_D_BM          0x00000400          // Boot Manager (BDS)
+#define EFI_D_BLKIO       0x00001000          // BlkIo Driver
+#define EFI_D_NET         0x00004000          // SNI Driver
+#define EFI_D_UNDI        0x00010000          // UNDI Driver
+#define EFI_D_LOADFILE    0x00020000          // UNDI Driver
+#define EFI_D_EVENT       0x00080000          // Event messages
+
+#define EFI_D_ERROR       0x80000000          // Error
+
+#define EFI_D_GENERIC (EFI_D_ERROR | EFI_D_INIT | EFI_D_WARN | EFI_D_INFO | \
+                        EFI_D_BLKIO | EFI_D_NET | EFI_D_UNDI )       
+
+#define EFI_D_INTRINSIC ( EFI_D_EVENT | EFI_D_POOL | EFI_D_PAGE | \
+                          EFI_D_BM | EFI_D_LOAD | EFI_D_VARIABLE )        
+
+#define EFI_D_RESERVED  (EFI_D_GENERIC | EFI_D_INTRINSIC)       
+
+#define EFI_DBUG_MASK   (EFI_D_ERROR)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/EfiDepex.h

@@ -0,0 +1,54 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+  EfiDepex.h
+
+Abstract:
+  This include file is only used in *.DXS files. Do not use this 
+  include file in normal DXE code.
+
+  Depex - Dependency Expresion
+
+  The BNF grammar is thus:
+     <depex>   ::= before GUID       
+                 | after GUID
+                 | SOR <bool>
+                 | <bool>            
+     <bool>    ::= <bool> and <term> 
+                 | <bool> or <term>  
+                 | <term>            
+     <term>    ::= not <factor>      
+                 | <factor>          
+     <factor>  ::= <bool>            
+                 | <boolval>         
+                 | <depinst>         
+                 | <termval>         
+     <boolval> ::= true              
+                 | false             
+     <depinst> ::= push GUID         
+     <termval> ::= end               
+
+--*/
+
+#ifndef _EFI_DEPEX_H_
+#define _EFI_DEPEX_H_
+
+#include "Tiano.h"
+
+//
+// The Depex grammer needs the string "TRUE" and "FALSE" we must
+// undo any pre-processor redefinitions
+//
+#undef TRUE
+#undef FALSE
+
+#endif

EdkCompatibilityPkg/Foundation/Include/EfiFlashMap.h

@@ -0,0 +1,128 @@
+/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiFlashMap.h
+
+Abstract:
+
+  Defines for the EFI Flash Map functionality
+  
+--*/
+
+#ifndef _EFI_FLASHMAP_H_
+#define _EFI_FLASHMAP_H_
+
+#include "PeiHob.h"
+
+//
+// Definition for flash map GUIDed HOBs
+//
+typedef UINT32  EFI_FLASH_AREA_ATTRIBUTES;
+
+#define EFI_FLASH_AREA_FV           0x0001
+#define EFI_FLASH_AREA_SUBFV        0x0002
+#define EFI_FLASH_AREA_MEMMAPPED_FV 0x0004
+#define EFI_FLASH_AREA_REQUIRED     0x0008
+#define EFI_FLASH_AREA_CORRUPT      0x0010
+
+typedef UINT8   EFI_FLASH_AREA_TYPE;
+
+#define EFI_FLASH_AREA_RECOVERY_BIOS  0x0   // Recovery code
+#define EFI_FLASH_AREA_MAIN_BIOS      0x1   // Regular BIOS code
+#define EFI_FLASH_AREA_PAL_B          0x2   // PAL-B
+#define EFI_FLASH_AREA_RESERVED_03    0x3   // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_RESERVED_04    0x4   // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_DMI_FRU        0x5   // DMI FRU information
+#define EFI_FLASH_AREA_OEM_BINARY     0x6   // OEM Binary Code/data
+#define EFI_FLASH_AREA_RESERVED_07    0x7   // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_RESERVED_08    0x8   // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_RESERVED_09    0x9   // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_RESERVED_0A    0x0a  // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_EFI_VARIABLES  0x0b  // EFI variables
+#define EFI_FLASH_AREA_MCA_LOG        0x0c  // MCA error log
+#define EFI_FLASH_AREA_SMBIOS_LOG     0x0d  // SMBIOS error log
+#define EFI_FLASH_AREA_FTW_BACKUP     0x0e  // A backup block during FTW operations
+#define EFI_FLASH_AREA_FTW_STATE      0x0f  // State information during FTW operations
+#define EFI_FLASH_AREA_UNUSED         0x0fd // Not used
+#define EFI_FLASH_AREA_GUID_DEFINED   0x0fe // Usage defined by a GUID
+#pragma pack(1)
+//
+// An individual sub-area Entry.
+// A single flash area may consist of  more than one sub-area.
+//
+typedef struct {
+  EFI_FLASH_AREA_ATTRIBUTES Attributes;
+  UINT32                    Reserved;
+  EFI_PHYSICAL_ADDRESS      Base;
+  EFI_PHYSICAL_ADDRESS      Length;
+  EFI_GUID                  FileSystem;
+} EFI_FLASH_SUBAREA_ENTRY;
+
+typedef struct {
+  UINT8                   Reserved[3];
+  EFI_FLASH_AREA_TYPE     AreaType;
+  EFI_GUID                AreaTypeGuid;
+  UINT32                  NumEntries;
+  EFI_FLASH_SUBAREA_ENTRY Entries[1];
+} EFI_FLASH_MAP_ENTRY_DATA;
+
+typedef struct {
+  UINT8                   Reserved[3];
+  EFI_FLASH_AREA_TYPE     AreaType;
+  EFI_GUID                AreaTypeGuid;
+  UINT32                  NumberOfEntries;
+  EFI_FLASH_SUBAREA_ENTRY Entries[1];
+  //
+  // Extended Hob data.
+  //
+  // VolumeId and FilePath indicating a unique file.
+  //
+  UINT32                  VolumeId;
+  CHAR16                  FilePath[256];
+  UINT32                  ActuralSize;
+  UINT32                  Offset;
+} EFI_FLASH_MAP_FS_ENTRY_DATA;
+
+typedef struct {
+  EFI_HOB_GENERIC_HEADER  Header;
+  EFI_GUID                Name;
+  UINT8                   Reserved[3];
+  EFI_FLASH_AREA_TYPE     AreaType;
+  EFI_GUID                AreaTypeGuid;
+  UINT32                  NumEntries;
+  EFI_FLASH_SUBAREA_ENTRY Entries[1];
+} EFI_HOB_FLASH_MAP_ENTRY_TYPE;
+
+//
+// Internal definitions
+//
+typedef struct {
+  UINT8                   Reserved[3];
+  EFI_FLASH_AREA_TYPE     AreaType;
+  EFI_GUID                AreaTypeGuid;
+  UINT32                  NumberOfEntries;
+  EFI_FLASH_SUBAREA_ENTRY SubAreaData;
+} EFI_FLASH_AREA_HOB_DATA;
+
+typedef struct {
+  UINTN                     Base;
+  UINTN                     Length;
+  EFI_FLASH_AREA_ATTRIBUTES Attributes;
+  EFI_FLASH_AREA_TYPE       AreaType;
+  UINT8                     Reserved[3];
+  EFI_GUID                  AreaTypeGuid;
+} EFI_FLASH_AREA_DATA;
+
+#pragma pack()
+
+#endif // #ifndef _EFI_FLASHMAP_H_

EdkCompatibilityPkg/Foundation/Include/EfiPci.h

@@ -0,0 +1,64 @@
+/*++
+
+Copyright (c) 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+    EfiPci.h
+
+Abstract:
+    Support for EFI PCI specification.
+
+Revision History
+
+--*/
+
+#ifndef _EFI_PCI_H_
+#define _EFI_PCI_H_
+
+//#include "pci22.h"
+//#include "pci23.h"
+//#include "pci30.h"
+
+#pragma pack(push, 1)
+
+typedef struct {
+  UINT8 Register;
+  UINT8 Function;
+  UINT8 Device;
+  UINT8 Bus;
+  UINT8 Reserved[4];
+} DEFIO_PCI_ADDR;
+
+#define EFI_ROOT_BRIDGE_LIST                            'eprb'
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1
+
+typedef struct {
+  UINT16  Signature;    // 0xaa55
+  UINT16  InitializationSize;
+  UINT32  EfiSignature; // 0x0EF1
+  UINT16  EfiSubsystem;
+  UINT16  EfiMachineType;
+  UINT16  CompressionType;
+  UINT8   Reserved[8];
+  UINT16  EfiImageHeaderOffset;
+  UINT16  PcirOffset;
+} EFI_PCI_EXPANSION_ROM_HEADER;
+
+typedef union {
+  UINT8                           *Raw;
+  PCI_EXPANSION_ROM_HEADER        *Generic;
+  EFI_PCI_EXPANSION_ROM_HEADER    *Efi;
+  EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
+} EFI_PCI_ROM_HEADER;
+
+#pragma pack(pop)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/EfiPerf.h

@@ -0,0 +1,158 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+ EfiPerf.h
+
+Abstract:
+ EfiPerf.h provides performance primitive for the DXE and Shell phase
+
+ 
+--*/
+
+#ifndef _EFI_PERF_H_
+#define _EFI_PERF_H_
+
+#include EFI_PROTOCOL_DEFINITION (Performance)
+
+EFI_STATUS
+InitializePerformanceInfrastructure (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable,
+  IN UINT64             Ticker
+  )
+/*++
+
+Routine Description:
+
+  TODO: Add function description
+
+Arguments:
+
+  ImageHandle - TODO: add argument description
+  SystemTable - TODO: add argument description
+  Ticker      - TODO: add argument description
+
+Returns:
+
+  TODO: add return values
+
+--*/
+;
+
+EFI_STATUS
+EndMeasure (
+  IN EFI_HANDLE       Handle,
+  IN UINT16           *Token,
+  IN UINT16           *Host,
+  IN UINT64           Ticker
+  )
+/*++
+
+Routine Description:
+
+  TODO: Add function description
+
+Arguments:
+
+  Handle  - TODO: add argument description
+  Token   - TODO: add argument description
+  Host    - TODO: add argument description
+  Ticker  - TODO: add argument description
+
+Returns:
+
+  TODO: add return values
+
+--*/
+;
+
+EFI_STATUS
+StartMeasure (
+  IN EFI_HANDLE       Handle,
+  IN UINT16           *Token,
+  IN UINT16           *Host,
+  IN UINT64           Ticker
+  )
+/*++
+
+Routine Description:
+
+  TODO: Add function description
+
+Arguments:
+
+  Handle  - TODO: add argument description
+  Token   - TODO: add argument description
+  Host    - TODO: add argument description
+  Ticker  - TODO: add argument description
+
+Returns:
+
+  TODO: add return values
+
+--*/
+;
+
+EFI_STATUS
+UpdateMeasure (
+  IN EFI_HANDLE      Handle,
+  IN UINT16          *Token,
+  IN UINT16          *Host,
+  IN EFI_HANDLE      HandleNew,
+  IN UINT16          *TokenNew,
+  IN UINT16          *HostNew
+  )
+/*++
+
+Routine Description:
+
+  TODO: Add function description
+
+Arguments:
+
+  Handle    - TODO: add argument description
+  Token     - TODO: add argument description
+  Host      - TODO: add argument description
+  HandleNew - TODO: add argument description
+  TokenNew  - TODO: add argument description
+  HostNew   - TODO: add argument description
+
+Returns:
+
+  TODO: add return values
+
+--*/
+;
+
+#ifdef EFI_DXE_PERFORMANCE
+#define PERF_ENABLE(handle, table, ticker)      InitializePerformanceInfrastructure (handle, table, ticker)
+#define PERF_START(handle, token, host, ticker) StartMeasure (handle, token, host, ticker)
+#define PERF_END(handle, token, host, ticker)   EndMeasure (handle, token, host, ticker)
+#define PERF_UPDATE(handle, token, host, handlenew, tokennew, hostnew) \
+  UpdateMeasure (handle, \
+                 token, \
+                 host, \
+                 handlenew, \
+                 tokennew, \
+                 hostnew \
+      )
+#define PERF_CODE(code) code
+#else
+#define PERF_ENABLE(handle, table, ticker)
+#define PERF_START(handle, token, host, ticker)
+#define PERF_END(handle, token, host, ticker)
+#define PERF_UPDATE(handle, token, host, handlenew, tokennew, hostnew)
+#define PERF_CODE(code)
+#endif
+
+#endif

EdkCompatibilityPkg/Foundation/Include/EfiSpec.h

@@ -0,0 +1,51 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiSpec.h
+
+Abstract:
+
+  EFI master include file.
+
+  This is the main include file for EFI components. There should be
+  no defines or macros added to this file, other than the EFI version 
+  information already in this file.
+
+  Don't add include files to the list for convenience, only add things
+  that are architectural. Don't add Protocols or GUID include files here
+
+--*/
+
+#ifndef _EFI_SPEC_H_
+#define _EFI_SPEC_H_
+
+#include "EfiCommon.h"
+#include "EfiApi.h"
+#include "EfiDevicePath.h"
+
+//
+// Check to make sure EFI_SPECIFICATION_VERSION and TIANO_RELEASE_VERSION are defined.
+//
+#if !defined(EFI_SPECIFICATION_VERSION)
+  #error EFI_SPECIFICATION_VERSION not defined
+#elif !defined(TIANO_RELEASE_VERSION)
+  #error TIANO_RELEASE_VERSION not defined
+#elif (TIANO_RELEASE_VERSION == 0)
+//
+// UEFI mode with no Tiano extensions is legal
+//
+#elif ((TIANO_RELEASE_VERSION < 0x00080005) && (EFI_SPECIFICATION_VERSION >= 0x00020000))
+  #error Illegal combination of EFI_SPECIFICATION_VERSION and TIANO_RELEASE_VERSION versions
+#endif
+
+#endif

EdkCompatibilityPkg/Foundation/Include/EfiStdArg.h

@@ -0,0 +1,75 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiStdArg.h
+
+Abstract:
+
+  Support for variable length argument lists using the ANSI standard.
+  
+  Since we are using the ANSI standard we used the standard nameing and
+  did not folow the coding convention
+
+  VA_LIST  - typedef for argument list.
+  VA_START (VA_LIST Marker, argument before the ...) - Init Marker for use.
+  VA_END (VA_LIST Marker) - Clear Marker
+  VA_ARG (VA_LIST Marker, var arg size) - Use Marker to get an argumnet from
+    the ... list. You must know the size and pass it in this macro.
+
+  example:
+
+  UINTN
+  ExampleVarArg (
+    IN UINTN  NumberOfArgs,
+    ...
+    )
+  {
+    VA_LIST Marker;
+    UINTN   Index;
+    UINTN   Result;
+
+    //
+    // Initialize the Marker
+    //
+    VA_START (Marker, NumberOfArgs);
+    for (Index = 0, Result = 0; Index < NumberOfArgs; Index++) {
+      //
+      // The ... list is a series of UINTN values, so average them up.
+      //
+      Result += VA_ARG (Marker, UINTN);
+    }
+
+    VA_END (Marker);
+    return Result
+  }
+
+--*/
+
+#ifndef _EFISTDARG_H_
+#define _EFISTDARG_H_
+
+#define _EFI_INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
+
+//
+// Also support coding convention rules for var arg macros
+//
+#ifndef VA_START
+
+typedef CHAR8 *VA_LIST;
+#define VA_START(ap, v) (ap = (VA_LIST) & (v) + _EFI_INT_SIZE_OF (v))
+#define VA_ARG(ap, t)   (*(t *) ((ap += _EFI_INT_SIZE_OF (t)) - _EFI_INT_SIZE_OF (t)))
+#define VA_END(ap)      (ap = (VA_LIST) 0)
+
+#endif
+
+#endif

EdkCompatibilityPkg/Foundation/Include/EfiTpm.h

@@ -0,0 +1,144 @@
+/*++
+
+Copyright (c) 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiTpm.h
+
+Abstract:
+
+  EFI definition according to TCG_EFI_Platform_1_20_Final
+
+  See http://trustedcomputinggroup.org for latest specification updates
+
+--*/
+
+#ifndef _EFI_TPM_H_
+#define _EFI_TPM_H_
+
+#include <Tiano.h>
+
+//
+// The start of TPM return codes
+//
+#define TPM_BASE                    (EFI_MAX_BIT + (EFI_MAX_BIT >> 1))
+#include <IndustryStandard/Tpm12.h>
+
+//
+// Standard event types
+//
+#define EV_POST_CODE                ((TCG_EVENTTYPE) 0x00000001)
+#define EV_SEPARATOR                ((TCG_EVENTTYPE) 0x00000004)
+#define EV_S_CRTM_CONTENTS          ((TCG_EVENTTYPE) 0x00000007)
+#define EV_S_CRTM_VERSION           ((TCG_EVENTTYPE) 0x00000008)
+
+//
+// EFI specific event types
+//
+#define EV_EFI_EVENT_BASE                   ((TCG_EVENTTYPE) 0x80000000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG       (EV_EFI_EVENT_BASE + 1)
+#define EV_EFI_VARIABLE_BOOT                (EV_EFI_EVENT_BASE + 2)
+#define EV_EFI_BOOT_SERVICES_APPLICATION    (EV_EFI_EVENT_BASE + 3)
+#define EV_EFI_BOOT_SERVICES_DRIVER         (EV_EFI_EVENT_BASE + 4)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER      (EV_EFI_EVENT_BASE + 5)
+#define EV_EFI_GPT_EVENT                    (EV_EFI_EVENT_BASE + 6)
+#define EV_EFI_ACTION                       (EV_EFI_EVENT_BASE + 7)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB       (EV_EFI_EVENT_BASE + 8)
+#define EV_EFI_HANDOFF_TABLES               (EV_EFI_EVENT_BASE + 9)
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (push, 1)
+
+typedef UINT32                     TCG_EVENTTYPE;
+
+#define TCG_DIGEST                 TPM_DIGEST
+#define TCG_PCRINDEX               TPM_PCRINDEX
+
+//
+// TCG_PCR_EVENT
+//
+typedef struct tdTCG_PCR_EVENT {
+  TCG_PCRINDEX                      PCRIndex;  // PCRIndex event extended to
+  TCG_EVENTTYPE                     EventType; // TCG EFI event type
+  TCG_DIGEST                        Digest;    // Value extended into PCRIndex
+  UINT32                            EventSize; // Size of the event data
+  UINT8                             Event[1];  // The event data
+} TCG_PCR_EVENT;
+
+//
+// TCG_PCR_EVENT_HDR
+//
+typedef struct tdTCG_PCR_EVENT_HDR {
+  TCG_PCRINDEX                      PCRIndex;
+  TCG_EVENTTYPE                     EventType;
+  TCG_DIGEST                        Digest;
+  UINT32                            EventSize;
+} TCG_PCR_EVENT_HDR;
+
+//
+// EFI_PLATFORM_FIRMWARE_BLOB
+//
+// BlobLength should be of type UINTN but we use UINT64 here
+// because PEI is 32-bit while DXE is 64-bit on x64 platforms
+//
+typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB {
+  EFI_PHYSICAL_ADDRESS              BlobBase;
+  UINT64                            BlobLength;
+} EFI_PLATFORM_FIRMWARE_BLOB;
+
+//
+// EFI_IMAGE_LOAD_EVENT
+//
+// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION,
+// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER
+//
+typedef struct tdEFI_IMAGE_LOAD_EVENT {
+  EFI_PHYSICAL_ADDRESS              ImageLocationInMemory;
+  UINTN                             ImageLengthInMemory;
+  UINTN                             ImageLinkTimeAddress;
+  UINTN                             LengthOfDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL          DevicePath[1];
+} EFI_IMAGE_LOAD_EVENT;
+
+//
+// EFI_HANDOFF_TABLE_POINTERS
+//
+// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate
+// the measurement of given configuration tables.
+//
+typedef struct tdEFI_HANDOFF_TABLE_POINTERS {
+  UINTN 	                    NumberOfTables;
+  EFI_CONFIGURATION_TABLE           TableEntry[1];
+} EFI_HANDOFF_TABLE_POINTERS;
+
+//
+// EFI_VARIABLE_DATA
+//
+// This structure serves as the header for measuring variables. The name of the
+// variable (in Unicode format) should immediately follow, then the variable
+// data.
+//
+typedef struct tdEFI_VARIABLE_DATA {
+  EFI_GUID                          VariableName;
+  UINTN                             UnicodeNameLength;
+  UINTN                             VariableDataLength;
+  CHAR16                            UnicodeName[1];
+  INT8                              VariableData[1];  // Driver or platform-specific data
+} EFI_VARIABLE_DATA;
+
+//
+// Restore original structure alignment
+//
+#pragma pack (pop)
+
+#endif  // _EFI_TPM_H_

EdkCompatibilityPkg/Foundation/Include/EfiVariable.h

@@ -0,0 +1,85 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiVariable.h
+  
+Abstract:
+  
+  Header file for EFI Variable Services
+
+--*/
+
+#ifndef _EFI_VARIABLE_H_
+#define _EFI_VARIABLE_H_
+
+#define VARIABLE_STORE_SIGNATURE  EFI_SIGNATURE_32 ('$', 'V', 'S', 'S')
+
+#define MAX_VARIABLE_SIZE         1024
+
+//
+// Enlarges the hardware error record maximum variable size to 32K bytes
+//
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+#define MAX_HARDWARE_ERROR_VARIABLE_SIZE 0x8000
+#endif
+
+#define VARIABLE_DATA             0x55AA
+
+//
+// Variable Store Header flags
+//
+#define VARIABLE_STORE_FORMATTED  0x5a
+#define VARIABLE_STORE_HEALTHY    0xfe
+
+//
+// Variable Store Status
+//
+typedef enum {
+  EfiRaw,
+  EfiValid,
+  EfiInvalid,
+  EfiUnknown
+} VARIABLE_STORE_STATUS;
+
+//
+// Variable State flags
+//
+#define VAR_IN_DELETED_TRANSITION     0xfe  // Variable is in obsolete transistion
+#define VAR_DELETED                   0xfd  // Variable is obsolete
+#define VAR_ADDED                     0x7f  // Variable has been completely added
+#define IS_VARIABLE_STATE(_c, _Mask)  (BOOLEAN) (((~_c) & (~_Mask)) != 0)
+
+#pragma pack(1)
+
+typedef struct {
+  UINT32  Signature;
+  UINT32  Size;
+  UINT8   Format;
+  UINT8   State;
+  UINT16  Reserved;
+  UINT32  Reserved1;
+} VARIABLE_STORE_HEADER;
+
+typedef struct {
+  UINT16    StartId;
+  UINT8     State;
+  UINT8     Reserved;
+  UINT32    Attributes;
+  UINT32    NameSize;
+  UINT32    DataSize;
+  EFI_GUID  VendorGuid;
+} VARIABLE_HEADER;
+
+#pragma pack()
+
+#endif // _EFI_VARIABLE_H_

EdkCompatibilityPkg/Foundation/Include/EfiWorkingBlockHeader.h

@@ -0,0 +1,47 @@
+/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiWorkingBlockHeader.h
+
+Abstract:
+
+  Defines data structure that is the headers found at the runtime 
+  updatable firmware volumes, such as the FileSystemGuid of the 
+  working block, the header structure of the variable block, FTW
+  working block, or event log block.
+
+--*/
+
+#ifndef _EFI_WORKING_BLOCK_HEADER_H_
+#define _EFI_WORKING_BLOCK_HEADER_H_
+
+//
+// EFI Fault tolerant working block header
+// The header is immediately followed by the write queue.
+//
+typedef struct {
+  EFI_GUID  Signature;
+  UINT32    Crc;
+  UINT8     WorkingBlockValid : 1;
+  UINT8     WorkingBlockInvalid : 1;
+#define WORKING_BLOCK_VALID   0x1
+#define WORKING_BLOCK_INVALID 0x2
+  UINT8     Reserved : 6;
+  UINT8     Reserved3[3];
+  UINT64    WriteQueueSize;
+  //
+  // UINT8                WriteQueue[WriteQueueSize];
+  //
+} EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER;
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Ia32/EfiBind.h

@@ -0,0 +1,269 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiBind.h
+
+Abstract:
+
+  Processor or Compiler specific defines and types for IA-32.
+  We are using the ANSI C 2000 _t type definitions for basic types.
+  This it technically a violation of the coding standard, but they
+  are used to make EfiTypes.h portable. Code other than EfiTypes.h
+  should never use any ANSI C 2000 _t integer types.
+
+--*/
+
+#ifndef _EFI_BIND_H_
+#define _EFI_BIND_H_
+
+#ifdef EFI_DEBUG
+
+#ifdef EFI_NT_EMULATOR
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)                  \
+          EFI_STATUS                                          \
+          EFIAPI                                              \
+          InitFunction (                                      \
+            EFI_HANDLE        ImageHandle,                    \
+            EFI_SYSTEM_TABLE  *SystemTable                    \
+            );                                                \
+                                                              \
+          UINTN                                               \
+          __stdcall                                           \
+          _DllMainCRTStartup (                                \
+              UINTN    Inst,                                  \
+              UINTN    reason_for_call,                       \
+              VOID    *rserved                                \
+              )                                               \
+          {                                                   \
+              return 1;                                       \
+          }                                                   \
+                                                              \
+          EFI_STATUS                                                 \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+              VOID *ImageHandle,                              \
+              VOID *SystemTable                               \
+              )                                               \
+          {                                                   \
+              return InitFunction(ImageHandle, SystemTable);  \
+          }
+
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+#else
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)                  
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+#endif
+
+#else
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)                  
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+#endif
+
+
+
+
+
+//
+// Make sure we are useing the correct packing rules per EFI specification
+//
+#pragma pack()
+
+#if _MSC_EXTENSIONS
+
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft* tools
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// Int64ShllMod32 unreferenced inline function
+//
+#pragma warning ( disable : 4514 )
+
+//
+// Unreferenced formal parameter - We are object oriented, so we pass This even
+//  if we  don't need them.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// This warning is caused by empty (after preprocessing) souce file.
+//
+#pragma warning ( disable : 4206 )
+
+
+#endif
+
+
+#if (__STDC_VERSION__ < 199901L)
+  //
+  // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
+  //
+ 
+  #if _MSC_EXTENSIONS 
+    
+    //
+    // use Microsoft* C complier dependent interger width types 
+    //
+    typedef unsigned __int64    uint64_t;
+    typedef __int64             int64_t;
+    typedef unsigned __int32    uint32_t;
+    typedef __int32             int32_t;
+    typedef unsigned short      uint16_t;
+    typedef short               int16_t;
+    typedef unsigned char       uint8_t;
+    typedef char                int8_t;
+  #else
+
+    //
+    // Assume standard IA-32 alignment. 
+    // BugBug: Need to check portability of long long
+    //
+    typedef unsigned long long  uint64_t;
+    typedef long long           int64_t;
+    typedef unsigned int        uint32_t;
+    typedef int                 int32_t;
+    typedef unsigned short      uint16_t;
+    typedef short               int16_t;
+    typedef unsigned char       uint8_t;
+    typedef char                int8_t;
+  #endif
+#else
+  //
+  // Use ANSI C 2000 stdint.h integer width declarations
+  //
+  #include "stdint.h"
+#endif
+
+//
+// Native integer size in stdint.h
+//
+typedef uint32_t  uintn_t;
+typedef int32_t   intn_t;
+
+//
+// Processor specific defines
+//
+#define EFI_MAX_BIT       0x80000000
+#define MAX_2_BITS        0xC0000000
+
+//
+// Maximum legal IA-32 address
+//
+#define EFI_MAX_ADDRESS   0xFFFFFFFF
+
+//
+//  Bad pointer value to use in check builds.
+//  if you see this value you are using uninitialized or free'ed data
+//
+#define EFI_BAD_POINTER          0xAFAFAFAF
+#define EFI_BAD_POINTER_AS_BYTE  0xAF
+
+//
+// Inject a break point in the code to assist debugging for NT Emulation Environment
+// For real hardware, just put in a halt loop. Don't do a while(1) because the
+// compiler will optimize away the rest of the function following, so that you run out in
+// the weeds if you skip over it with a debugger.
+//
+#define EFI_BREAKPOINT()  __asm { int 3 }
+#define EFI_DEADLOOP()    { volatile UINTN __iii; __iii = 1; while (__iii); }
+
+//
+// Memory Fence forces serialization, and is needed to support out of order
+//  memory transactions. The Memory Fence is mainly used to make sure IO
+//  transactions complete in a deterministic sequence, and to syncronize locks
+//  an other MP code. Currently no memory fencing is required.
+//
+#define MEMORY_FENCE()
+
+//
+// Some compilers don't support the forward reference construct:
+//  typedef struct XXXXX. The forward reference is required for 
+//  ANSI compatibility.
+//
+// The following macro provide a workaround for such cases.
+//
+
+
+#ifdef EFI_NO_INTERFACE_DECL
+  #define EFI_FORWARD_DECLARATION(x)
+#else
+  #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#endif
+
+
+//
+// Some C compilers optimize the calling conventions to increase performance.
+// _EFIAPI is used to make all public APIs follow the standard C calling 
+// convention.
+//
+#if _MSC_EXTENSIONS
+  //
+  // Microsoft* compiler requires _EFIAPI useage, __cdecl is Microsoft* specific C.
+  // 
+
+  #define _EFIAPI __cdecl  
+#else
+  #define _EFIAPI       
+#endif
+
+
+#ifdef _EFI_WINNT
+
+  #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( disable : 4142 )
+
+  #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( default : 4142 )
+#else
+
+  #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( disable : 4068 )
+
+  #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( default : 4068 )
+
+#endif
+
+
+
+#endif
+

EdkCompatibilityPkg/Foundation/Include/Ia32/EfiPeOptionalHeader.h

@@ -0,0 +1,38 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiPeOptionalHeader.h
+
+Abstract:
+  Defines the optional header in the PE image per the PE specification.  This
+  file must be included only from within EfiImage.h since 
+  EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
+  there.
+
+--*/
+
+#ifndef _EFI_PE_OPTIONAL_HEADER_H_
+#define _EFI_PE_OPTIONAL_HEADER_H_
+
+#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_IA32)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+  (((Machine) == EFI_IMAGE_MACHINE_IA32) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64) 
+
+#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC
+typedef EFI_IMAGE_OPTIONAL_HEADER32 EFI_IMAGE_OPTIONAL_HEADER;
+typedef EFI_IMAGE_NT_HEADERS32      EFI_IMAGE_NT_HEADERS;
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Ia32/TianoBind.h

@@ -0,0 +1,102 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  TianoBind.h
+
+Abstract:
+
+  Tiano's Processor or Compiler specific defines and types for IA-32 
+  besides EfiBind.h.
+
+--*/
+
+#ifndef _TIANO_BIND_H_
+#define _TIANO_BIND_H_
+
+#include "EfiBind.h"
+
+#ifdef EFI_DEBUG
+
+#ifdef EFI_NT_EMULATOR
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)                     \
+					VOID                                                \
+					EFIAPI                                              \
+					InitFunction (                                      \
+  					IN  VOID *HobStart																\
+  				);																									\
+																															\
+          UINTN                                               \
+          __stdcall                                           \
+          _DllMainCRTStartup (                                \
+              UINTN    Inst,                                  \
+              UINTN    reason_for_call,                       \
+              VOID    *rserved                                \
+              )                                               \
+          {                                                   \
+              return 1;                                       \
+          }                                                   \
+                                                              \
+          VOID                                                \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+              VOID *Hob                                       \
+              )                                               \
+          {                                                   \
+              InitFunction(Hob);                              \
+          }
+
+
+
+
+#define EFI_SMI_HANDLER_ENTRY_POINT(InitFunction)             \
+          UINTN                                               \
+          __stdcall                                           \
+          _DllMainCRTStartup (                                \
+              UINTN    Inst,                                  \
+              UINTN    reason_for_call,                       \
+              VOID    *rserved                                \
+              )                                               \
+          {                                                   \
+              return 1;                                       \
+          }                                                   \
+                                                              \
+          EFI_STATUS                                                 \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+              VOID  *ImageHandle,                             \
+              VOID  *Smst,                                    \
+              VOID  *CommunicationBuffer,                     \
+              UINTN *SourceSize                               \
+              )                                               \
+          {                                                   \
+              return InitFunction(ImageHandle, Smst, CommunicationBuffer, SourceSize);  \
+          }
+
+#else
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+#define EFI_SMI_HANDLER_ENTRY_POINT(InitFunction)
+
+#endif
+
+#else
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+#define EFI_SMI_HANDLER_ENTRY_POINT(InitFunction)
+
+#endif
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi.h

@@ -0,0 +1,31 @@
+/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  Acpi.h
+
+Abstract:
+
+  This file contains some basic ACPI definitions that are consumed by drivers
+  that do not care about ACPI versions.
+
+--*/
+
+#ifndef _ACPI_H_
+#define _ACPI_H_
+
+#include "AcpiCommon.h"
+#include "Acpi1_0.h"
+#include "Acpi2_0.h"
+#include "Acpi3_0.h"
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi1_0.h

@@ -0,0 +1,299 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+  
+    Acpi1_0.h
+
+Abstract:
+
+  ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
+
+--*/
+
+#ifndef _ACPI_1_0_H_
+#define _ACPI_1_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI 1.0b table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Reserved;
+  UINT32  RsdtAddress;
+} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      FirmwareCtrl;
+  UINT32                      Dsdt;
+  UINT8                       IntModel;
+  UINT8                       Reserved1;
+  UINT16                      SciInt;
+  UINT32                      SmiCmd;
+  UINT8                       AcpiEnable;
+  UINT8                       AcpiDisable;
+  UINT8                       S4BiosReq;
+  UINT8                       Reserved2;
+  UINT32                      Pm1aEvtBlk;
+  UINT32                      Pm1bEvtBlk;
+  UINT32                      Pm1aCntBlk;
+  UINT32                      Pm1bCntBlk;
+  UINT32                      Pm2CntBlk;
+  UINT32                      PmTmrBlk;
+  UINT32                      Gpe0Blk;
+  UINT32                      Gpe1Blk;
+  UINT8                       Pm1EvtLen;
+  UINT8                       Pm1CntLen;
+  UINT8                       Pm2CntLen;
+  UINT8                       PmTmLen;
+  UINT8                       Gpe0BlkLen;
+  UINT8                       Gpe1BlkLen;
+  UINT8                       Gpe1Base;
+  UINT8                       Reserved3;
+  UINT16                      PLvl2Lat;
+  UINT16                      PLvl3Lat;
+  UINT16                      FlushSize;
+  UINT16                      FlushStride;
+  UINT8                       DutyOffset;
+  UINT8                       DutyWidth;
+  UINT8                       DayAlrm;
+  UINT8                       MonAlrm;
+  UINT8                       Century;
+  UINT8                       Reserved4;
+  UINT8                       Reserved5;
+  UINT8                       Reserved6;
+  UINT32                      Flags;
+} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x01
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_WBINVD       (1 << 0)
+#define EFI_ACPI_1_0_WBINVD_FLUSH (1 << 1)
+#define EFI_ACPI_1_0_PROC_C1      (1 << 2)
+#define EFI_ACPI_1_0_P_LVL2_UP    (1 << 3)
+#define EFI_ACPI_1_0_PWR_BUTTON   (1 << 4)
+#define EFI_ACPI_1_0_SLP_BUTTON   (1 << 5)
+#define EFI_ACPI_1_0_FIX_RTC      (1 << 6)
+#define EFI_ACPI_1_0_RTC_S4       (1 << 7)
+#define EFI_ACPI_1_0_TMR_VAL_EXT  (1 << 8)
+#define EFI_ACPI_1_0_DCK_CAP      (1 << 9)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT8   Reserved[40];
+} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_S4BIOS_F (1 << 0)
+
+//
+// Multiple APIC Description Table header definition.  The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_PCAT_COMPAT  (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_1_0_IO_APIC                        0x01
+#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_1_0_LOCAL_APIC_NMI                 0x04
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  SystemVectorBase;
+} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterruptVector;
+  UINT16  Flags;
+} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterruptVector;
+} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicInti;
+} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  0x2052545020445352
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_1_0_APIC_SIGNATURE 0x43495041
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445344
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  0x53434146
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  0x54534253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi2_0.h

@@ -0,0 +1,513 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  Acpi2_0.h
+
+Abstract:
+
+  ACPI 2.0 definitions from the ACPI Specification, revision 2.0
+
+--*/
+
+#ifndef _ACPI_2_0_H_
+#define _ACPI_2_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI Specification Revision
+//
+#define EFI_ACPI_2_0_REVISION 0x02
+
+//
+// ACPI 2.0 Generic Address Space definition
+//
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   Reserved;
+  UINT64  Address;
+} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_2_0_SYSTEM_MEMORY              0
+#define EFI_ACPI_2_0_SYSTEM_IO                  1
+#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_2_0_SMBUS                      4
+#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE  0x7F
+
+//
+// ACPI 2.0 table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
+
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_2_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT64 table pointers.
+//
+//
+// XSDT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT8                                   Reserved2[3];
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x03
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)
+#define EFI_ACPI_2_0_8042           (1 << 1)
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_WBINVD         (1 << 0)
+#define EFI_ACPI_2_0_WBINVD_FLUSH   (1 << 1)
+#define EFI_ACPI_2_0_PROC_C1        (1 << 2)
+#define EFI_ACPI_2_0_P_LVL2_UP      (1 << 3)
+#define EFI_ACPI_2_0_PWR_BUTTON     (1 << 4)
+#define EFI_ACPI_2_0_SLP_BUTTON     (1 << 5)
+#define EFI_ACPI_2_0_FIX_RTC        (1 << 6)
+#define EFI_ACPI_2_0_RTC_S4         (1 << 7)
+#define EFI_ACPI_2_0_TMR_VAL_EXT    (1 << 8)
+#define EFI_ACPI_2_0_DCK_CAP        (1 << 9)
+#define EFI_ACPI_2_0_RESET_REG_SUP  (1 << 10)
+#define EFI_ACPI_2_0_SEALED_CASE    (1 << 11)
+#define EFI_ACPI_2_0_HEADLESS       (1 << 12)
+#define EFI_ACPI_2_0_CPU_SW_SLP     (1 << 13)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved[31];
+} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// FACS Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x01
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)
+
+//
+// Multiple APIC Description Table header definition.  The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_PCAT_COMPAT  (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_2_0_IO_APIC                        0x01
+#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_2_0_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_2_0_IO_SAPIC                       0x06
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC          0x07
+#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES     0x08
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Local APIC Address Override Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+//
+// IO SAPIC Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
+
+//
+// Local SAPIC Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  Reserved;
+} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// SBST Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Embedded Controller Boot Resources Table (ECDT)
+// The table is followed by a null terminated ASCII string that contains
+// a fully qualified reference to the name space object.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+//
+// ECDT Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  0x2052545020445352
+
+//
+// "SPIC" Multiple SAPIC Description Table
+//
+// BUGBUG: Don't know where this came from except SR870BN4 uses it.
+// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
+//
+#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
+
+//
+// "BOOT" MS Simple Boot Spec
+//
+#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
+
+//
+// "DBGP" MS Bebug Port Spec
+//
+#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445344
+
+//
+// "ECDT" Embedded Controller Boot Resources Table
+//
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
+
+//
+// "ETDT" Event Timer Description Table
+//
+#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  0x54445445
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  0x53434146
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  0x43495041
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  0x54534253
+
+//
+// "SLIT" System Locality Information Table
+//
+#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  0x54494C53
+
+//
+// "SPCR" Serial Port Concole Redirection Table
+//
+#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  0x52435053
+
+//
+// "SRAT" Static Resource Affinity Table
+//
+#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+//
+// "SPMI" Server Platform Management Interface Table
+//
+#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE 0x494D5053
+
+//
+// "XSDT" Extended System Description Table
+//
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445358
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi3_0.h

@@ -0,0 +1,681 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  Acpi3_0.h
+
+Abstract:
+
+  ACPI 3.0 definitions from the ACPI Specification Revision 3.0
+
+--*/
+
+#ifndef _ACPI_3_0_H_
+#define _ACPI_3_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI Specification Revision
+//
+#define EFI_ACPI_3_0_REVISION 0x03
+
+//
+// ACPI 3.0 Generic Address Space definition
+//
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_3_0_SYSTEM_MEMORY              0
+#define EFI_ACPI_3_0_SYSTEM_IO                  1
+#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_3_0_SMBUS                      4
+#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE  0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_3_0_UNDEFINED  0
+#define EFI_ACPI_3_0_BYTE       1
+#define EFI_ACPI_3_0_WORD       2
+#define EFI_ACPI_3_0_DWORD      3
+#define EFI_ACPI_3_0_QWORD      4
+
+//
+// ACPI 3.0 table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// RSD_PTR Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  // ACPISpec30 (Revision 3.0) says current value is 2
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_3_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT64 table pointers.
+//
+//
+// XSDT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT8                                   Reserved2[3];
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x04
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_3_0_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER  7
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_LEGACY_DEVICES    (1 << 0)
+#define EFI_ACPI_3_0_8042              (1 << 1)
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT   (1 << 2)
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED (1 << 3)
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS (1 << 4)
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_WBINVD                   (1 << 0)
+#define EFI_ACPI_3_0_WBINVD_FLUSH             (1 << 1)
+#define EFI_ACPI_3_0_PROC_C1                  (1 << 2)
+#define EFI_ACPI_3_0_P_LVL2_UP                (1 << 3)
+#define EFI_ACPI_3_0_PWR_BUTTON               (1 << 4)
+#define EFI_ACPI_3_0_SLP_BUTTON               (1 << 5)
+#define EFI_ACPI_3_0_FIX_RTC                  (1 << 6)
+#define EFI_ACPI_3_0_RTC_S4                   (1 << 7)
+#define EFI_ACPI_3_0_TMR_VAL_EXT              (1 << 8)
+#define EFI_ACPI_3_0_DCK_CAP                  (1 << 9)
+#define EFI_ACPI_3_0_RESET_REG_SUP            (1 << 10)
+#define EFI_ACPI_3_0_SEALED_CASE              (1 << 11)
+#define EFI_ACPI_3_0_HEADLESS                 (1 << 12)
+#define EFI_ACPI_3_0_CPU_SW_SLP               (1 << 13)
+#define EFI_ACPI_3_0_PCI_EXP_WAK              (1 << 14)
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK       (1 << 15)
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID         (1 << 16)
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE  (1 << 17)
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL (1 << 18)
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE (1 << 19)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved[31];
+} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// FACS Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x01
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_S4BIOS_F (1 << 0)
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header followed by a
+// definition block.
+//
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+//
+// Multiple APIC Description Table header definition.  The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_PCAT_COMPAT  (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_3_0_IO_APIC                        0x01
+#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_3_0_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_3_0_IO_SAPIC                       0x06
+#define EFI_ACPI_3_0_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES     0x08
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure Definition
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_POLARITY      (3 << 0)
+#define EFI_ACPI_3_0_TRIGGER_MODE  (3 << 2)
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Local APIC Address Override Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+//
+// IO SAPIC Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
+
+//
+// Local SAPIC Structure
+// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+//
+// Platform Interrupt Source Flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE     (1 << 0)
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// SBST Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Embedded Controller Boot Resources Table (ECDT)
+// The table is followed by a null terminated ASCII string that contains
+// a fully qualified reference to the name space object.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+//
+// ECDT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+//
+// System Resource Affinity Table (SRAT.  The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  // Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+//
+// SRAT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x02
+
+//
+// SRAT structure types.
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_3_0_MEMORY_AFFINITY                      0x01
+
+//
+// Processor Local APIC/SAPIC Affinity Structure Definition
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT8   Reserved[4];
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+//
+// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+//
+// Memory Affinity Structure Definition
+//
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_3_0_MEMORY_NONVOLATILE   (1 << 2)
+
+//
+// System Locality Distance Information Table (SLIT).
+// The rest of the table is a matrix.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+//
+// SLIT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  0x2052545020445352
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  0x43495041
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445344
+
+//
+// "ECDT" Embedded Controller Boot Resources Table
+//
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  0x53434146
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  0x54534253
+
+//
+// "SLIT" System Locality Information Table
+//
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  0x54494C53
+
+//
+// "SRAT" System Resource Affinity Table
+//
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+//
+// "XSDT" Extended System Description Table
+//
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  0x54445358
+
+//
+// "BOOT" MS Simple Boot Spec
+//
+#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
+
+//
+// "CPEP" Corrected Platform Error Polling Table
+// See
+//
+#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE 0x50455043
+
+//
+// "DBGP" MS Debug Port Spec
+//
+#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
+
+//
+// "ETDT" Event Timer Description Table
+//
+#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  0x54445445
+
+//
+// "HPET" IA-PC High Precision Event Timer Table
+//
+#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE 0x54455048
+
+//
+// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+//
+#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  0x4746434D
+
+//
+// "SPCR" Serial Port Concole Redirection Table
+//
+#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  0x52435053
+
+//
+// "SPMI" Server Platform Management Interface Table
+//
+#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE 0x494D5053
+
+//
+// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+//
+#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE 0x41504354
+
+//
+// "WDRT" Watchdog Resource Table
+//
+#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE 0x54524457
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AcpiCommon.h

@@ -0,0 +1,98 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  AcpiCommon.h
+
+Abstract:
+
+  This file contains some basic ACPI definitions that are consumed by drivers
+  that do not care about ACPI versions.
+
+--*/
+
+#ifndef _ACPI_COMMON_H_
+#define _ACPI_COMMON_H_
+
+#include "Tiano.h"
+
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_COMMON_HEADER;
+
+//
+// Common ACPI description table header.  This structure prefaces most ACPI tables.
+//
+#pragma pack(1)
+
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT8   Revision;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT64  OemTableId;
+  UINT32  OemRevision;
+  UINT32  CreatorId;
+  UINT32  CreatorRevision;
+} EFI_ACPI_DESCRIPTION_HEADER;
+
+#pragma pack()
+//
+// Define for Pci Host Bridge Resource Allocation
+//
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
+#define ACPI_END_TAG_DESCRIPTOR       0x79
+
+#define ACPI_ADDRESS_SPACE_TYPE_MEM   0x00
+#define ACPI_ADDRESS_SPACE_TYPE_IO    0x01
+#define ACPI_ADDRESS_SPACE_TYPE_BUS   0x02
+
+//
+// Make sure structures match spec
+//
+#pragma pack(1)
+
+typedef struct {
+  UINT8   Desc;
+  UINT16  Len;
+  UINT8   ResType;
+  UINT8   GenFlag;
+  UINT8   SpecificFlag;
+  UINT64  AddrSpaceGranularity;
+  UINT64  AddrRangeMin;
+  UINT64  AddrRangeMax;
+  UINT64  AddrTranslationOffset;
+  UINT64  AddrLen;
+} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
+
+typedef struct {
+  UINT8 Desc;
+  UINT8 Checksum;
+} EFI_ACPI_END_TAG_DESCRIPTOR;
+
+//
+// General use definitions
+//
+#define EFI_ACPI_RESERVED_BYTE  0x00
+#define EFI_ACPI_RESERVED_WORD  0x0000
+#define EFI_ACPI_RESERVED_DWORD 0x00000000
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AlertStandardFormatTable.h

@@ -0,0 +1,123 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  AlertStandardFormatTable.h
+
+Abstract:
+
+  ACPI Alert Standard Format Description Table ASF! as described 
+  in the ASF2.0 Specification
+
+--*/
+
+#ifndef _ALERT_STANDARD_FORMAT_TABLE_H
+#define _ALERT_STANDARD_FORMAT_TABLE_H
+
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Information Record header that appears at the beginning of each record
+//
+typedef struct {
+  UINT8                                Type;
+  UINT8                                Reserved;
+  UINT16                               RecordLength;
+} EFI_ACPI_ASF_RECORD_HEADER;
+
+//
+// This structure contains information that identifies the system type 
+// and configuration
+//
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                MinWatchDogResetValue;
+  UINT8                                MinPollingInterval;
+  UINT16                               SystemID;
+  UINT32                               IANAManufactureID;
+  UINT8                                FeatureFlags;
+  UINT8                                Reserved[3];
+} EFI_ACPI_ASF_INFO;
+
+//
+// Alert sensors definition
+//
+#define ASF_ALRT_SENSOR_ARRAY_LENGTH     36
+
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                AssertionEventBitMask;
+  UINT8                                DeassertionEventBitMask;
+  UINT8                                NumberOfAlerts;
+  UINT8                                ArrayElementLength;
+  UINT8                                DeviceArray[ASF_ALRT_SENSOR_ARRAY_LENGTH];
+} EFI_ACPI_ASF_ALRT;
+
+//
+// Alert Remote Control System Actions
+//
+#define ASF_RCTL_DEVICES_ARRAY_LENGTH      16  
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                NumberOfControls;
+  UINT8                                ArrayElementLength;
+  UINT16                               RctlReserved;
+  UINT8                                ControlArray[ASF_RCTL_DEVICES_ARRAY_LENGTH];
+} EFI_ACPI_ASF_RCTL;
+
+//
+// Remote Control Capabilities
+//
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                RemoteControlCapabilities[7];
+  UINT8                                RMCPCompletionCode;
+  UINT32                               RMCPIANA;
+  UINT8                                RMCPSpecialCommand;
+  UINT8                                RMCPSpecialCommandParameter[2];
+  UINT8                                RMCPBootOptions[2];
+  UINT8                                RMCPOEMParameters[2];
+} EFI_ACPI_ASF_RMCP;
+
+//
+// SMBus Devices with fixed addresses
+//
+#define ASF_ADDR_DEVICE_ARRAY_LENGTH      16  
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                SEEPROMAddress;
+  UINT8                                NumberOfDevices;
+  UINT8                                FixedSmbusAddresses[ASF_ADDR_DEVICE_ARRAY_LENGTH];
+} EFI_ACPI_ASF_ADDR;
+
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER          Header;
+  EFI_ACPI_ASF_INFO                    AsfInfo;
+  EFI_ACPI_ASF_ALRT                    AsfAlert;
+  EFI_ACPI_ASF_RCTL                    AsfRctl;
+  EFI_ACPI_ASF_RMCP                    AsfRmcp;
+  EFI_ACPI_ASF_ADDR                    AsfAddr;
+} EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE;
+
+//
+// "ASF!" ASF Description Table Signature
+//
+#define EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE  0x21465341
+
+#pragma pack ()
+
+#endif // _ALERT_STANDARD_FORMAT_TABLE_H

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/DMARemappingReportingTable.h

@@ -0,0 +1,202 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  DMARemappingReportingTable.h
+
+Abstract:
+
+  The definition for ACPI DMA-Remapping Reporting (DMAR) Table.
+  It is defined in "Intel VT for Direct IO Architecture Specification".
+
+--*/
+
+#ifndef _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
+#define _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
+
+#include "AcpiCommon.h"
+
+//
+// "DMAR" DMAR Description Table Signature
+//
+#define EFI_ACPI_DMAR_DESCRIPTION_TABLE_SIGNATURE  0x52414d44
+
+//
+// DMAR Revision
+//
+#define EFI_ACPI_DMAR_DESCRIPTION_TABLE_REVISION   0x01
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Definition for DMA Remapping Structure Types
+//
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_DRHD  0
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_RMRR  1
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_ATSR  2
+
+//
+// Definition for DMA Remapping Structure Header
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+} EFI_ACPI_DMAR_STRUCTURE_HEADER;
+
+//
+// Definition for DMA-Remapping PCI Path
+//
+typedef struct {
+  UINT8         Device;
+  UINT8         Function;
+} EFI_ACPI_DMAR_PCI_PATH;
+
+//
+// Definition for DMA-Remapping Device Scope Entry Structure
+//
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ENDPOINT                 0x01
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_BRIDGE                   0x02
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC                   0x03
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET         0x04
+typedef struct {
+  UINT8                   DeviceScopeEntryType;
+  UINT8                   Length;
+  UINT16                  Reserved_2;
+  UINT8                   EnumerationID;
+  UINT8                   StartingBusNumber;
+} EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
+
+//
+// Definition for DMA-Remapping Hardware Definition (DRHD) Structure
+//
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_SET     0x1
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_CLEAR   0x0
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT8                                       Flags;
+  UINT8                                       Reserved_5;
+  UINT16                                      SegmentNumber;
+  UINT64                                      RegisterBaseAddress;
+} EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
+
+//
+// Definition for Reserved Memory Region Reporting (RMRR) Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT8                                       Reserved_4[2];
+  UINT16                                      SegmentNumber;
+  UINT64                                      ReservedMemoryRegionBaseAddress;
+  UINT64                                      ReservedMemoryRegionLimitAddress;
+} EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
+
+//
+// Definition for Root Port ATS Capability Reporting (ATSR) Structure
+//
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_SET     0x1
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_CLEAR   0x0
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT8                                       Flags;
+  UINT8                                       Reserved_5;
+  UINT16                                      SegmentNumber;
+} EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
+
+//
+// Definition for DMA Remapping Structure
+//
+typedef union {
+  EFI_ACPI_DMAR_STRUCTURE_HEADER                               DMARStructureHeader;
+  EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE             DMARHardwareUnitDefinition;
+  EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE     DMARReservedMemoryRegionReporting;
+  EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE   DMARRootPortATSCapabilityReporting;
+} EFI_ACPI_DMA_REMAPPING_STRUCTURE;
+
+//
+// Definition for DMA-Remapping Reporting ACPI Table
+//
+#define EFI_ACPI_DMAR_TABLE_FLAGS_INTR_REMAP_SET            0x01
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER                               Header;
+  UINT8                                                     HostAddressWidth;
+  UINT8                                                     Flags;
+  UINT8                                                     Reserved_38[10];
+} EFI_ACPI_DMAR_DESCRIPTION_TABLE;
+
+//
+// The Platform specific definition can be as follows:
+//   NOTE: we use /**/ as comment for user convenience to copy it.
+//
+
+/*
+
+//
+// Dmar.h
+//
+
+#define EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES                  0x01  // user need to update
+typedef struct {
+  EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE               Header;
+  EFI_ACPI_DMAR_PCI_PATH                                   PciPath[EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES];    
+} EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY    0x01  // user need to update
+typedef struct {
+  EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE           Header;
+  EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE             DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY];
+} EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY    0x01  // user need to update
+typedef struct {
+  EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE   Header;
+  EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE             DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY];
+} EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY    0x01  // user need to update
+typedef struct {
+  EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE   Header;
+  EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE               DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY];
+} EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
+
+#define EFI_ACPI_DMAR_DHRD_ENTRY_COUNT                     0x1   // user need to update
+#define EFI_ACPI_DMAR_RMRR_ENTRY_COUNT                     0x1   // user need to update
+#define EFI_ACPI_DMAR_ATSR_ENTRY_COUNT                     0x1   // user need to update
+
+typedef struct {
+  EFI_ACPI_DMAR_DESCRIPTION_TABLE                                  Header;
+
+#if EFI_ACPI_3_0_DMAR_DHRD_ENTRY_COUNT > 0
+  EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE             Dhrd[EFI_ACPI_DMAR_DHRD_ENTRY_COUNT];
+#endif
+
+#if EFI_ACPI_3_0_DMAR_RMRR_ENTRY_COUNT > 0
+  EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE     Rmrr[EFI_ACPI_DMAR_RMRR_ENTRY_COUNT];
+#endif
+
+#if EFI_ACPI_3_0_DMAR_ATSR_ENTRY_COUNT > 0
+  EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE   Atsr[EFI_ACPI_DMAR_ATSR_ENTRY_COUNT];
+#endif
+
+} EFI_ACPI_3_0_DMA_REMAPPING_REPORTING_TABLE;
+
+*/
+
+#pragma pack()
+
+#endif
+

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/HighPrecisionEventTimerTable.h

@@ -0,0 +1,62 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  HighPrecisionEventTimerTable.h
+
+Abstract:
+
+  ACPI high precision event timer table definition, defined at 
+  Intel IA-PC HPET (High Precision Event Timers) Specification.
+
+--*/
+
+#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+
+//
+// Include files
+//
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// High Precision Event Timer Table header definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  EventTimerBlockId;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  BaseAddressLower32Bit;
+  UINT8                                   HpetNumber;
+  UINT16                                  MainCounterMinimumClockTickInPeriodicMode;
+  UINT8                                   PageProtectionAndOemAttribute;
+} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
+
+//
+// HPET Revision (defined in spec)
+//
+#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION  0x01
+
+//
+// Page protection setting
+// Values 3 through 15 are reserved for use by the specification
+//
+#define EFI_ACPI_NO_PAGE_PROTECTION   0
+#define EFI_ACPI_4KB_PAGE_PROTECTION  1
+#define EFI_ACPI_64KB_PAGE_PROTECTION 2
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/LegacyBiosMpTable.h

@@ -0,0 +1,283 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  LegacyBiosMpTable.h
+
+Abstract:
+  Defives data structures per Multi Processor Specification Ver 1.4.
+
+--*/
+
+#ifndef LEGACY_BIOS_MPTABLE_H_
+#define LEGACY_BIOS_MPTABLE_H_
+
+#include "Tiano.h"
+
+#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
+
+//
+// Define MP table structures. All are packed.
+//
+#pragma pack(push, 1)
+
+#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE  EFI_SIGNATURE_32 ('_', 'M', 'P', '_')
+typedef struct {
+  UINT32  Signature;
+  UINT32  PhysicalAddress;
+  UINT8   Length;
+  UINT8   SpecRev;
+  UINT8   Checksum;
+  UINT8   FeatureByte1;
+  struct {
+    UINT32  Reserved1 : 6;
+    UINT32  MutipleClk : 1;
+    UINT32  Imcr : 1;
+    UINT32  Reserved2 : 24;
+  } FeatureByte2_5;
+} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;
+
+#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE  EFI_SIGNATURE_32 ('P', 'C', 'M', 'P')
+typedef struct {
+  UINT32  Signature;
+  UINT16  BaseTableLength;
+  UINT8   SpecRev;
+  UINT8   Checksum;
+  CHAR8   OemId[8];
+  CHAR8   OemProductId[12];
+  UINT32  OemTablePointer;
+  UINT16  OemTableSize;
+  UINT16  EntryCount;
+  UINT32  LocalApicAddress;
+  UINT16  ExtendedTableLength;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved;
+} EFI_LEGACY_MP_TABLE_HEADER;
+
+typedef struct {
+  UINT8 EntryType;
+} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;
+
+//
+// Entry Type 0: Processor.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR  0x00
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Id;
+  UINT8 Ver;
+  struct {
+    UINT8 Enabled : 1;
+    UINT8 Bsp : 1;
+    UINT8 Reserved : 6;
+  } Flags;
+  struct {
+    UINT32  Stepping : 4;
+    UINT32  Model : 4;
+    UINT32  Family : 4;
+    UINT32  Reserved : 20;
+  } Signature;
+  struct {
+    UINT32  Fpu : 1;
+    UINT32  Reserved1 : 6;
+    UINT32  Mce : 1;
+    UINT32  Cx8 : 1;
+    UINT32  Apic : 1;
+    UINT32  Reserved2 : 22;
+  } Features;
+  UINT32  Reserved1;
+  UINT32  Reserved2;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;
+
+//
+// Entry Type 1: Bus.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS  0x01
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Id;
+  CHAR8 TypeString[6];
+} EFI_LEGACY_MP_TABLE_ENTRY_BUS;
+
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS   "CBUS  "  // Corollary CBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII"  // Corollary CBUS II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA   "EISA  "  // Extended ISA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE"  // IEEE FutureBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN"  // Internal bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA    "ISA   "  // Industry Standard Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI    "MBI   "  // Multibus I
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII   "MBII  "  // Multibus II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA    "MCA   "  // Micro Channel Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI    "MPI   "  // MPI
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA   "MPSA  "  // MPSA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS  "NUBUS "  // Apple Macintosh NuBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI    "PCI   "  // Peripheral Component Interconnect
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA"  // PC Memory Card International Assoc.
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC     "TC    "  // DEC TurboChannel
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL     "VL    "  // VESA Local Bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME    "VME   "  // VMEbus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS"  // Express System Bus
+//
+// Entry Type 2: I/O APIC.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Id;
+  UINT8 Ver;
+  struct {
+    UINT8 Enabled : 1;
+    UINT8 Reserved : 7;
+  } Flags;
+  UINT32  Address;
+} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;
+
+//
+// Entry Type 3: I/O Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
+typedef struct {
+  UINT8 EntryType;
+  UINT8 IntType;
+  struct {
+    UINT16  Polarity : 2;
+    UINT16  Trigger : 2;
+    UINT16  Reserved : 12;
+  } Flags;
+  UINT8 SourceBusId;
+  union {
+    struct {
+      UINT8 IntNo : 2;
+      UINT8 Dev : 5;
+      UINT8 Reserved : 1;
+    } fields;
+    UINT8 byte;
+  } SourceBusIrq;
+  UINT8 DestApicId;
+  UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;
+
+typedef enum {
+  EfiLegacyMpTableEntryIoIntTypeInt   = 0,
+  EfiLegacyMpTableEntryIoIntTypeNmi   = 1,
+  EfiLegacyMpTableEntryIoIntTypeSmi   = 2,
+  EfiLegacyMpTableEntryIoIntTypeExtInt= 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;
+
+typedef enum {
+  EfiLegacyMpTableEntryIoIntFlagsPolaritySpec       = 0x0,
+  EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1,
+  EfiLegacyMpTableEntryIoIntFlagsPolarityReserved   = 0x2,
+  EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow  = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;
+
+typedef enum {
+  EfiLegacyMpTableEntryIoIntFlagsTriggerSpec        = 0x0,
+  EfiLegacyMpTableEntryIoIntFlagsTriggerEdge        = 0x1,
+  EfiLegacyMpTableEntryIoIntFlagsTriggerReserved    = 0x2,
+  EfiLegacyMpTableEntryIoIntFlagsTriggerLevel       = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 4: Local Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT  0x04
+typedef struct {
+  UINT8 EntryType;
+  UINT8 IntType;
+  struct {
+    UINT16  Polarity : 2;
+    UINT16  Trigger : 2;
+    UINT16  Reserved : 12;
+  } Flags;
+  UINT8 SourceBusId;
+  UINT8 SourceBusIrq;
+  UINT8 DestApicId;
+  UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;
+
+typedef enum {
+  EfiLegacyMpTableEntryLocalIntTypeInt              = 0,
+  EfiLegacyMpTableEntryLocalIntTypeNmi              = 1,
+  EfiLegacyMpTableEntryLocalIntTypeSmi              = 2,
+  EfiLegacyMpTableEntryLocalIntTypeExtInt           = 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;
+
+typedef enum {
+  EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec      = 0x0,
+  EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1,
+  EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved  = 0x2,
+  EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;
+
+typedef enum {
+  EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec       = 0x0,
+  EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge       = 0x1,
+  EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved   = 0x2,
+  EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel      = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 128: System Address Space Mapping.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
+typedef struct {
+  UINT8   EntryType;
+  UINT8   Length;
+  UINT8   BusId;
+  UINT8   AddressType;
+  UINT64  AddressBase;
+  UINT64  AddressLength;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;
+
+typedef enum {
+  EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo       = 0,
+  EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory   = 1,
+  EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2,
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE;
+
+//
+// Entry Type 129: Bus Hierarchy.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY  0x81
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Length;
+  UINT8 BusId;
+  struct {
+    UINT8 SubtractiveDecode : 1;
+    UINT8 Reserved : 7;
+  } BusInfo;
+  UINT8 ParentBus;
+  UINT8 Reserved1;
+  UINT8 Reserved2;
+  UINT8 Reserved3;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;
+
+//
+// Entry Type 130: Compatibility Bus Address Space Modifier.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Length;
+  UINT8 BusId;
+  struct {
+    UINT8 RangeMode : 1;
+    UINT8 Reserved : 7;
+  } AddrMode;
+  UINT32  PredefinedRangeList;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;
+
+#pragma pack(pop)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h

@@ -0,0 +1,56 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  MemoryMappedConfigurationSpaceAccessTable.h
+
+Abstract:
+
+  ACPI memory mapped configuration space access table definition, defined at 
+  in the PCI Firmware Specification, version 3.0.
+  Specification is available at http://www.pcisig.com.
+
+--*/
+
+#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+
+//
+// Include files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// Memory Mapped Configuration Space Access Table (MCFG)
+// This table is a basic description table header followed by
+// a number of base address allocation structures.
+//
+typedef struct {
+  UINT64  BaseAddress;
+  UINT16  PciSegmentGroupNumber;
+  UINT8   StartBusNumber;
+  UINT8   EndBusNumber;
+  UINT32  Reserved;
+} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
+
+//
+// MCFG Revision (defined in spec)
+//
+#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION  0x01
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h

@@ -0,0 +1,73 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name: 
+
+  SdramSpd.h
+
+Abstract:
+
+  This file contains definitions for the SPD fields on an SDRAM.
+ 
+--*/
+
+#ifndef _SDRAM_SPD_H
+#define _SDRAM_SPD_H
+
+//
+// SDRAM SPD field definitions
+//
+#define SPD_MEMORY_TYPE                 2
+#define SPD_SDRAM_ROW_ADDR              3
+#define SPD_SDRAM_COL_ADDR              4
+#define SPD_SDRAM_MODULE_ROWS           5
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
+#define SPD_SDRAM_ECC_SUPPORT           11
+#define SPD_SDRAM_REFRESH               12
+#define SPD_SDRAM_WIDTH                 13
+#define SPD_SDRAM_ERROR_WIDTH           14
+#define SPD_SDRAM_BURST_LENGTH          16
+#define SPD_SDRAM_NO_OF_BANKS           17
+#define SPD_SDRAM_CAS_LATENCY           18
+#define SPD_SDRAM_MODULE_ATTR           21
+
+#define SPD_SDRAM_TCLK1_PULSE           9   // cycle time for highest cas latency
+#define SPD_SDRAM_TAC1_PULSE            10  // access time for highest cas latency
+#define SPD_SDRAM_TCLK2_PULSE           23  // cycle time for 2nd highest cas latency
+#define SPD_SDRAM_TAC2_PULSE            24  // access time for 2nd highest cas latency
+#define SPD_SDRAM_TCLK3_PULSE           25  // cycle time for 3rd highest cas latency
+#define SPD_SDRAM_TAC3_PULSE            26  // access time for 3rd highest cas latency
+#define SPD_SDRAM_MIN_PRECHARGE         27
+#define SPD_SDRAM_ACTIVE_MIN            28
+#define SPD_SDRAM_RAS_CAS               29
+#define SPD_SDRAM_RAS_PULSE             30
+#define SPD_SDRAM_DENSITY               31
+
+//
+// Memory Type Definitions
+//
+#define SPD_VAL_SDR_TYPE  4 // SDR SDRAM memory
+#define SPD_VAL_DDR_TYPE  7 // DDR SDRAM memory
+#define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory
+//
+// ECC Type Definitions
+//
+#define SPD_ECC_TYPE_NONE   0x00  // No error checking
+#define SPD_ECC_TYPE_PARITY 0x01  // No error checking
+#define SPD_ECC_TYPE_ECC    0x02  // Error checking only
+//
+// Module Attributes (Bit positions)
+//
+#define SPD_BUFFERED    0x01
+#define SPD_REGISTERED  0x02
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ServerProcessorManagementInterfaceTable.h

@@ -0,0 +1,80 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  ServerProcessorManagementInterfaceTable.h
+
+Abstract:
+
+  ACPI Server Processor Management Interface Table SPMI as described 
+  in the IPMI2.0 Specification Revistion 1.5
+
+--*/
+
+#ifndef _SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+#define _SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Server Processor Management Interface Table definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER            Header;
+  UINT8                                  Reserved_36;
+  UINT8                                  InterfaceType;
+  UINT16                                 SpecificationRevision;
+  UINT8                                  InterruptType;
+  UINT8                                  GPE;
+  UINT8                                  Reserved_42;
+  UINT8                                  PCIDeviceFlag;
+  UINT32                                 GlobalSystemInterrupt;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+  UINT8                                  PCISegmentGroup_UID1;
+  UINT8                                  PCIBusNumber_UID2;
+  UINT8                                  PCIDeviceNumber_UID3;
+  UINT8                                  PCIFunctionNumber_UID4;
+} EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+//
+// SPMI Revision
+//
+#define EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISION  0x05
+
+//
+// Interface Type
+//
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_RESERVED   0
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_KCS        1
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_SMIC       2
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_BT         3
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_SSIF       4
+
+//
+// SPMI Specfication Revision
+//
+#define EFI_ACPI_SPMI_SPECIFICATION_REVISION  0x0150
+
+//
+// SPMI Interrupt Type
+//
+#define EFI_ACPI_SPMI_INTERRUPT_TYPE_SCI     0x1
+#define EFI_ACPI_SPMI_INTERRUPT_TYPE_IOAPIC  0x2
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h

@@ -0,0 +1,576 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name: 
+
+  Smbios.h
+
+Abstract:
+
+--*/
+
+#ifndef _SMBIOS_TABLE_H_
+#define _SMBIOS_TABLE_H_
+
+#include "Tiano.h"
+
+#pragma pack(1)
+
+typedef UINT8 SMBIOS_TABLE_STRING;
+
+typedef struct {
+  UINT8                 AnchorString[4];
+  UINT8                 EntryPointStructureChecksum;
+  UINT8                 EntryPointLength;
+  UINT8                 MajorVersion;
+  UINT8                 MinorVersion;
+  UINT16                MaxStructureSize;
+  UINT8                 EntryPointRevision;
+  UINT8                 FormattedArea[5];
+  UINT8                 IntermediateAnchorString[5];
+  UINT8                 IntermediateChecksum;
+  UINT16                TableLength;
+  UINT32                TableAddress;
+  UINT16                NumberOfSmbiosStructures;
+  UINT8                 SmbiosBcdRevision;
+} SMBIOS_TABLE_STRUCTURE;
+
+typedef struct {
+  UINT8                 Type;
+  UINT8                 Length;
+  UINT16                Handle;
+} SMBIOS_TABLE_HEADER;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Vendor;
+  SMBIOS_TABLE_STRING   BiosVersion;
+  UINT16                BiosSegment;
+  SMBIOS_TABLE_STRING   BiosReleaseDate;
+  UINT8                 BiosSize;
+  UINT64                BiosCharacteristics;
+  UINT8                 BIOSCharacteristicsExtensionBytes[2];
+  UINT8                 SystemBiosMajorRelease;
+  UINT8                 SystemBiosMinorRelease;
+  UINT8                 EmbeddedControllerFirmwareMajorRelease;
+  UINT8                 EmbeddedControllerFirmwareMinorRelease;
+} SMBIOS_TABLE_TYPE0;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Manufacturer;
+  SMBIOS_TABLE_STRING   ProductName;
+  SMBIOS_TABLE_STRING   Version;
+  SMBIOS_TABLE_STRING   SerialNumber;
+  EFI_GUID              Uuid;
+  UINT8                 WakeUpType;
+  SMBIOS_TABLE_STRING   SKUNumber;
+  SMBIOS_TABLE_STRING   Family;
+} SMBIOS_TABLE_TYPE1;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Manufacturer;
+  SMBIOS_TABLE_STRING   ProductName;
+  SMBIOS_TABLE_STRING   Version;
+  SMBIOS_TABLE_STRING   SerialNumber;
+  SMBIOS_TABLE_STRING   AssetTag;
+  UINT8                 FeatureFlag;
+  SMBIOS_TABLE_STRING   LocationInChassis;
+  UINT16                ChassisHandle;
+  UINT8                 BoardType;
+  UINT8                 NumberOfContainedObjectHandles;
+  UINT16                ContainedObjectHandles[1];
+} SMBIOS_TABLE_TYPE2;
+
+typedef struct {
+  UINT8                 ContainedElementType;
+  UINT8                 ContainedElementMinimum;
+  UINT8                 ContainedElementMaximum;
+} CONTAINED_ELEMENT;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Manufacturer;
+  UINT8                 Type;
+  SMBIOS_TABLE_STRING   Version;
+  SMBIOS_TABLE_STRING   SerialNumber;
+  SMBIOS_TABLE_STRING   AssetTag;
+  UINT8                 BootupState;
+  UINT8                 PowerSupplyState;
+  UINT8                 ThermalState;
+  UINT8                 SecurityStatus;
+  UINT8                 OemDefined[4];
+  UINT8                 Height;
+  UINT8                 NumberofPowerCords;
+  UINT8                 ContainedElementCount;
+  UINT8                 ContainedElementRecordLength;
+  CONTAINED_ELEMENT     ContainedElements[1];
+} SMBIOS_TABLE_TYPE3;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 Socket;
+  UINT8                 ProcessorType;
+  UINT8                 ProcessorFamily;
+  SMBIOS_TABLE_STRING   ProcessorManufacture;
+  UINT8                 ProcessorId[8];
+  SMBIOS_TABLE_STRING   ProcessorVersion;
+  UINT8                 Voltage;
+  UINT16                ExternalClock;
+  UINT16                MaxSpeed;
+  UINT16                CurrentSpeed;
+  UINT8                 Status;
+  UINT8                 ProcessorUpgrade;
+  UINT16                L1CacheHandle;
+  UINT16                L2CacheHandle;
+  UINT16                L3CacheHandle;
+  SMBIOS_TABLE_STRING   SerialNumber;
+  SMBIOS_TABLE_STRING   AssetTag;
+  SMBIOS_TABLE_STRING   PartNumber;
+} SMBIOS_TABLE_TYPE4;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 ErrDetectMethod;
+  UINT8                 ErrCorrectCapability;
+  UINT8                 SupportInterleave;
+  UINT8                 CurrentInterleave;
+  UINT8                 MaxMemoryModuleSize;
+  UINT16                SupportSpeed;
+  UINT16                SupportMemoryType;
+  UINT8                 MemoryModuleVoltage;
+  UINT8                 AssociatedMemorySlotNum;
+  UINT16                MemoryModuleConfigHandles[1];
+//  UINT8                 EnableErrCorrectCapabilities;
+} SMBIOS_TABLE_TYPE5;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   SocketDesignation;
+  UINT8                 BankConnections;
+  UINT8                 CurrentSpeed;
+  UINT16                CurrentMemoryType;
+  UINT8                 InstalledSize;
+  UINT8                 EnabledSize;
+  UINT8                 ErrorStatus;
+} SMBIOS_TABLE_TYPE6;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   SocketDesignation;
+  UINT16                CacheConfiguration;
+  UINT16                MaximumCacheSize;
+  UINT16                InstalledSize;
+  UINT16                SupportedSRAMType;
+  UINT16                CurrentSRAMType;
+  UINT8                 CacheSpeed;
+  UINT8                 ErrorCorrectionType;
+  UINT8                 SystemCacheType;
+  UINT8                 Associativity;
+} SMBIOS_TABLE_TYPE7;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   InternalReferenceDesignator;
+  UINT8                 InternalConnectorType;
+  SMBIOS_TABLE_STRING   ExternalReferenceDesignator;
+  UINT8                 ExternalConnectorType;
+  UINT8                 PortType;
+} SMBIOS_TABLE_TYPE8;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   SlotDesignation;
+  UINT8                 SlotType;
+  UINT8                 SlotDataBusWidth;
+  UINT8                 CurrentUsage;
+  UINT8                 SlotLength;
+  UINT16                SlotID;
+  UINT8                 SlotCharacteristics1;
+  UINT8                 SlotCharacteristics2;
+} SMBIOS_TABLE_TYPE9;
+
+typedef struct {
+  UINT8                 DeviceType;
+  SMBIOS_TABLE_STRING   DescriptionString;
+} DEVICE_STRUCT;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  DEVICE_STRUCT         Device[1];
+} SMBIOS_TABLE_TYPE10;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 StringCount;
+} SMBIOS_TABLE_TYPE11;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 StringCount;
+} SMBIOS_TABLE_TYPE12;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 InstallableLanguages;
+  UINT8                 Flags;
+  UINT8                 reserved[15];
+  SMBIOS_TABLE_STRING   CurrentLanguages;
+} SMBIOS_TABLE_TYPE13;
+
+typedef struct {
+  UINT8                 ItemType;
+  UINT16                ItemHandle;
+} GROUP_STRUCT;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   GroupName;
+  GROUP_STRUCT          Group[1];
+} SMBIOS_TABLE_TYPE14;
+
+typedef struct {
+  UINT8                 LogType;
+  UINT8                 DataFormatType;
+} EVENT_LOG_TYPE;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT16                LogAreaLength;
+  UINT16                LogHeaderStartOffset;
+  UINT16                LogDataStartOffset;
+  UINT8                 AccessMethod;
+  UINT8                 LogStatus;
+  UINT32                LogChangeToken;
+  UINT32                AccessMethodAddress;
+  UINT8                 LogHeaderFormat;
+  UINT8                 NumberOfSupportedLogTypeDescriptors;
+  UINT8                 LengthOfLogTypeDescriptor;
+  EVENT_LOG_TYPE        EventLogTypeDescriptors[1];
+} SMBIOS_TABLE_TYPE15;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 Location;
+  UINT8                 Use;
+  UINT8                 MemoryErrorCorrection;
+  UINT32                MaximumCapacity;
+  UINT16                MemoryErrorInformationHandle;
+  UINT16                NumberOfMemoryDevices;
+} SMBIOS_TABLE_TYPE16;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT16                MemoryArrayHandle;
+  UINT16                MemoryErrorInformationHandle;
+  UINT16                TotalWidth;
+  UINT16                DataWidth;
+  UINT16                Size;
+  UINT8                 FormFactor;
+  UINT8                 DeviceSet;
+  SMBIOS_TABLE_STRING   DeviceLocator;
+  SMBIOS_TABLE_STRING   BankLocator;
+  UINT8                 MemoryType;
+  UINT16                TypeDetail;
+  UINT16                Speed;
+  SMBIOS_TABLE_STRING   Manufacturer;
+  SMBIOS_TABLE_STRING   SerialNumber;
+  SMBIOS_TABLE_STRING   AssetTag;
+  SMBIOS_TABLE_STRING   PartNumber;
+} SMBIOS_TABLE_TYPE17;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 ErrorType;
+  UINT8                 ErrorGranularity;
+  UINT8                 ErrorOperation;
+  UINT32                VendorSyndrome;
+  UINT32                MemoryArrayErrorAddress;
+  UINT32                DeviceErrorAddress;
+  UINT32                ErrorResolution;
+} SMBIOS_TABLE_TYPE18;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT32                StartingAddress;
+  UINT32                EndingAddress;
+  UINT16                MemoryArrayHandle;
+  UINT8                 PartitionWidth;
+} SMBIOS_TABLE_TYPE19;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT32                StartingAddress;
+  UINT32                EndingAddress;
+  UINT16                MemoryDeviceHandle;
+  UINT16                MemoryArrayMappedAddressHandle;
+  UINT8                 PartitionRowPosition;
+  UINT8                 InterleavePosition;
+  UINT8                 InterleavedDataDepth;
+} SMBIOS_TABLE_TYPE20;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 Type;
+  UINT8                 Interface;
+  UINT8                 NumberOfButtons;
+} SMBIOS_TABLE_TYPE21;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Location;
+  SMBIOS_TABLE_STRING   Manufacturer;
+  SMBIOS_TABLE_STRING   ManufactureDate;
+  SMBIOS_TABLE_STRING   SerialNumber;
+  SMBIOS_TABLE_STRING   DeviceName;
+  UINT8                 DeviceChemistry;
+  UINT16                DeviceCapacity;
+  UINT16                DesignVoltage;
+  SMBIOS_TABLE_STRING   SBDSVersionNumber;
+  UINT8                 MaximumErrorInBatteryData;
+  UINT16                SBDSSerialNumber;
+  UINT16                SBDSManufactureDate;
+  SMBIOS_TABLE_STRING   SBDSDeviceChemistry;
+  UINT8                 DesignCapacityMultiplier;
+  UINT32                OEMSpecific;
+} SMBIOS_TABLE_TYPE22;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 Capabilities;
+  UINT16                ResetCount;
+  UINT16                ResetLimit;
+  UINT16                TimerInterval;
+  UINT16                Timeout;
+} SMBIOS_TABLE_TYPE23;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 HardwareSecuritySettings;
+} SMBIOS_TABLE_TYPE24;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 NextScheduledPowerOnMonth;
+  UINT8                 NextScheduledPowerOnDayOfMonth;
+  UINT8                 NextScheduledPowerOnHour;
+  UINT8                 NextScheduledPowerOnMinute;
+  UINT8                 NextScheduledPowerOnSecond;
+} SMBIOS_TABLE_TYPE25;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Description;
+  UINT8                 LocationAndStatus;
+  UINT16                MaximumValue;
+  UINT16                MinimumValue;
+  UINT16                Resolution;
+  UINT16                Tolerance;
+  UINT16                Accuracy;
+  UINT32                OEMDefined;
+  UINT16                NominalValue;
+} SMBIOS_TABLE_TYPE26;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT16                TemperatureProbeHandle;
+  UINT8                 DeviceTypeAndStatus;
+  UINT8                 CoolingUnitGroup;
+  UINT32                OEMDefined;
+  UINT16                NominalSpeed;
+} SMBIOS_TABLE_TYPE27;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Description;
+  UINT8                 LocationAndStatus;
+  UINT16                MaximumValue;
+  UINT16                MinimumValue;
+  UINT16                Resolution;
+  UINT16                Tolerance;
+  UINT16                Accuracy;
+  UINT32                OEMDefined;
+  UINT16                NominalValue;
+} SMBIOS_TABLE_TYPE28;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Description;
+  UINT8                 LocationAndStatus;
+  UINT16                MaximumValue;
+  UINT16                MinimumValue;
+  UINT16                Resolution;
+  UINT16                Tolerance;
+  UINT16                Accuracy;
+  UINT32                OEMDefined;
+  UINT16                NominalValue;
+} SMBIOS_TABLE_TYPE29;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   ManufacturerName;
+  UINT8                 Connections;
+} SMBIOS_TABLE_TYPE30;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 Checksum;
+  UINT8                 Reserved1;
+  UINT16                Reserved2;
+  UINT32                BisEntry16;
+  UINT32                BisEntry32;
+  UINT64                Reserved3;
+  UINT32                Reserved4;
+} SMBIOS_TABLE_TYPE31;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 Reserved[6];
+  UINT8                 BootStatus[1];
+} SMBIOS_TABLE_TYPE32;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 ErrorType;
+  UINT8                 ErrorGranularity;
+  UINT8                 ErrorOperation;
+  UINT32                VendorSyndrome;
+  UINT64                MemoryArrayErrorAddress;
+  UINT64                DeviceErrorAddress;
+  UINT32                ErrorResolution;
+} SMBIOS_TABLE_TYPE33;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Description;
+  UINT8                 Type;
+  UINT32                Address;
+  UINT8                 AddressType;
+} SMBIOS_TABLE_TYPE34;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  SMBIOS_TABLE_STRING   Description;
+  UINT16                ManagementDeviceHandle;
+  UINT16                ComponentHandle;
+  UINT16                ThresholdHandle;
+} SMBIOS_TABLE_TYPE35;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT16                LowerThresholdNonCritical;
+  UINT16                UpperThresholdNonCritical;
+  UINT16                LowerThresholdCritical;
+  UINT16                UpperThresholdCritical;
+  UINT16                LowerThresholdNonRecoverable;
+  UINT16                UpperThresholdNonRecoverable;
+} SMBIOS_TABLE_TYPE36;
+
+typedef struct {
+  UINT8                 DeviceLoad;
+  UINT16                DeviceHandle;
+} MEMORY_DEVICE;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 ChannelType;
+  UINT8                 MaximumChannelLoad;
+  UINT8                 MemoryDeviceCount;
+  MEMORY_DEVICE         MemoryDevice[1];
+} SMBIOS_TABLE_TYPE37;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 InterfaceType;
+  UINT8                 IPMISpecificationRevision;
+  UINT8                 I2CSlaveAddress;
+  UINT8                 NVStorageDeviceAddress;
+  UINT64                BaseAddress;
+  UINT8                 BaseAddressModifier_InterruptInfo;
+  UINT8                 InterruptNumber;
+} SMBIOS_TABLE_TYPE38;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+  UINT8                 PowerUnitGroup;
+  SMBIOS_TABLE_STRING   Location;
+  SMBIOS_TABLE_STRING   DeviceName;
+  SMBIOS_TABLE_STRING   Manufacturer;
+  SMBIOS_TABLE_STRING   SerialNumber;
+  SMBIOS_TABLE_STRING   AssetTagNumber;
+  SMBIOS_TABLE_STRING   ModelPartNumber;
+  SMBIOS_TABLE_STRING   RevisionLevel;
+  UINT16                MaxPowerCapacity;
+  UINT16                PowerSupplyCharacteristics;
+  UINT16                InputVoltageProbeHandle;
+  UINT16                CoolingDeviceHandle;
+  UINT16                InputCurrentProbeHandle;
+} SMBIOS_TABLE_TYPE39;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+} SMBIOS_TABLE_TYPE126;
+
+typedef struct {
+  SMBIOS_TABLE_HEADER   Hdr;
+} SMBIOS_TABLE_TYPE127;
+
+typedef union {
+  SMBIOS_TABLE_HEADER   *Hdr;
+  SMBIOS_TABLE_TYPE0    *Type0;
+  SMBIOS_TABLE_TYPE1    *Type1;
+  SMBIOS_TABLE_TYPE2    *Type2;
+  SMBIOS_TABLE_TYPE3    *Type3;
+  SMBIOS_TABLE_TYPE4    *Type4;
+  SMBIOS_TABLE_TYPE5    *Type5;
+  SMBIOS_TABLE_TYPE6    *Type6;
+  SMBIOS_TABLE_TYPE7    *Type7;
+  SMBIOS_TABLE_TYPE8    *Type8;
+  SMBIOS_TABLE_TYPE9    *Type9;
+  SMBIOS_TABLE_TYPE10   *Type10;
+  SMBIOS_TABLE_TYPE11   *Type11;
+  SMBIOS_TABLE_TYPE12   *Type12;
+  SMBIOS_TABLE_TYPE13   *Type13;
+  SMBIOS_TABLE_TYPE14   *Type14;
+  SMBIOS_TABLE_TYPE15   *Type15;
+  SMBIOS_TABLE_TYPE16   *Type16;
+  SMBIOS_TABLE_TYPE17   *Type17;
+  SMBIOS_TABLE_TYPE18   *Type18;
+  SMBIOS_TABLE_TYPE19   *Type19;
+  SMBIOS_TABLE_TYPE20   *Type20;
+  SMBIOS_TABLE_TYPE21   *Type21;
+  SMBIOS_TABLE_TYPE22   *Type22;
+  SMBIOS_TABLE_TYPE23   *Type23;
+  SMBIOS_TABLE_TYPE24   *Type24;
+  SMBIOS_TABLE_TYPE25   *Type25;
+  SMBIOS_TABLE_TYPE26   *Type26;
+  SMBIOS_TABLE_TYPE27   *Type27;
+  SMBIOS_TABLE_TYPE28   *Type28;
+  SMBIOS_TABLE_TYPE29   *Type29;
+  SMBIOS_TABLE_TYPE30   *Type30;
+  SMBIOS_TABLE_TYPE31   *Type31;
+  SMBIOS_TABLE_TYPE32   *Type32;
+  SMBIOS_TABLE_TYPE33   *Type33;
+  SMBIOS_TABLE_TYPE34   *Type34;
+  SMBIOS_TABLE_TYPE35   *Type35;
+  SMBIOS_TABLE_TYPE36   *Type36;
+  SMBIOS_TABLE_TYPE37   *Type37;
+  SMBIOS_TABLE_TYPE38   *Type38;
+  SMBIOS_TABLE_TYPE39   *Type39;
+  SMBIOS_TABLE_TYPE126  *Type126;
+  SMBIOS_TABLE_TYPE127  *Type127;
+  UINT8                 *Raw;
+} SMBIOS_STRUCTURE_POINTER;
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/WatchdogDescriptionTable.h

@@ -0,0 +1,94 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  WatchdogDescriptionTable.h
+
+Abstract:
+
+  ACPI Watchdog Description Table as defined in Intel
+  ICH Family Watchdog Timer (WDT) Application Note (AP-725)
+
+--*/
+
+#ifndef _WATCH_DOG_DESCRIPTION_TABLE_H_
+#define _WATCH_DOG_DESCRIPTION_TABLE_H_
+
+//
+// Include files
+//
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// WDDT structure
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT16                                  SpecVersion;
+  UINT16                                  TableVersion;
+  UINT16                                  Vid;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  BaseAddress;
+  UINT16                                  TimerMaxCount;
+  UINT16                                  TimerMinCount;
+  UINT16                                  TimerCountPeriod;
+  UINT16                                  Status;
+  UINT16                                  Capability;
+} EFI_ACPI_1_0_WATCH_DOG_DESCRIPTION_TABLE;
+
+//
+// "WDDT" Watchdog Description Table signatures
+//
+#define EFI_ACPI_1_0_WDDT_SIGNATURE 0x54444457
+
+#pragma pack()
+
+//
+// WDDT Revision
+//
+#define EFI_ACPI_WATCHDOG_DESCRIPTION_1_0_TABLE_REVISION  0x01
+
+//
+// WDDT Spec Version
+//
+#define EFI_ACPI_WDDT_SPEC_1_0_VERSION                0x01
+
+//
+// WDDT Description Table Version
+//
+#define EFI_ACPI_WDDT_TABLE_1_0_VERSION               0x01
+
+//
+// WDT Status
+//
+#define EFI_ACPI_WDDT_STATUS_AVAILABLE             0x0001
+#define EFI_ACPI_WDDT_STATUS_ACTIVE                0x0002
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS         0x0000
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS           0x0004
+#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT      0x0800
+#define EFI_ACPI_WDDT_STATUS_WDT_EVENT             0x1000
+#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT      0x2000
+#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT   0x4000
+
+//
+// WDT Capability
+//
+#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET            0x0001
+#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT         0x0002
+#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN     0x0004
+#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN    0x0008
+#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT  0x0010
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h

@@ -0,0 +1,331 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+    Atapi.h
+    
+Abstract: 
+    
+
+Revision History
+--*/
+
+#ifndef _ATAPI_H
+#define _ATAPI_H
+
+#include "Tiano.h"
+
+#pragma pack(1)
+
+typedef struct {
+  UINT16  config;                     /* General Configuration */
+  UINT16  cylinders;                  /* Number of Cylinders */
+  UINT16  reserved_2;
+  UINT16  heads;                      /* Number of logical heads */
+  UINT16  vendor_data1;
+  UINT16  vendoe_data2;
+  UINT16  sectors_per_track;
+  UINT16  vendor_specific_7_9[3];
+  CHAR8   SerialNo[20];               /* ASCII */
+  UINT16  vendor_specific_20_21[2];
+  UINT16  ecc_bytes_available;
+  CHAR8   FirmwareVer[8];             /* ASCII */
+  CHAR8   ModelName[40];              /* ASCII */
+  UINT16  multi_sector_cmd_max_sct_cnt;
+  UINT16  reserved_48;
+  UINT16  capabilities;
+  UINT16  reserved_50;
+  UINT16  pio_cycle_timing;
+  UINT16  reserved_52;
+  UINT16  field_validity;
+  UINT16  current_cylinders;
+  UINT16  current_heads;
+  UINT16  current_sectors;
+  UINT16  CurrentCapacityLsb;
+  UINT16  CurrentCapacityMsb;
+  UINT16  reserved_59;
+  UINT16  user_addressable_sectors_lo;
+  UINT16  user_addressable_sectors_hi;
+  UINT16  reserved_62;
+  UINT16  multi_word_dma_mode;
+  UINT16  advanced_pio_modes;
+  UINT16  min_multi_word_dma_cycle_time;
+  UINT16  rec_multi_word_dma_cycle_time;
+  UINT16  min_pio_cycle_time_without_flow_control;
+  UINT16  min_pio_cycle_time_with_flow_control;
+  UINT16  reserved_69_79[11];
+  UINT16  major_version_no;
+  UINT16  minor_version_no;
+  UINT16  reserved_82_127[46];
+  UINT16  security_status;
+  UINT16  vendor_data_129_159[31];
+  UINT16  reserved_160_255[96];
+} IDENTIFY;
+
+typedef struct {
+  UINT8 peripheral_type;
+  UINT8 RMB;
+  UINT8 version;
+  UINT8 response_data_format;
+  UINT8 addnl_length;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 vendor_info[8];
+  UINT8 product_id[12];
+  UINT8 eeprom_product_code[4];
+  UINT8 firmware_rev_level[4];
+  UINT8 firmware_sub_rev_level[1];
+  UINT8 reserved_37;
+  UINT8 reserved_38;
+  UINT8 reserved_39;
+  UINT8 max_capacity_hi;
+  UINT8 max_capacity_mid;
+  UINT8 max_capacity_lo;
+  UINT8 reserved_43_95[95 - 43 + 1];
+  UINT8 vendor_id[20];
+  UINT8 eeprom_drive_sno[12];
+} INQUIRY_DATA;
+
+typedef struct {
+  UINT8 error_code : 7;
+  UINT8 valid : 1;
+  UINT8 reserved_1;
+  UINT8 sense_key : 4;
+  UINT8 reserved_21 : 1;
+  UINT8 ILI : 1;
+  UINT8 reserved_22 : 2;
+  UINT8 vendor_specific_3;
+  UINT8 vendor_specific_4;
+  UINT8 vendor_specific_5;
+  UINT8 vendor_specific_6;
+  UINT8 addnl_sense_length;           // n - 7
+  UINT8 vendor_specific_8;
+  UINT8 vendor_specific_9;
+  UINT8 vendor_specific_10;
+  UINT8 vendor_specific_11;
+  UINT8 addnl_sense_code;             // mandatory
+  UINT8 addnl_sense_code_qualifier;   // mandatory
+  UINT8 field_replaceable_unit_code;  // optional
+  UINT8 reserved_15;
+  UINT8 reserved_16;
+  UINT8 reserved_17;
+  //
+  // Followed by additional sense bytes     : FIXME
+  //
+} REQUEST_SENSE_DATA;
+
+typedef struct {
+  UINT8 LastLba3;
+  UINT8 LastLba2;
+  UINT8 LastLba1;
+  UINT8 LastLba0;
+  UINT8 BlockSize3;
+  UINT8 BlockSize2;
+  UINT8 BlockSize1;
+  UINT8 BlockSize0;
+} READ_CAPACITY_DATA;
+
+typedef struct {
+  UINT8 reserved_0;
+  UINT8 reserved_1;
+  UINT8 reserved_2;
+  UINT8 Capacity_Length;
+  UINT8 LastLba3;
+  UINT8 LastLba2;
+  UINT8 LastLba1;
+  UINT8 LastLba0;
+  UINT8 DesCode : 2;
+  UINT8 reserved_9 : 6;
+  UINT8 BlockSize2;
+  UINT8 BlockSize1;
+  UINT8 BlockSize0;
+} READ_FORMAT_CAPACITY_DATA;
+
+#pragma pack()
+//
+// ATAPI Command
+//
+#define ATAPI_SOFT_RESET_CMD      0x08
+#define PACKET_CMD                0xA0
+#define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
+#define ATAPI_SERVICE_CMD         0xA2
+
+//
+// ATAPI Packet Command
+//
+#pragma pack(1)
+
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1;
+  UINT8 reserved_2;
+  UINT8 reserved_3;
+  UINT8 reserved_4;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 reserved_8;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} TEST_UNIT_READY_CMD;
+
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1 : 4;
+  UINT8 lun : 4;
+  UINT8 page_code;
+  UINT8 reserved_3;
+  UINT8 allocation_length;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 reserved_8;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} INQUIRY_CMD;
+
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1 : 4;
+  UINT8 lun : 4;
+  UINT8 reserved_2;
+  UINT8 reserved_3;
+  UINT8 allocation_length;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 reserved_8;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} REQUEST_SENSE_CMD;
+
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1 : 5;
+  UINT8 lun : 3;
+  UINT8 Lba0;
+  UINT8 Lba1;
+  UINT8 Lba2;
+  UINT8 Lba3;
+  UINT8 reserved_6;
+  UINT8 TranLen0;
+  UINT8 TranLen1;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} READ10_CMD;
+
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1;
+  UINT8 reserved_2;
+  UINT8 reserved_3;
+  UINT8 reserved_4;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 allocation_length_hi;
+  UINT8 allocation_length_lo;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} READ_FORMAT_CAP_CMD;
+
+typedef struct {
+  UINT8 peripheral_type;
+  UINT8 RMB;
+  UINT8 version;
+  UINT8 response_data_format;
+  UINT8 addnl_length;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 vendor_info[8];
+  UINT8 product_id[12];
+  UINT8 eeprom_product_code[4];
+  UINT8 firmware_rev_level[4];
+} USB_INQUIRY_DATA;
+
+typedef union {
+  UINT16              Data16[6];
+  TEST_UNIT_READY_CMD TestUnitReady;
+  READ10_CMD          Read10;
+  REQUEST_SENSE_CMD   RequestSence;
+  INQUIRY_CMD         Inquiry;
+  READ_FORMAT_CAP_CMD ReadFormatCapacity;
+} ATAPI_PACKET_COMMAND;
+
+#pragma pack()
+//
+// Packet Command Code
+//
+#define TEST_UNIT_READY       0x00
+#define REQUEST_SENSE         0x03
+#define INQUIRY               0x12
+#define READ_FORMAT_CAPACITY  0x23
+#define READ_CAPACITY         0x25
+#define READ_10               0x28
+
+#define DEFAULT_CTL           (0x0a)  // default content of device control register, disable INT
+#define DEFAULT_CMD           (0xa0)
+
+#define MAX_ATAPI_BYTE_COUNT  (0xfffe)
+
+//
+// Sense Key
+//
+#define REQUEST_SENSE_ERROR (0x70)
+#define SK_NO_SENSE         (0x0)
+#define SK_RECOVERY_ERROR   (0x1)
+#define SK_NOT_READY        (0x2)
+#define SK_MEDIUM_ERROR     (0x3)
+#define SK_HARDWARE_ERROR   (0x4)
+#define SK_ILLEGAL_REQUEST  (0x5)
+#define SK_UNIT_ATTENTION   (0x6)
+#define SK_DATA_PROTECT     (0x7)
+#define SK_BLANK_CHECK      (0x8)
+#define SK_VENDOR_SPECIFIC  (0x9)
+#define SK_RESERVED_A       (0xA)
+#define SK_ABORT            (0xB)
+#define SK_RESERVED_C       (0xC)
+#define SK_OVERFLOW         (0xD)
+#define SK_MISCOMPARE       (0xE)
+#define SK_RESERVED_F       (0xF)
+
+//
+// Additional Sense Codes
+//
+#define ASC_NOT_READY                   (0x04)
+#define ASC_MEDIA_ERR1                  (0x10)
+#define ASC_MEDIA_ERR2                  (0x11)
+#define ASC_MEDIA_ERR3                  (0x14)
+#define ASC_MEDIA_ERR4                  (0x30)
+#define ASC_MEDIA_UPSIDE_DOWN           (0x06)
+#define ASC_INVALID_CMD                 (0x20)
+#define ASC_LBA_OUT_OF_RANGE            (0x21)
+#define ASC_INVALID_FIELD               (0x24)
+#define ASC_WRITE_PROTECTED             (0x27)
+#define ASC_MEDIA_CHANGE                (0x28)
+#define ASC_RESET                       (0x29)  /* Power On Reset or Bus Reset occurred */
+#define ASC_ILLEGAL_FIELD               (0x26)
+#define ASC_NO_MEDIA                    (0x3A)
+#define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define ASCQ_IN_PROGRESS  (0x01)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci.h

@@ -0,0 +1,31 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+    pci.h
+
+Abstract:
+    Support for PCI standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI_H
+#define _PCI_H
+
+#include "pci22.h"
+#include "pci23.h"
+#include "pci30.h"
+#include "EfiPci.h"
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h

@@ -0,0 +1,555 @@
+/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+    pci22.h
+
+Abstract:
+    Support for PCI 2.2 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI22_H
+#define _PCI22_H
+
+#define PCI_MAX_SEGMENT 0
+
+#define PCI_MAX_BUS     255
+
+#define PCI_MAX_DEVICE  31
+#define PCI_MAX_FUNC    7
+
+//
+// Command
+//
+#define PCI_VGA_PALETTE_SNOOP_DISABLED  0x20
+
+#pragma pack(push, 1)
+typedef struct {
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT16  Command;
+  UINT16  Status;
+  UINT8   RevisionID;
+  UINT8   ClassCode[3];
+  UINT8   CacheLineSize;
+  UINT8   LatencyTimer;
+  UINT8   HeaderType;
+  UINT8   BIST;
+} PCI_DEVICE_INDEPENDENT_REGION;
+
+typedef struct {
+  UINT32  Bar[6];
+  UINT32  CISPtr;
+  UINT16  SubsystemVendorID;
+  UINT16  SubsystemID;
+  UINT32  ExpansionRomBar;
+  UINT8   CapabilityPtr;
+  UINT8   Reserved1[3];
+  UINT32  Reserved2;
+  UINT8   InterruptLine;
+  UINT8   InterruptPin;
+  UINT8   MinGnt;
+  UINT8   MaxLat;
+} PCI_DEVICE_HEADER_TYPE_REGION;
+
+typedef struct {
+  PCI_DEVICE_INDEPENDENT_REGION Hdr;
+  PCI_DEVICE_HEADER_TYPE_REGION Device;
+} PCI_TYPE00;
+
+typedef struct {
+  UINT32  Bar[2];
+  UINT8   PrimaryBus;
+  UINT8   SecondaryBus;
+  UINT8   SubordinateBus;
+  UINT8   SecondaryLatencyTimer;
+  UINT8   IoBase;
+  UINT8   IoLimit;
+  UINT16  SecondaryStatus;
+  UINT16  MemoryBase;
+  UINT16  MemoryLimit;
+  UINT16  PrefetchableMemoryBase;
+  UINT16  PrefetchableMemoryLimit;
+  UINT32  PrefetchableBaseUpper32;
+  UINT32  PrefetchableLimitUpper32;
+  UINT16  IoBaseUpper16;
+  UINT16  IoLimitUpper16;
+  UINT8   CapabilityPtr;
+  UINT8   Reserved[3];
+  UINT32  ExpansionRomBAR;
+  UINT8   InterruptLine;
+  UINT8   InterruptPin;
+  UINT16  BridgeControl;
+} PCI_BRIDGE_CONTROL_REGISTER;
+
+typedef struct {
+  PCI_DEVICE_INDEPENDENT_REGION Hdr;
+  PCI_BRIDGE_CONTROL_REGISTER   Bridge;
+} PCI_TYPE01;
+
+typedef union {
+  PCI_TYPE00  Device;
+  PCI_TYPE01  Bridge;
+} PCI_TYPE_GENERIC;
+
+typedef struct {
+  UINT32  CardBusSocketReg; // Cardus Socket/ExCA Base
+  // Address Register
+  //
+  UINT16  Reserved;
+  UINT16  SecondaryStatus;      // Secondary Status
+  UINT8   PciBusNumber;         // PCI Bus Number
+  UINT8   CardBusBusNumber;     // CardBus Bus Number
+  UINT8   SubordinateBusNumber; // Subordinate Bus Number
+  UINT8   CardBusLatencyTimer;  // CardBus Latency Timer
+  UINT32  MemoryBase0;          // Memory Base Register 0
+  UINT32  MemoryLimit0;         // Memory Limit Register 0
+  UINT32  MemoryBase1;
+  UINT32  MemoryLimit1;
+  UINT32  IoBase0;
+  UINT32  IoLimit0;             // I/O Base Register 0
+  UINT32  IoBase1;              // I/O Limit Register 0
+  UINT32  IoLimit1;
+  UINT8   InterruptLine;        // Interrupt Line
+  UINT8   InterruptPin;         // Interrupt Pin
+  UINT16  BridgeControl;        // Bridge Control
+} PCI_CARDBUS_CONTROL_REGISTER;
+
+//
+// Definitions of PCI class bytes and manipulation macros.
+//
+#define PCI_CLASS_OLD                 0x00
+#define PCI_CLASS_OLD_OTHER           0x00
+#define PCI_CLASS_OLD_VGA             0x01
+
+#define PCI_CLASS_MASS_STORAGE        0x01
+#define PCI_CLASS_MASS_STORAGE_SCSI   0x00
+#define PCI_CLASS_MASS_STORAGE_IDE    0x01  // obsolete
+#define PCI_CLASS_IDE                 0x01
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
+#define PCI_CLASS_MASS_STORAGE_IPI    0x03
+#define PCI_CLASS_MASS_STORAGE_RAID   0x04
+#define PCI_CLASS_MASS_STORAGE_OTHER  0x80
+
+#define PCI_CLASS_NETWORK             0x02
+#define PCI_CLASS_NETWORK_ETHERNET    0x00
+#define PCI_CLASS_ETHERNET            0x00  // obsolete
+#define PCI_CLASS_NETWORK_TOKENRING   0x01
+#define PCI_CLASS_NETWORK_FDDI        0x02
+#define PCI_CLASS_NETWORK_ATM         0x03
+#define PCI_CLASS_NETWORK_ISDN        0x04
+#define PCI_CLASS_NETWORK_OTHER       0x80
+
+#define PCI_CLASS_DISPLAY             0x03
+#define PCI_CLASS_DISPLAY_CTRL        0x03  // obsolete
+#define PCI_CLASS_DISPLAY_VGA         0x00
+#define PCI_CLASS_VGA                 0x00  // obsolete
+#define PCI_CLASS_DISPLAY_XGA         0x01
+#define PCI_CLASS_DISPLAY_3D          0x02
+#define PCI_CLASS_DISPLAY_OTHER       0x80
+#define PCI_CLASS_DISPLAY_GFX         0x80
+#define PCI_CLASS_GFX                 0x80  // obsolete
+
+#define PCI_CLASS_BRIDGE              0x06
+#define PCI_CLASS_BRIDGE_HOST         0x00
+#define PCI_CLASS_BRIDGE_ISA          0x01
+#define PCI_CLASS_ISA                 0x01  // obsolete
+#define PCI_CLASS_BRIDGE_EISA         0x02
+#define PCI_CLASS_BRIDGE_MCA          0x03
+#define PCI_CLASS_BRIDGE_P2P          0x04
+#define PCI_CLASS_BRIDGE_PCMCIA       0x05
+#define PCI_CLASS_BRIDGE_NUBUS        0x06
+#define PCI_CLASS_BRIDGE_CARDBUS      0x07
+#define PCI_CLASS_BRIDGE_RACEWAY      0x08
+#define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
+#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete
+
+#define PCI_CLASS_SCC                 0x07  // Simple communications controllers 
+#define PCI_SUBCLASS_SERIAL           0x00
+#define PCI_IF_GENERIC_XT             0x00
+#define PCI_IF_16450                  0x01
+#define PCI_IF_16550                  0x02
+#define PCI_IF_16650                  0x03
+#define PCI_IF_16750                  0x04
+#define PCI_IF_16850                  0x05
+#define PCI_IF_16950                  0x06
+#define PCI_SUBCLASS_PARALLEL         0x01
+#define PCI_IF_PARALLEL_PORT          0x00
+#define PCI_IF_BI_DIR_PARALLEL_PORT   0x01
+#define PCI_IF_ECP_PARALLEL_PORT      0x02
+#define PCI_IF_1284_CONTROLLER        0x03
+#define PCI_IF_1284_DEVICE            0xFE
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
+#define PCI_SUBCLASS_MODEM            0x03
+#define PCI_IF_GENERIC_MODEM          0x00
+#define PCI_IF_16450_MODEM            0x01
+#define PCI_IF_16550_MODEM            0x02
+#define PCI_IF_16650_MODEM            0x03
+#define PCI_IF_16750_MODEM            0x04
+#define PCI_SUBCLASS_OTHER            0x80
+
+#define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
+#define PCI_SUBCLASS_PIC              0x00
+#define PCI_IF_8259_PIC               0x00
+#define PCI_IF_ISA_PIC                0x01
+#define PCI_IF_EISA_PIC               0x02
+#define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.  
+#define PCI_IF_APIC_CONTROLLER2       0x20 
+#define PCI_SUBCLASS_TIMER            0x02
+#define PCI_IF_8254_TIMER             0x00
+#define PCI_IF_ISA_TIMER              0x01
+#define PCI_EISA_TIMER                0x02
+#define PCI_SUBCLASS_RTC              0x03
+#define PCI_IF_GENERIC_RTC            0x00
+#define PCI_IF_ISA_RTC                0x00
+#define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller
+
+#define PCI_CLASS_INPUT_DEVICE        0x09
+#define PCI_SUBCLASS_KEYBOARD         0x00
+#define PCI_SUBCLASS_PEN              0x01
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
+#define PCI_SUBCLASS_SCAN_CONTROLLER  0x03
+#define PCI_SUBCLASS_GAMEPORT         0x04
+
+#define PCI_CLASS_DOCKING_STATION     0x0A
+
+#define PCI_CLASS_PROCESSOR           0x0B
+#define PCI_SUBCLASS_PROC_386         0x00
+#define PCI_SUBCLASS_PROC_486         0x01
+#define PCI_SUBCLASS_PROC_PENTIUM     0x02
+#define PCI_SUBCLASS_PROC_ALPHA       0x10
+#define PCI_SUBCLASS_PROC_POWERPC     0x20
+#define PCI_SUBCLASS_PROC_MIPS        0x30
+#define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor
+
+#define PCI_CLASS_SERIAL              0x0C
+#define PCI_CLASS_SERIAL_FIREWIRE     0x00
+#define PCI_CLASS_SERIAL_ACCESS_BUS   0x01
+#define PCI_CLASS_SERIAL_SSA          0x02
+#define PCI_CLASS_SERIAL_USB          0x03
+#define PCI_IF_EHCI                   0x20
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define PCI_CLASS_SERIAL_SMB          0x05
+
+#define PCI_CLASS_WIRELESS            0x0D
+#define PCI_SUBCLASS_IRDA             0x00
+#define PCI_SUBCLASS_IR               0x01
+#define PCI_SUBCLASS_RF               0x02
+
+#define PCI_CLASS_INTELLIGENT_IO      0x0E
+
+#define PCI_CLASS_SATELLITE           0x0F
+#define PCI_SUBCLASS_TV               0x01
+#define PCI_SUBCLASS_AUDIO            0x02
+#define PCI_SUBCLASS_VOICE            0x03
+#define PCI_SUBCLASS_DATA             0x04
+
+#define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller
+#define PCI_SUBCLASS_NET_COMPUT       0x00
+#define PCI_SUBCLASS_ENTERTAINMENT    0x10 
+
+#define PCI_CLASS_DPIO                0x11
+
+#define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
+#define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
+#define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
+
+#define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
+#define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
+#define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
+#define IS_PCI_GFX(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
+#define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
+#define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
+#define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
+#define IS_PCI_SCSI(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
+#define IS_PCI_RAID(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
+#define IS_PCI_LPC(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
+#define IS_PCI_ISA_PDECODE(_p)        IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
+#define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
+#define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
+#define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
+#define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
+
+#define HEADER_TYPE_DEVICE            0x00
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
+#define HEADER_TYPE_CARDBUS_BRIDGE    0x02
+
+#define HEADER_TYPE_MULTI_FUNCTION    0x80
+#define HEADER_LAYOUT_CODE            0x7f
+
+#define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
+#define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
+#define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
+
+#define PCI_DEVICE_ROMBAR             0x30
+#define PCI_BRIDGE_ROMBAR             0x38
+
+#define PCI_MAX_BAR                   0x0006
+#define PCI_MAX_CONFIG_OFFSET         0x0100
+
+#define PCI_VENDOR_ID_OFFSET                        0x00
+#define PCI_DEVICE_ID_OFFSET                        0x02
+#define PCI_COMMAND_OFFSET                          0x04
+#define PCI_PRIMARY_STATUS_OFFSET                   0x06
+#define PCI_REVISION_ID_OFFSET                      0x08
+#define PCI_CLASSCODE_OFFSET                        0x09
+#define PCI_SUBCLASSCODE_OFFSET                     0x0A
+#define PCI_CACHELINE_SIZE_OFFSET                   0x0C
+#define PCI_LATENCY_TIMER_OFFSET                    0x0D
+#define PCI_HEADER_TYPE_OFFSET                      0x0E
+#define PCI_BIST_OFFSET                             0x0F
+#define PCI_BASE_ADDRESSREG_OFFSET                  0x10
+#define PCI_CARDBUS_CIS_OFFSET                      0x28
+#define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
+#define PCI_SID_OFFSET                              0x2E // SubSystem ID
+#define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
+#define PCI_EXPANSION_ROM_BASE                      0x30
+#define PCI_CAPBILITY_POINTER_OFFSET                0x34
+#define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register
+#define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register
+#define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register
+#define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register
+
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
+
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
+
+//
+// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
+//
+#define PCI_INT_LINE_UNKNOWN                    0xFF               
+
+
+typedef struct {
+  UINT32  Reg : 8;
+  UINT32  Func : 3;
+  UINT32  Dev : 5;
+  UINT32  Bus : 8;
+  UINT32  Reserved : 7;
+  UINT32  Enable : 1;
+} PCI_CONFIG_ACCESS_CF8;
+
+#pragma pack()
+
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
+#define PCI_DATA_STRUCTURE_SIGNATURE                    EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
+#define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
+#define PCI_CODE_TYPE_EFI_IMAGE                         0x03
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001
+
+#define EFI_PCI_COMMAND_IO_SPACE                        0x0001
+#define EFI_PCI_COMMAND_MEMORY_SPACE                    0x0002
+#define EFI_PCI_COMMAND_BUS_MASTER                      0x0004
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE                   0x0008
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     0x0010
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               0x0020
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            0x0040
+#define EFI_PCI_COMMAND_STEPPING_CONTROL                0x0080
+#define EFI_PCI_COMMAND_SERR                            0x0100
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               0x0200
+
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    0x0001
+#define EFI_PCI_BRIDGE_CONTROL_SERR                     0x0002
+#define EFI_PCI_BRIDGE_CONTROL_ISA                      0x0004
+#define EFI_PCI_BRIDGE_CONTROL_VGA                      0x0008
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16                   0x0010
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             0x0020
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      0x0040
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        0x0080
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    0x0100
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  0x0200
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             0x0400
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       0x0800
+
+//
+// Following are the PCI-CARDBUS bridge control bit
+//
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE       0x0080
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE   0x0100
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE   0x0200
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
+
+//
+// Following are the PCI status control bit
+//
+#define EFI_PCI_STATUS_CAPABILITY             0x0010
+#define EFI_PCI_STATUS_66MZ_CAPABLE           0x0020
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE     0x0080
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR      0x0100
+
+#define EFI_PCI_CAPABILITY_PTR                0x34
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
+
+#pragma pack(1)
+typedef struct {
+  UINT16  Signature;    // 0xaa55
+  UINT8   Reserved[0x16];
+  UINT16  PcirOffset;
+} PCI_EXPANSION_ROM_HEADER;
+
+typedef struct {
+  UINT16  Signature;    // 0xaa55
+  UINT8   Size512;
+  UINT8   InitEntryPoint[3];
+  UINT8   Reserved[0x12];
+  UINT16  PcirOffset;
+} EFI_LEGACY_EXPANSION_ROM_HEADER;
+
+typedef struct {
+  UINT32  Signature;    // "PCIR"
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT16  Reserved0;
+  UINT16  Length;
+  UINT8   Revision;
+  UINT8   ClassCode[3];
+  UINT16  ImageLength;
+  UINT16  CodeRevision;
+  UINT8   CodeType;
+  UINT8   Indicator;
+  UINT16  Reserved1;
+} PCI_DATA_STRUCTURE;
+
+//
+// PCI Capability List IDs and records
+//
+#define EFI_PCI_CAPABILITY_ID_PMI     0x01
+#define EFI_PCI_CAPABILITY_ID_AGP     0x02
+#define EFI_PCI_CAPABILITY_ID_VPD     0x03
+#define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
+#define EFI_PCI_CAPABILITY_ID_MSI     0x05
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
+#define EFI_PCI_CAPABILITY_ID_PCIX    0x07
+
+typedef struct {
+  UINT8 CapabilityID;
+  UINT8 NextItemPtr;
+} EFI_PCI_CAPABILITY_HDR;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_PMI
+//
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  PMC;
+  UINT16                  PMCSR;
+  UINT8                   BridgeExtention;
+  UINT8                   Data;
+} EFI_PCI_CAPABILITY_PMI;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_AGP
+//
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT8                   Rev;
+  UINT8                   Reserved;
+  UINT32                  Status;
+  UINT32                  Command;
+} EFI_PCI_CAPABILITY_AGP;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_VPD
+//
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  AddrReg;
+  UINT32                  DataReg;
+} EFI_PCI_CAPABILITY_VPD;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_SLOTID
+//
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT8                   ExpnsSlotReg;
+  UINT8                   ChassisNo;
+} EFI_PCI_CAPABILITY_SLOTID;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_MSI
+//
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  MsgCtrlReg;
+  UINT32                  MsgAddrReg;
+  UINT16                  MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI32;
+
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  MsgCtrlReg;
+  UINT32                  MsgAddrRegLsdw;
+  UINT32                  MsgAddrRegMsdw;
+  UINT16                  MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI64;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
+//
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  //
+  // not finished - fields need to go here
+  //
+} EFI_PCI_CAPABILITY_HOTPLUG;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_PCIX
+//
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  CommandReg;
+  UINT32                  StatusReg;
+} EFI_PCI_CAPABILITY_PCIX;
+
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  SecStatusReg;
+  UINT32                  StatusReg;
+  UINT32                  SplitTransCtrlRegUp;
+  UINT32                  SplitTransCtrlRegDn;
+} EFI_PCI_CAPABILITY_PCIX_BRDG;
+
+#define DEVICE_ID_NOCARE    0xFFFF
+
+#define PCI_ACPI_UNUSED     0
+#define PCI_BAR_NOCHANGE    0
+#define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFF
+#define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFE
+#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFD
+#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFC
+
+#define PCI_BAR_IDX0        0x00
+#define PCI_BAR_IDX1        0x01
+#define PCI_BAR_IDX2        0x02
+#define PCI_BAR_IDX3        0x03
+#define PCI_BAR_IDX4        0x04
+#define PCI_BAR_IDX5        0x05
+#define PCI_BAR_ALL         0xFF
+
+#pragma pack(pop)
+
+//
+// NOTE: The following header files are included here for
+// compatibility consideration.
+//
+#include "EfiPci.h"
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci23.h

@@ -0,0 +1,31 @@
+/*++
+
+Copyright (c) 2006 - 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+    pci23.h
+
+Abstract:
+    Support for PCI 2.3 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI23_H
+#define _PCI23_H
+
+#include "pci22.h"
+
+#define PCI_EXP_MAX_CONFIG_OFFSET     0x1000
+#define EFI_PCI_CAPABILITY_ID_PCIEXP  0x10
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci30.h

@@ -0,0 +1,52 @@
+/*++
+
+Copyright (c) 2006 - 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+    pci30.h
+
+Abstract:
+    Support for PCI 3.0 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI30_H
+#define _PCI30_H
+
+#include "pci23.h"
+
+#define PCI_CLASS_MASS_STORAGE_SATADPA   0x06
+#define PCI_CLASS_MASS_STORAGE_AHCI      PCI_CLASS_MASS_STORAGE_SATADPA
+
+#pragma pack(push, 1)
+
+typedef struct {
+  UINT32  Signature;    // "PCIR"
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT16  DeviceListOffset;
+  UINT16  Length;
+  UINT8   Revision;
+  UINT8   ClassCode[3];
+  UINT16  ImageLength;
+  UINT16  CodeRevision;
+  UINT8   CodeType;
+  UINT8   Indicator;
+  UINT16  MaxRuntimeImageLength;
+  UINT16  ConfigUtilityCodeHeaderOffset;
+  UINT16  DMTFCLPEntryPointOffset;
+} PCI_3_0_DATA_STRUCTURE;
+
+#pragma pack(pop)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h

@@ -0,0 +1,292 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                  
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+    scsi.h
+    
+Abstract: 
+    support for SCSI standard
+
+Revision History
+--*/
+
+#ifndef _SCSI_H
+#define _SCSI_H
+
+//
+// SCSI command OP Code
+//
+//
+// Commands for all device types
+//
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
+#define EFI_SCSI_OP_COMPARE           0x39
+#define EFI_SCSI_OP_COPY              0x18
+#define EFI_SCSI_OP_COPY_VERIFY       0x3a
+#define EFI_SCSI_OP_INQUIRY           0x12
+#define EFI_SCSI_OP_LOG_SELECT        0x4c
+#define EFI_SCSI_OP_LOG_SENSE         0x4d
+#define EFI_SCSI_OP_MODE_SEL6         0x15
+#define EFI_SCSI_OP_MODE_SEL10        0x55
+#define EFI_SCSI_OP_MODE_SEN6         0x1a
+#define EFI_SCSI_OP_MODE_SEN10        0x5a
+#define EFI_SCSI_OP_READ_BUFFER       0x3c
+#define EFI_SCSI_OP_REQUEST_SENSE     0x03
+#define EFI_SCSI_OP_SEND_DIAG         0x1d
+#define EFI_SCSI_OP_TEST_UNIT_READY   0x00
+#define EFI_SCSI_OP_WRITE_BUFF        0x3b
+
+//
+// Commands unique to Direct Access Devices
+//
+#define EFI_SCSI_OP_COMPARE         0x39
+#define EFI_SCSI_OP_FORMAT          0x04
+#define EFI_SCSI_OP_LOCK_UN_CACHE   0x36
+#define EFI_SCSI_OP_PREFETCH        0x34
+#define EFI_SCSI_OP_MEDIA_REMOVAL   0x1e
+#define EFI_SCSI_OP_READ6           0x08
+#define EFI_SCSI_OP_READ10          0x28
+#define EFI_SCSI_OP_READ_CAPACITY   0x25
+#define EFI_SCSI_OP_READ_DEFECT     0x37
+#define EFI_SCSI_OP_READ_LONG       0x3e
+#define EFI_SCSI_OP_REASSIGN_BLK    0x07
+#define EFI_SCSI_OP_RECEIVE_DIAG    0x1c
+#define EFI_SCSI_OP_RELEASE         0x17
+#define EFI_SCSI_OP_REZERO          0x01
+#define EFI_SCSI_OP_SEARCH_DATA_E   0x31
+#define EFI_SCSI_OP_SEARCH_DATA_H   0x30
+#define EFI_SCSI_OP_SEARCH_DATA_L   0x32
+#define EFI_SCSI_OP_SEEK6           0x0b
+#define EFI_SCSI_OP_SEEK10          0x2b
+#define EFI_SCSI_OP_SEND_DIAG       0x1d
+#define EFI_SCSI_OP_SET_LIMIT       0x33
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
+#define EFI_SCSI_OP_SYNC_CACHE      0x35
+#define EFI_SCSI_OP_VERIFY          0x2f
+#define EFI_SCSI_OP_WRITE6          0x0a
+#define EFI_SCSI_OP_WRITE10         0x2a
+#define EFI_SCSI_OP_WRITE_VERIFY    0x2e
+#define EFI_SCSI_OP_WRITE_LONG      0x3f
+#define EFI_SCSI_OP_WRITE_SAME      0x41
+
+//
+// Commands unique to Sequential Access Devices
+//
+#define EFI_SCSI_OP_ERASE             0x19
+#define EFI_SCSI_OP_LOAD_UNLOAD       0x1b
+#define EFI_SCSI_OP_LOCATE            0x2b
+#define EFI_SCSI_OP_READ_BLOCK_LIMIT  0x05
+#define EFI_SCSI_OP_READ_POS          0x34
+#define EFI_SCSI_OP_READ_REVERSE      0x0f
+#define EFI_SCSI_OP_RECOVER_BUF_DATA  0x14
+#define EFI_SCSI_OP_RESERVE_UNIT      0x16
+#define EFI_SCSI_OP_REWIND            0x01
+#define EFI_SCSI_OP_SPACE             0x11
+#define EFI_SCSI_OP_VERIFY_TAPE       0x13
+#define EFI_SCSI_OP_WRITE_FILEMARK    0x10
+
+//
+// Commands unique to Printer Devices
+//
+#define EFI_SCSI_OP_PRINT       0x0a
+#define EFI_SCSI_OP_SLEW_PRINT  0x0b
+#define EFI_SCSI_OP_STOP_PRINT  0x1b
+#define EFI_SCSI_OP_SYNC_BUFF   0x10
+
+//
+// Commands unique to Processor Devices
+//
+#define EFI_SCSI_OP_RECEIVE 0x08
+#define EFI_SCSI_OP_SEND    0x0a
+
+//
+// Commands unique to Write-Once Devices
+//
+#define EFI_SCSI_OP_MEDIUM_SCAN     0x38
+#define EFI_SCSI_OP_SEARCH_DAT_E10  0x31
+#define EFI_SCSI_OP_SEARCH_DAT_E12  0xb1
+#define EFI_SCSI_OP_SEARCH_DAT_H10  0x30
+#define EFI_SCSI_OP_SEARCH_DAT_H12  0xb0
+#define EFI_SCSI_OP_SEARCH_DAT_L10  0x32
+#define EFI_SCSI_OP_SEARCH_DAT_L12  0xb2
+#define EFI_SCSI_OP_SET_LIMIT10     0x33
+#define EFI_SCSI_OP_SET_LIMIT12     0xb3
+#define EFI_SCSI_OP_VERIFY10        0x2f
+#define EFI_SCSI_OP_VERIFY12        0xaf
+#define EFI_SCSI_OP_WRITE12         0xaa
+#define EFI_SCSI_OP_WRITE_VERIFY10  0x2e
+#define EFI_SCSI_OP_WRITE_VERIFY12  0xae
+
+//
+// Commands unique to CD-ROM Devices
+//
+#define EFI_SCSI_OP_PLAY_AUD_10       0x45
+#define EFI_SCSI_OP_PLAY_AUD_12       0xa5
+#define EFI_SCSI_OP_PLAY_AUD_MSF      0x47
+#define EFI_SCSI_OP_PLAY_AUD_TKIN     0x48
+#define EFI_SCSI_OP_PLAY_TK_REL10     0x49
+#define EFI_SCSI_OP_PLAY_TK_REL12     0xa9
+#define EFI_SCSI_OP_READ_CD_CAPACITY  0x25
+#define EFI_SCSI_OP_READ_HEADER       0x44
+#define EFI_SCSI_OP_READ_SUB_CHANNEL  0x42
+#define EFI_SCSI_OP_READ_TOC          0x43
+
+//
+// Commands unique to Scanner Devices
+//
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
+#define EFI_SCSI_OP_GET_WINDOW        0x25
+#define EFI_SCSI_OP_OBJECT_POS        0x31
+#define EFI_SCSI_OP_SCAN              0x1b
+#define EFI_SCSI_OP_SET_WINDOW        0x24
+
+//
+// Commands unique to Optical Memory Devices
+//
+#define EFI_SCSI_OP_UPDATE_BLOCK  0x3d
+
+//
+// Commands unique to Medium Changer Devices
+//
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM   0xa6
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
+#define EFI_SCSI_OP_POS_TO_ELEMENT    0x2b
+#define EFI_SCSI_OP_REQUEST_VE_ADDR   0xb5
+#define EFI_SCSI_OP_SEND_VOL_TAG      0xb6
+
+//
+// Commands unique to Communition Devices
+//
+#define EFI_SCSI_OP_GET_MESSAGE6    0x08
+#define EFI_SCSI_OP_GET_MESSAGE10   0x28
+#define EFI_SCSI_OP_GET_MESSAGE12   0xa8
+#define EFI_SCSI_OP_SEND_MESSAGE6   0x0a
+#define EFI_SCSI_OP_SEND_MESSAGE10  0x2a
+#define EFI_SCSI_OP_SEND_MESSAGE12  0xaa
+
+//
+// SCSI Data Transfer Direction
+//
+#define EFI_SCSI_DATA_IN  0
+#define EFI_SCSI_DATA_OUT 1
+
+//
+// Peripheral Device Type Definitions
+//
+#define EFI_SCSI_TYPE_DISK          0x00  // Disk device
+#define EFI_SCSI_TYPE_TAPE          0x01  // Tape device
+#define EFI_SCSI_TYPE_PRINTER       0x02  // Printer
+#define EFI_SCSI_TYPE_PROCESSOR     0x03  // Processor
+#define EFI_SCSI_TYPE_WORM          0x04  // Write-once read-multiple
+#define EFI_SCSI_TYPE_CDROM         0x05  // CD-ROM device
+#define EFI_SCSI_TYPE_SCANNER       0x06  // Scanner device
+#define EFI_SCSI_TYPE_OPTICAL       0x07  // Optical memory device
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08  // Medium Changer device
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09  // Communications device
+#define EFI_SCSI_TYPE_RESERVED_LOW  0x0A  // Reserved (low)
+#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1E  // Reserved (high)
+#define EFI_SCSI_TYPE_UNKNOWN       0x1F  // Unknown or no device type
+#pragma pack(1)
+//
+// Data structures for scsi command use
+//
+typedef struct {
+  UINT8 Peripheral_Type : 5;
+  UINT8 Peripheral_Qualifier : 3;
+  UINT8 DeviceType_Modifier : 7;
+  UINT8 RMB : 1;
+  UINT8 Version;
+  UINT8 Response_Data_Format;
+  UINT8 Addnl_Length;
+  UINT8 Reserved_5_95[95 - 5 + 1];
+} EFI_SCSI_INQUIRY_DATA;
+
+typedef struct {
+  UINT8 Error_Code : 7;
+  UINT8 Valid : 1;
+  UINT8 Segment_Number;
+  UINT8 Sense_Key : 4;
+  UINT8 Reserved_21 : 1;
+  UINT8 ILI : 1;
+  UINT8 Reserved_22 : 2;
+  UINT8 Information_3_6[4];
+  UINT8 Addnl_Sense_Length;           // n - 7
+  UINT8 Vendor_Specific_8_11[4];
+  UINT8 Addnl_Sense_Code;             // mandatory
+  UINT8 Addnl_Sense_Code_Qualifier;   // mandatory
+  UINT8 Field_Replaceable_Unit_Code;  // optional
+  UINT8 Reserved_15_17[3];
+} EFI_SCSI_SENSE_DATA;
+
+typedef struct {
+  UINT8 LastLba3;
+  UINT8 LastLba2;
+  UINT8 LastLba1;
+  UINT8 LastLba0;
+  UINT8 BlockSize3;
+  UINT8 BlockSize2;
+  UINT8 BlockSize1;
+  UINT8 BlockSize0;
+} EFI_SCSI_DISK_CAPACITY_DATA;
+
+#pragma pack()
+//
+// Sense Key
+//
+#define EFI_SCSI_REQUEST_SENSE_ERROR  (0x70)
+#define EFI_SCSI_SK_NO_SENSE          (0x0)
+#define EFI_SCSI_SK_RECOVERY_ERROR    (0x1)
+#define EFI_SCSI_SK_NOT_READY         (0x2)
+#define EFI_SCSI_SK_MEDIUM_ERROR      (0x3)
+#define EFI_SCSI_SK_HARDWARE_ERROR    (0x4)
+#define EFI_SCSI_SK_ILLEGAL_REQUEST   (0x5)
+#define EFI_SCSI_SK_UNIT_ATTENTION    (0x6)
+#define EFI_SCSI_SK_DATA_PROTECT      (0x7)
+#define EFI_SCSI_SK_BLANK_CHECK       (0x8)
+#define EFI_SCSI_SK_VENDOR_SPECIFIC   (0x9)
+#define EFI_SCSI_SK_RESERVED_A        (0xA)
+#define EFI_SCSI_SK_ABORT             (0xB)
+#define EFI_SCSI_SK_RESERVED_C        (0xC)
+#define EFI_SCSI_SK_OVERFLOW          (0xD)
+#define EFI_SCSI_SK_MISCOMPARE        (0xE)
+#define EFI_SCSI_SK_RESERVED_F        (0xF)
+
+//
+// Additional Sense Codes
+//
+#define EFI_SCSI_ASC_NOT_READY                    (0x04)
+#define EFI_SCSI_ASC_MEDIA_ERR1                   (0x10)
+#define EFI_SCSI_ASC_MEDIA_ERR2                   (0x11)
+#define EFI_SCSI_ASC_MEDIA_ERR3                   (0x14)
+#define EFI_SCSI_ASC_MEDIA_ERR4                   (0x30)
+#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN            (0x06)
+#define EFI_SCSI_ASC_INVALID_CMD                  (0x20)
+#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE             (0x21)
+#define EFI_SCSI_ASC_INVALID_FIELD                (0x24)
+#define EFI_SCSI_ASC_WRITE_PROTECTED              (0x27)
+#define EFI_SCSI_ASC_MEDIA_CHANGE                 (0x28)
+#define EFI_SCSI_ASC_RESET                        (0x29)  /* Power On Reset or Bus Reset occurred */
+#define EFI_SCSI_ASC_ILLEGAL_FIELD                (0x26)
+#define EFI_SCSI_ASC_NO_MEDIA                     (0x3A)
+#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK  (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
+
+//
+// Max bytes needed to represent ID of a SCSI device
+//
+#define EFI_SCSI_TARGET_MAX_BYTES (0x10)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h

@@ -0,0 +1,293 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+    usb.h
+
+Abstract:
+    Support for USB 1.1 standard.
+
+
+
+
+Revision History
+
+--*/
+
+#ifndef _USB_H
+#define _USB_H
+//
+// USB Descriptor types
+//
+#define USB_DT_DEVICE     0x01
+#define USB_DT_CONFIG     0x02
+#define USB_DT_STRING     0x03
+#define USB_DT_INTERFACE  0x04
+#define USB_DT_ENDPOINT   0x05
+#define USB_DT_HUB        0x29
+#define USB_DT_HID        0x21
+
+//
+// USB request type
+//
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS    (0x01 << 5)
+#define USB_TYPE_VENDOR   (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+
+//
+// USB request targer device
+//
+#define USB_RECIP_DEVICE    0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT  0x02
+#define USB_RECIP_OTHER     0x03
+
+//
+// Request target types.
+//
+#define USB_RT_DEVICE     0x00
+#define USB_RT_INTERFACE  0x01
+#define USB_RT_ENDPOINT   0x02
+#define USB_RT_HUB        (USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT       (USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+//
+// USB Transfer Results
+//
+#define EFI_USB_NOERROR         0x00
+#define EFI_USB_ERR_NOTEXECUTE  0x01
+#define EFI_USB_ERR_STALL       0x02
+#define EFI_USB_ERR_BUFFER      0x04
+#define EFI_USB_ERR_BABBLE      0x08
+#define EFI_USB_ERR_NAK         0x10
+#define EFI_USB_ERR_CRC         0x20
+#define EFI_USB_ERR_TIMEOUT     0x40
+#define EFI_USB_ERR_BITSTUFF    0x80
+#define EFI_USB_ERR_SYSTEM      0x100
+
+//
+//Use 200 ms to increase the error handling response time
+//
+#define EFI_USB_INTERRUPT_DELAY 2000000
+
+//
+// USB transation direction
+//
+typedef enum {
+  EfiUsbDataIn,
+  EfiUsbDataOut,
+  EfiUsbNoData
+} EFI_USB_DATA_DIRECTION;
+
+//
+// Usb Data recipient type
+//
+typedef enum {
+  EfiUsbDevice,
+  EfiUsbInterface,
+  EfiUsbEndpoint
+} EFI_USB_RECIPIENT;
+
+typedef enum {
+  EfiUsbEndpointHalt,
+  EfiUsbDeviceRemoteWakeup
+} EFI_USB_STANDARD_FEATURE_SELECTOR;
+
+#pragma pack(1)
+//
+// Usb device request structure
+//
+typedef struct {
+  UINT8   RequestType;
+  UINT8   Request;
+  UINT16  Value;
+  UINT16  Index;
+  UINT16  Length;
+} EFI_USB_DEVICE_REQUEST;
+
+//
+// Standard USB request
+//
+#define USB_DEV_GET_STATUS                  0x00
+
+#define USB_DEV_CLEAR_FEATURE               0x01
+
+#define USB_DEV_SET_FEATURE                 0x03
+
+#define USB_DEV_SET_ADDRESS                 0x05
+#define USB_DEV_SET_ADDRESS_REQ_TYPE        0x00
+
+#define USB_DEV_GET_DESCRIPTOR              0x06
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE     0x80
+
+#define USB_DEV_SET_DESCRIPTOR              0x07
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE     0x00
+
+#define USB_DEV_GET_CONFIGURATION           0x08
+#define USB_DEV_GET_CONFIGURATION_REQ_TYPE  0x80
+
+#define USB_DEV_SET_CONFIGURATION           0x09
+#define USB_DEV_SET_CONFIGURATION_REQ_TYPE  0x00
+
+#define USB_DEV_GET_INTERFACE               0x0A
+#define USB_DEV_GET_INTERFACE_REQ_TYPE      0x81
+
+#define USB_DEV_SET_INTERFACE               0x0B
+#define USB_DEV_SET_INTERFACE_REQ_TYPE      0x01
+
+#define USB_DEV_SYNCH_FRAME                 0x0C
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE        0x82
+
+//
+// Device descriptor. refer USB1.1
+//
+typedef struct usb_device_descriptor {
+  UINT8   Length;
+  UINT8   DescriptorType;
+  UINT16  BcdUSB;
+  UINT8   DeviceClass;
+  UINT8   DeviceSubClass;
+  UINT8   DeviceProtocol;
+  UINT8   MaxPacketSize0;
+  UINT16  IdVendor;
+  UINT16  IdProduct;
+  UINT16  BcdDevice;
+  UINT8   StrManufacturer;
+  UINT8   StrProduct;
+  UINT8   StrSerialNumber;
+  UINT8   NumConfigurations;
+} EFI_USB_DEVICE_DESCRIPTOR;
+
+//
+// Endpoint descriptor
+//
+typedef struct {
+  UINT8   Length;
+  UINT8   DescriptorType;
+  UINT8   EndpointAddress;
+  UINT8   Attributes;
+  UINT16  MaxPacketSize;
+  UINT8   Interval;
+} EFI_USB_ENDPOINT_DESCRIPTOR;
+
+//
+// Interface descriptor
+//
+typedef struct {
+  UINT8 Length;
+  UINT8 DescriptorType;
+  UINT8 InterfaceNumber;
+  UINT8 AlternateSetting;
+  UINT8 NumEndpoints;
+  UINT8 InterfaceClass;
+  UINT8 InterfaceSubClass;
+  UINT8 InterfaceProtocol;
+  UINT8 Interface;
+} EFI_USB_INTERFACE_DESCRIPTOR;
+
+//
+// USB alternate setting
+//
+typedef struct {
+  EFI_USB_INTERFACE_DESCRIPTOR  *Interface;
+} USB_ALT_SETTING;
+
+//
+// Configuration descriptor
+//
+typedef struct {
+  UINT8   Length;
+  UINT8   DescriptorType;
+  UINT16  TotalLength;
+  UINT8   NumInterfaces;
+  UINT8   ConfigurationValue;
+  UINT8   Configuration;
+  UINT8   Attributes;
+  UINT8   MaxPower;
+} EFI_USB_CONFIG_DESCRIPTOR;
+
+//
+// Supported String Languages
+//
+typedef struct {
+  UINT8   Length;
+  UINT8   DescriptorType;
+  UINT16  SupportedLanID[1];
+} EFI_USB_SUPPORTED_LANGUAGES;
+
+//
+// String descriptor
+//
+typedef struct {
+  UINT8   Length;
+  UINT8   DescriptorType;
+  CHAR16  String[1];
+} EFI_USB_STRING_DESCRIPTOR;
+
+//
+// Hub descriptor
+//
+#define MAXBYTES  8
+typedef struct {
+  UINT8 Length;
+  UINT8 DescriptorType;
+  UINT8 NbrPorts;
+  UINT8 HubCharacteristics[2];
+  UINT8 PwrOn2PwrGood;
+  UINT8 HubContrCurrent;
+  UINT8 Filler[MAXBYTES];
+} EFI_USB_HUB_DESCRIPTOR;
+
+typedef struct {
+  UINT16  PortStatus;
+  UINT16  PortChangeStatus;
+} EFI_USB_PORT_STATUS;
+
+//
+// Constant value for Port Status & Port Change Status
+//
+#define USB_PORT_STAT_CONNECTION    0x0001
+#define USB_PORT_STAT_ENABLE        0x0002
+#define USB_PORT_STAT_SUSPEND       0x0004
+#define USB_PORT_STAT_OVERCURRENT   0x0008
+#define USB_PORT_STAT_RESET         0x0010
+#define USB_PORT_STAT_POWER         0x0100
+#define USB_PORT_STAT_LOW_SPEED     0x0200
+#define USB_PORT_STAT_HIGH_SPEED    0x0400
+#define USB_PORT_STAT_OWNER         0x0800
+
+#define USB_PORT_STAT_C_CONNECTION  0x0001
+#define USB_PORT_STAT_C_ENABLE      0x0002
+#define USB_PORT_STAT_C_SUSPEND     0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET       0x0010
+
+//
+// Used for set/clear port feature request
+//
+typedef enum {
+  EfiUsbPortEnable            = 1,
+  EfiUsbPortSuspend           = 2,
+  EfiUsbPortReset             = 4,
+  EfiUsbPortPower             = 8,
+  EfiUsbPortOwner             = 13,
+  EfiUsbPortConnectChange     = 16,
+  EfiUsbPortEnableChange      = 17,
+  EfiUsbPortSuspendChange     = 18,
+  EfiUsbPortOverCurrentChange = 19,
+  EfiUsbPortResetChange       = 20
+} EFI_USB_PORT_FEATURE;
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Ipf/EfiBind.h

@@ -0,0 +1,247 @@
+/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiBind.h
+
+Abstract:
+
+  Processor or Compiler specific defines and types for Intel Itanium(TM).
+  We are using the ANSI C 2000 _t type definitions for basic types.
+  This it technically a violation of the coding standard, but they
+  are used to make EfiTypes.h portable. Code other than EfiTypes.h
+  should never use any ANSI C 2000 _t integer types.
+
+--*/
+
+#ifndef _EFI_BIND_H_
+#define _EFI_BIND_H_
+
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)                 
+
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+
+
+
+//
+// Make sure we are useing the correct packing rules per EFI specification
+//
+#pragma pack()
+
+
+#if _MSC_EXTENSIONS 
+    
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft tools. Copied from the 
+// IA-32 version of efibind.h
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// Can not cast a function pointer to a data pointer. We need to do this on 
+// IPF to get access to the PLABEL.
+//
+#pragma warning ( disable : 4514 )
+
+//
+// Int64ShllMod32 unreferenced inline function
+//
+#pragma warning ( disable : 4054 )
+
+//
+// Unreferenced formal parameter - We are object oriented, so we pass This even
+//  if we  don't need them.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// This warning is caused by empty (after preprocessing) souce file.
+//
+#pragma warning ( disable : 4206 )
+
+//
+// Warning: The result of the unary '&' operator may be unaligned. Ignore it.
+//
+#pragma warning ( disable : 4366 )
+
+#endif
+
+
+#if (__STDC_VERSION__ < 199901L)
+  //
+  // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
+  //
+ 
+  #if _MSC_EXTENSIONS 
+    
+
+    //
+    // use Microsoft C complier dependent interger width types 
+    //
+    typedef unsigned __int64    uint64_t;
+    typedef __int64             int64_t;
+    typedef unsigned __int32    uint32_t;
+    typedef __int32             int32_t;
+    typedef unsigned short      uint16_t;
+    typedef short               int16_t;
+    typedef unsigned char       uint8_t;
+    typedef char                int8_t;
+  #else
+    #ifdef _EFI_P64 
+      //
+      // P64 - is Intel Itanium(TM) speak for pointers being 64-bit and longs and ints 
+      //  are 32-bits
+      //
+      typedef unsigned long long  uint64_t;
+      typedef long long           int64_t;
+      typedef unsigned int        uint32_t;
+      typedef int                 int32_t;
+      typedef unsigned short      uint16_t;
+      typedef short               int16_t;
+      typedef unsigned char       uint8_t;
+      typedef char                int8_t;
+    #else
+      //
+      // Assume LP64 - longs and pointers are 64-bit. Ints are 32-bit.
+      //
+      typedef unsigned long   uint64_t;
+      typedef long            int64_t;
+      typedef unsigned int    uint32_t;
+      typedef int             int32_t;
+      typedef unsigned short  uint16_t;
+      typedef short           int16_t;
+      typedef unsigned char   uint8_t;
+      typedef char            int8_t;
+    #endif
+  #endif
+#else
+  //
+  // Use ANSI C 2000 stdint.h integer width declarations
+  //
+  #include "stdint.h"
+#endif
+
+//
+// Native integer size in stdint.h
+//
+typedef uint64_t  uintn_t;
+typedef int64_t   intn_t;
+
+//
+// Processor specific defines
+//
+#define EFI_MAX_BIT  0x8000000000000000
+#define MAX_2_BITS   0xC000000000000000
+
+//
+// Maximum legal Itanium-based address
+//
+#define EFI_MAX_ADDRESS   0xFFFFFFFFFFFFFFFF
+
+//
+//  Bad pointer value to use in check builds.
+//  if you see this value you are using uninitialized or free'ed data
+//
+#define EFI_BAD_POINTER          0xAFAFAFAFAFAFAFAF
+#define EFI_BAD_POINTER_AS_BYTE  0xAF
+
+//
+// Inject a break point in the code to assist debugging.
+//
+#pragma intrinsic (__break)  
+#define EFI_BREAKPOINT()  __break(0)
+#define EFI_DEADLOOP()    while(TRUE)
+
+//
+// Memory Fence forces serialization, and is needed to support out of order
+//  memory transactions. The Memory Fence is mainly used to make sure IO
+//  transactions complete in a deterministic sequence, and to syncronize locks
+//  an other MP code. Intel Itanium(TM) processors require explicit memory fence instructions
+//  after every IO. Need to find a way of doing that in the function _mf.
+//
+void __mfa (void);                       
+#pragma intrinsic (__mfa)  
+#define MEMORY_FENCE()  __mfa()
+
+
+//
+// Some compilers don't support the forward reference construct:
+//  typedef struct XXXXX. The forward reference is required for 
+//  ANSI compatibility.
+//
+// The following macro provide a workaround for such cases.
+//
+
+
+#ifdef EFI_NO_INTERFACE_DECL
+  #define EFI_FORWARD_DECLARATION(x)
+#else
+  #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#endif
+
+//
+// Some C compilers optimize the calling conventions to increase performance.
+// _EFIAPI is used to make all public APIs follow the standard C calling 
+// convention.
+//
+
+#if _MSC_EXTENSIONS 
+  #define _EFIAPI __cdecl  
+#else
+  #define _EFIAPI       
+#endif
+
+
+#ifdef _EFI_WINNT
+
+  #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( disable : 4142 )
+
+  #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( default : 4142 )
+#else
+
+  #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( disable : 4068 )
+
+  #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( default : 4068 )
+
+
+#endif
+
+
+#endif
+

EdkCompatibilityPkg/Foundation/Include/Ipf/EfiPeOptionalHeader.h

@@ -0,0 +1,37 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiPeOptionalHeader.h
+
+Abstract:
+  Defines the optional header in the PE image per the PE specification.  This
+  file must be included only from within EfiImage.h since 
+  EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
+  there.
+
+--*/
+
+#ifndef _EFI_PE_OPTIONAL_HEADER_H_
+#define _EFI_PE_OPTIONAL_HEADER_H_
+
+#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_IA64)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+  (((Machine) == EFI_IMAGE_MACHINE_IA64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) 
+
+#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC
+typedef EFI_IMAGE_OPTIONAL_HEADER64 EFI_IMAGE_OPTIONAL_HEADER;
+typedef EFI_IMAGE_NT_HEADERS64      EFI_IMAGE_NT_HEADERS;
+#endif

EdkCompatibilityPkg/Foundation/Include/Ipf/IpfDefines.h

@@ -0,0 +1,556 @@
+// ++
+
+// TODO: fix comment to start with /*++
+//
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+//  IpfDefines.h
+//
+// Abstract:
+//
+//  IPF Processor Defines.
+//  NOTE: This file is included by assembly files as well.
+//
+// --
+//
+#ifndef _IPFDEFINES_H
+#define _IPFDEFINES_H
+
+//
+//  IPI DElivery Methods
+//
+#define IPI_INT_DELIVERY    0x0
+#define IPI_PMI_DELIVERY    0x2
+#define IPI_NMI_DELIVERY    0x4
+#define IPI_INIT_DELIVERY   0x5
+#define IPI_ExtINT_DELIVERY 0x7
+
+//
+// Define Itanium-based system registers.
+//
+// Define Itanium-based system register bit field offsets.
+//
+// Processor Status Register (PSR) Bit positions
+//
+// User / System mask
+//
+#define PSR_RV0 0
+#define PSR_BE  1
+#define PSR_UP  2
+#define PSR_AC  3
+#define PSR_MFL 4
+#define PSR_MFH 5
+
+//
+// PSR bits 6-12 reserved (must be zero)
+//
+#define PSR_MBZ0    6
+#define PSR_MBZ0_V  0x1ffUL L
+
+//
+// System only mask
+//
+#define PSR_IC      13
+#define PSR_IC_MASK (1 << 13)
+#define PSR_I       14
+#define PSR_PK      15
+#define PSR_MBZ1    16
+#define PSR_MBZ1_V  0x1UL L
+#define PSR_DT      17
+#define PSR_DFL     18
+#define PSR_DFH     19
+#define PSR_SP      20
+#define PSR_PP      21
+#define PSR_DI      22
+#define PSR_SI      23
+#define PSR_DB      24
+#define PSR_LP      25
+#define PSR_TB      26
+#define PSR_RT      27
+
+//
+// PSR bits 28-31 reserved (must be zero)
+//
+#define PSR_MBZ2    28
+#define PSR_MBZ2_V  0xfUL L
+
+//
+// Neither mask
+//
+#define PSR_CPL     32
+#define PSR_CPL_LEN 2
+#define PSR_IS      34
+#define PSR_MC      35
+#define PSR_IT      36
+#define PSR_IT_MASK 0x1000000000
+#define PSR_ID      37
+#define PSR_DA      38
+#define PSR_DD      39
+#define PSR_SS      40
+#define PSR_RI      41
+#define PSR_RI_LEN  2
+#define PSR_ED      43
+#define PSR_BN      44
+
+//
+// PSR bits 45-63 reserved (must be zero)
+//
+#define PSR_MBZ3    45
+#define PSR_MBZ3_V  0xfffffUL L
+
+//
+// Floating Point Status Register (FPSR) Bit positions
+//
+//
+// Traps
+//
+#define FPSR_VD 0
+#define FPSR_DD 1
+#define FPSR_ZD 2
+#define FPSR_OD 3
+#define FPSR_UD 4
+#define FPSR_ID 5
+
+//
+// Status Field 0 - Controls
+//
+#define FPSR0_FTZ0  6
+#define FPSR0_WRE0  7
+#define FPSR0_PC0   8
+#define FPSR0_RC0   10
+#define FPSR0_TD0   12
+
+//
+// Status Field 0 - Flags
+//
+#define FPSR0_V0  13
+#define FPSR0_D0  14
+#define FPSR0_Z0  15
+#define FPSR0_O0  16
+#define FPSR0_U0  17
+#define FPSR0_I0  18
+
+//
+// Status Field 1 - Controls
+//
+#define FPSR1_FTZ0  19
+#define FPSR1_WRE0  20
+#define FPSR1_PC0   21
+#define FPSR1_RC0   23
+#define FPSR1_TD0   25
+
+//
+// Status Field 1 - Flags
+//
+#define FPSR1_V0  26
+#define FPSR1_D0  27
+#define FPSR1_Z0  28
+#define FPSR1_O0  29
+#define FPSR1_U0  30
+#define FPSR1_I0  31
+
+//
+// Status Field 2 - Controls
+//
+#define FPSR2_FTZ0  32
+#define FPSR2_WRE0  33
+#define FPSR2_PC0   34
+#define FPSR2_RC0   36
+#define FPSR2_TD0   38
+
+//
+// Status Field 2 - Flags
+//
+#define FPSR2_V0  39
+#define FPSR2_D0  40
+#define FPSR2_Z0  41
+#define FPSR2_O0  42
+#define FPSR2_U0  43
+#define FPSR2_I0  44
+
+//
+// Status Field 3 - Controls
+//
+#define FPSR3_FTZ0  45
+#define FPSR3_WRE0  46
+#define FPSR3_PC0   47
+#define FPSR3_RC0   49
+#define FPSR3_TD0   51
+
+//
+// Status Field 0 - Flags
+//
+#define FPSR3_V0  52
+#define FPSR3_D0  53
+#define FPSR3_Z0  54
+#define FPSR3_O0  55
+#define FPSR3_U0  56
+#define FPSR3_I0  57
+
+//
+// FPSR bits 58-63 Reserved -- Must be zero
+//
+#define FPSR_MBZ0   58
+#define FPSR_MBZ0_V 0x3fUL L
+
+//
+// For setting up FPSR on kernel entry
+// All traps are disabled.
+//
+#define FPSR_FOR_KERNEL     0x3f
+
+#define FP_REG_SIZE         16  // 16 byte spill size
+#define HIGHFP_REGS_LENGTH  (96 * 16)
+
+//
+// Define hardware Task Priority Register (TPR)
+//
+//
+// TPR bit positions
+//
+#define TPR_MIC     4   // Bits 0 - 3 ignored
+#define TPR_MIC_LEN 4
+#define TPR_MMI     16  // Mask Maskable Interrupt
+//
+// Define hardware Interrupt Status Register (ISR)
+//
+//
+// ISR bit positions
+//
+#define ISR_CODE          0
+#define ISR_CODE_LEN      16
+#define ISR_CODE_MASK     0xFFFF
+#define ISR_IA_VECTOR     16
+#define ISR_IA_VECTOR_LEN 8
+#define ISR_MBZ0          24
+#define ISR_MBZ0_V        0xff
+#define ISR_X             32
+#define ISR_W             33
+#define ISR_R             34
+#define ISR_NA            35
+#define ISR_SP            36
+#define ISR_RS            37
+#define ISR_IR            38
+#define ISR_NI            39
+#define ISR_MBZ1          40
+#define ISR_EI            41
+#define ISR_ED            43
+#define ISR_MBZ2          44
+#define ISR_MBZ2_V        0xfffff
+
+//
+// ISR codes
+//
+// For General exceptions: ISR{3:0}
+//
+#define ISR_ILLEGAL_OP  0 //  Illegal operation fault
+#define ISR_PRIV_OP     1 //  Privileged operation fault
+#define ISR_PRIV_REG    2 //  Privileged register fauls
+#define ISR_RESVD_REG   3 //  Reserved register/field flt
+#define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault
+//
+// Define hardware Default Control Register (DCR)
+//
+//
+// DCR bit positions
+//
+#define DCR_PP        0
+#define DCR_BE        1
+#define DCR_LC        2
+#define DCR_MBZ0      4
+#define DCR_MBZ0_V    0xf
+#define DCR_DM        8
+#define DCR_DP        9
+#define DCR_DK        10
+#define DCR_DX        11
+#define DCR_DR        12
+#define DCR_DA        13
+#define DCR_DD        14
+#define DCR_DEFER_ALL 0x7f00
+#define DCR_MBZ1      2
+#define DCR_MBZ1_V    0xffffffffffffUL L
+
+//
+// Define hardware RSE Configuration Register
+//
+// RS Configuration (RSC) bit field positions
+//
+#define RSC_MODE        0
+#define RSC_PL          2
+#define RSC_BE          4
+#define RSC_MBZ0        5
+#define RSC_MBZ0_V      0x3ff
+#define RSC_LOADRS      16
+#define RSC_LOADRS_LEN  14
+#define RSC_MBZ1        30
+#define RSC_MBZ1_V      0x3ffffffffUL L
+
+//
+// RSC modes
+//
+#define RSC_MODE_LY (0x0) // Lazy
+#define RSC_MODE_SI (0x1) // Store intensive
+#define RSC_MODE_LI (0x2) // Load intensive
+#define RSC_MODE_EA (0x3) // Eager
+//
+// RSC Endian bit values
+//
+#define RSC_BE_LITTLE 0
+#define RSC_BE_BIG    1
+
+//
+// Define Interruption Function State (IFS) Register
+//
+// IFS bit field positions
+//
+#define IFS_IFM     0
+#define IFS_IFM_LEN 38
+#define IFS_MBZ0    38
+#define IFS_MBZ0_V  0x1ffffff
+#define IFS_V       63
+#define IFS_V_LEN   1
+
+//
+// IFS is valid when IFS_V = IFS_VALID
+//
+#define IFS_VALID 1
+
+//
+// Define Page Table Address (PTA)
+//
+#define PTA_VE        0
+#define PTA_VF        8
+#define PTA_SIZE      2
+#define PTA_SIZE_LEN  6
+#define PTA_BASE      15
+
+//
+// Define Region Register (RR)
+//
+//
+// RR bit field positions
+//
+#define RR_VE       0
+#define RR_MBZ0     1
+#define RR_PS       2
+#define RR_PS_LEN   6
+#define RR_RID      8
+#define RR_RID_LEN  24
+#define RR_MBZ1     32
+
+//
+// SAL uses region register 0 and RID of 1000
+//
+#define SAL_RID     0x1000
+#define SAL_RR_REG  0x0
+#define SAL_TR      0x0
+
+//
+// Total number of region registers
+//
+#define RR_SIZE 8
+
+//
+// Define Protection Key Register (PKR)
+//
+// PKR bit field positions
+//
+#define PKR_V       0
+#define PKR_WD      1
+#define PKR_RD      2
+#define PKR_XD      3
+#define PKR_MBZ0    4
+#define PKR_KEY     8
+#define PKR_KEY_LEN 24
+#define PKR_MBZ1    32
+
+#define PKR_VALID   (1 << PKR_V)
+
+//
+// Number of protection key registers
+//
+#define PKRNUM  8
+
+//
+// Define Interruption TLB Insertion register (ITIR)
+//
+//
+// Define Translation Insertion Format (TR)
+//
+// PTE0 bit field positions
+//
+#define PTE0_P    0
+#define PTE0_MBZ0 1
+#define PTE0_MA   2
+#define PTE0_A    5
+#define PTE0_D    6
+#define PTE0_PL   7
+#define PTE0_AR   9
+#define PTE0_PPN  12
+#define PTE0_MBZ1 48
+#define PTE0_ED   52
+#define PTE0_IGN0 53
+
+//
+// ITIR bit field positions
+//
+#define ITIR_MBZ0     0
+#define ITIR_PS       2
+#define ITIR_PS_LEN   6
+#define ITIR_KEY      8
+#define ITIR_KEY_LEN  24
+#define ITIR_MBZ1     32
+#define ITIR_MBZ1_LEN 16
+#define ITIR_PPN      48
+#define ITIR_PPN_LEN  15
+#define ITIR_MBZ2     63
+
+#define ATTR_IPAGE    0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)
+#define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)
+// Dirty (bit 6=1), Accessed (bit 5=1),
+// MA WB (bits 4-2=000), Present (bit 0=1)
+//
+// Memory access rights
+//
+#define AR_UR_KR      0x0 // user/kernel read
+#define AR_URX_KRX    0x1 // user/kernel read and execute
+#define AR_URW_KRW    0x2 // user/kernel read & write
+#define AR_URWX_KRWX  0x3 // user/kernel read,write&execute
+#define AR_UR_KRW     0x4 // user read/kernel read,write
+#define AR_URX_KRWX   0x5 // user read/execute, kernel all
+#define AR_URWX_KRW   0x6 // user all, kernel read & write
+#define AR_UX_KRX     0x7 // user execute only, kernel read and execute
+//
+// Memory attribute values
+//
+//
+// The next 4 are all cached, non-sequential & speculative, coherent
+//
+#define MA_WBU  0x0 // Write back, unordered
+//
+// The next 3 are all non-cached, sequential & non-speculative
+//
+#define MA_UC   0x4 // Non-coalescing, sequential & non-speculative
+#define MA_UCE  0x5 // Non-coalescing, sequential, non-speculative
+// & fetchadd exported
+//
+#define MA_WC   0x6 // Non-cached, Coalescing,  non-seq., spec.
+#define MA_NAT  0xf // NaT page
+//
+// Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the
+// base of IVA (Interruption Vector Address)
+//
+#define IVT_SIZE          0x8000
+#define EXTRA_ALIGNMENT   0x1000
+
+#define OFF_VHPTFLT       0x0000  // VHPT Translation fault
+#define OFF_ITLBFLT       0x0400  // Instruction TLB fault
+#define OFF_DTLBFLT       0x0800  // Data TLB fault
+#define OFF_ALTITLBFLT    0x0C00  // Alternate ITLB fault
+#define OFF_ALTDTLBFLT    0x1000  // Alternate DTLB fault
+#define OFF_NESTEDTLBFLT  0x1400  // Nested TLB fault
+#define OFF_IKEYMISSFLT   0x1800  // Inst Key Miss fault
+#define OFF_DKEYMISSFLT   0x1C00  // Data Key Miss fault
+#define OFF_DIRTYBITFLT   0x2000  // Dirty-Bit fault
+#define OFF_IACCESSBITFLT 0x2400  // Inst Access-Bit fault
+#define OFF_DACCESSBITFLT 0x2800  // Data Access-Bit fault
+#define OFF_BREAKFLT      0x2C00  // Break Inst fault
+#define OFF_EXTINT        0x3000  // External Interrupt
+//
+//  Offset 0x3400 to 0x0x4C00 are reserved
+//
+#define OFF_PAGENOTPFLT   0x5000  // Page Not Present fault
+#define OFF_KEYPERMFLT    0x5100  // Key Permission fault
+#define OFF_IACCESSRTFLT  0x5200  // Inst Access-Rights flt
+#define OFF_DACCESSRTFLT  0x5300  // Data Access-Rights fault
+#define OFF_GPFLT         0x5400  // General Exception fault
+#define OFF_FPDISFLT      0x5500  // Disable-FP fault
+#define OFF_NATFLT        0x5600  // NAT Consumption fault
+#define OFF_SPECLNFLT     0x5700  // Speculation fault
+#define OFF_DBGFLT        0x5900  // Debug fault
+#define OFF_ALIGNFLT      0x5A00  // Unaligned Reference fault
+#define OFF_LOCKDREFFLT   0x5B00  // Locked Data Reference fault
+#define OFF_FPFLT         0x5C00  // Floating Point fault
+#define OFF_FPTRAP        0x5D00  // Floating Point Trap
+#define OFF_LOPRIVTRAP    0x5E00  // Lower-Privilege Transfer Trap
+#define OFF_TAKENBRTRAP   0x5F00  // Taken Branch Trap
+#define OFF_SSTEPTRAP     0x6000  // Single Step Trap
+//
+// Offset 0x6100 to 0x6800 are reserved
+//
+#define OFF_IA32EXCEPTN   0x6900  // iA32 Exception
+#define OFF_IA32INTERCEPT 0x6A00  // iA32 Intercept
+#define OFF_IA32INT       0x6B00  // iA32 Interrupt
+#define NUMBER_OF_VECTORS 0x100
+//
+// Privilege levels
+//
+#define PL_KERNEL 0
+#define PL_USER   3
+
+//
+// Instruction set (IS) bits
+//
+#define IS_IA64 0
+#define IS_IA   1
+
+//
+// RSC while in kernel: enabled, little endian, PL = 0, eager mode
+//
+#define RSC_KERNEL  ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
+
+//
+// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
+//
+#define RSC_KERNEL_LAZ  ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
+
+//
+// RSE disabled: disabled, PL = 0, little endian, eager mode
+//
+#define RSC_KERNEL_DISABLED   ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
+
+#define NAT_BITS_PER_RNAT_REG 63
+
+//
+// Macros for generating PTE0 and PTE1 value
+//
+#define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \
+                ( ( ed << PTE0_ED )               |  \
+                  ( ppn12_47 << PTE0_PPN )        |  \
+                  ( ar << PTE0_AR )               |  \
+                  ( pl << PTE0_PL )               |  \
+                  ( d << PTE0_D )                 |  \
+                  ( a << PTE0_A )                 |  \
+                  ( ma << PTE0_MA )               |  \
+                  ( p << PTE0_P )                    \
+                )
+
+#define ITIR(ppn48_63, key, ps)            \
+                ( ( ps << ITIR_PS )       |  \
+                  ( key << ITIR_KEY )     |  \
+                  ( ppn48_63 << ITIR_PPN )         \
+    )
+
+//
+// Macro to generate mask value from bit position. The result is a
+// 64-bit.
+//
+#define BITMASK(bp, value)      (value << bp)
+
+#define BUNDLE_SIZE             16
+#define SPURIOUS_INT            0xF
+
+#define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;
+
+#define FAST_ENABLE_INTERRUPTS  ssm BITMASK (PSR_I, 1);;
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Ipf/IpfMacro.i

@@ -0,0 +1,66 @@
+//++
+// Copyright (c) 2004, Intel Corporation                                                         
+// All rights reserved. This program and the accompanying materials                          
+// are licensed and made available under the terms and conditions of the BSD License         
+// which accompanies this distribution.  The full text of the license may be found at        
+// http://opensource.org/licenses/bsd-license.php                                            
+//                                                                                           
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+// 
+// Module Name:
+//
+//  IpfMacro.i
+//
+// Abstract:
+//
+//  Contains the macros needed for calling procedures in Itanium-based assembly code.
+//
+//
+// Revision History:
+//
+//--
+
+#ifndef  _IA64PROC_I
+#define  _IA64PROC_I
+
+
+#define PROCEDURE_ENTRY(name)   .##text;            \
+                                .##type name, @function;    \
+                                .##proc name;           \
+name::
+
+#define PROCEDURE_EXIT(name)    .##endp name
+
+// Note: use of NESTED_SETUP requires number of locals (l) >= 3
+
+#define NESTED_SETUP(i,l,o,r) \
+         alloc loc1=ar##.##pfs,i,l,o,r ;\
+         mov loc0=b0
+
+#define NESTED_RETURN \
+         mov b0=loc0 ;\
+         mov ar##.##pfs=loc1 ;;\
+         br##.##ret##.##dpnt  b0;;
+
+
+#define INTERRUPT_HANDLER_BEGIN(name) \
+PROCEDURE_ENTRY(name##HandlerBegin) \
+;; \
+PROCEDURE_EXIT(name##HandlerBegin)
+
+#define INTERRUPT_HANDLER_END(name) \
+PROCEDURE_ENTRY(name##HandlerEnd) \
+;; \
+PROCEDURE_EXIT(name##HandlerEnd) 
+
+
+#define INTERRUPT_HANDLER_BLOCK_BEGIN \
+INTERRUPT_HANDLER_BEGIN(First)
+
+#define INTERRUPT_HANDLER_BLOCK_END \
+INTERRUPT_HANDLER_END(Last)
+
+
+
+#endif  // _IA64PROC_I

EdkCompatibilityPkg/Foundation/Include/Ipf/PalApi.h

@@ -0,0 +1,133 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  PalApi.h
+
+Abstract:
+
+  Main PAL API's defined in PAL specification. 
+
+
+Revision History:
+
+--*/
+
+#ifndef _PALPROC_H
+#define _PALPROC_H
+
+#include "Tiano.h"
+
+#define PAL_CACHE_FLUSH       0x0001
+#define PAL_CACHE_INFO        0x0002
+#define PAL_CACHE_INIT        0x0003
+#define PAL_CACHE_SUMMARY     0x0004
+#define PAL_MEM_ATTRIB        0x0005
+#define PAL_PTCE_INFO         0x0006
+#define PAL_VM_INFO           0x0007
+#define PAL_VM_SUMMARY        0x0008
+#define PAL_BUS_GET_FEATURES  0x0009
+#define PAL_BUS_SET_FEATURES  0x000a
+#define PAL_DEBUG_INFO        0x000b
+#define PAL_FIXED_ADDR        0x000c
+#define PAL_FREQ_BASE         0x000d
+#define PAL_FREQ_RATIOS       0x000e
+#define PAL_PERF_MON_INFO     0x000f
+#define PAL_PLATFORM_ADDR     0x0010
+#define PAL_PROC_GET_FEATURES 0x0011
+#define PAL_PROC_SET_FEATURES 0x0012
+#define PAL_RSE_INFO          0x0013
+#define PAL_VERSION           0x0014
+
+#define PAL_MC_CLEAR_LOG      0x0015
+#define PAL_MC_DRAIN          0x0016
+#define PAL_MC_EXPECTED       0x0017
+#define PAL_MC_DYNAMIC_STATE  0x0018
+#define PAL_MC_ERROR_INFO     0x0019
+#define PAL_MC_RESUME         0x001a
+#define PAL_MC_REGISTER_MEM   0x001b
+#define PAL_HALT              0x001c
+#define PAL_HALT_LIGHT        0x001d
+#define PAL_COPY_INFO         0x001e
+#define PAL_SHUTDOWN          0x002c
+#define PAL_AUTH              0x0209
+#define PAL_SINGL_DISPERSAL   0x0226  // dec. 550
+#define PAL_HALT_INFO         0x0101
+#define PAL_CACHE_LINE_INIT   0x001f
+#define PAL_PMI_ENTRYPOINT    0x0020
+#define PAL_ENTER_IA_32_ENV   0x0021
+#define PAL_VM_PAGE_SIZE      0x0022
+#define PAL_MEM_FOR_TEST      0x0025
+#define PAL_CACHE_PROT_INFO   0x0026
+
+#define PAL_COPY_PAL          0x0100
+#define PAL_CACHE_READ        0x0103
+#define PAL_CACHE_WRITE       0x0104
+#define PAL_TEST_PROC         0x0102
+
+#define PAL_DEBUG_FEATURE     0x0063  // vp1
+typedef UINT64  EFI_PAL_STATUS;
+
+//
+//  Return values from PAL
+//
+typedef struct {
+  EFI_PAL_STATUS  Status; // register r8
+  UINT64          r9;
+  UINT64          r10;
+  UINT64          r11;
+} PAL_RETURN_REGS;
+
+//
+// PAL equates for other parameters.
+//
+#define PAL_SUCCESS             0x0
+#define PAL_CALL_ERROR          0xfffffffffffffffd
+#define PAL_CALL_UNIMPLEMENTED  0xffffffffffffffff
+#define PAL_CACHE_TYPE_I        0x1
+#define PAL_CACHE_TYPE_D        0x2
+#define PAL_CACHE_TYPE_I_AND_D  0x3
+#define PAL_CACHE_NO_INT        0x0
+#define PAL_CACHE_INT           0x2
+//
+// #define PAL_CACHE_PLAT_ACK                              0x4
+//
+#define PAL_CACHE_NO_PLAT_ACK               0x0
+#define PAL_CACHE_INVALIDATE                0x1
+#define PAL_CACHE_NO_INVALIDATE             0x0
+#define PAL_CACHE_ALL_LEVELS                - 0x1
+
+#define PAL_FEATURE_ENABLE                  0x1
+#define PAL_ENABLE_BERR_BIT                 63
+#define PAL_ENABLE_MCA_BINIT_BIT            61
+#define PAL_ENABLE_CMCI_MCA_BIT             60
+#define PAL_CACHE_DISABLE_BIT               59
+#define PAL_DISABLE_COHERENCY_BIT           58
+
+#define PAL_DIS_BUS_DATA_ERR_CHECK_BIT      63
+#define PAL_DIS_BUS_ADDR_ERR_CHECK_BIT      61
+#define PAL_DIS_BUS_INIT_EVENT_SIGNAL_BIT   60
+#define PAL_DIS_BUS_REQ_ERR_SIGNAL_BIT      58
+#define PAL_DIS_BUS_REQ_INT_ERR_SIGNAL_BIT  57
+#define PAL_DIS_BUS_REQ_ERR_CHECK_BIT       56
+#define PAL_DIS_BUS_RESP_ERR_CHECK_BIT      55
+
+#define PAL_COPY_BSP_TOKEN                  0x0
+#define PAL_COPY_AP_TOKEN                   0x1
+
+#define PAL_CODE_TOKEN                      0x0
+#define PAL_IA32EMU_CODE_TOKEN              0x1
+
+#define PAL_INTERRUPT_BLOCK_TOKEN           0x0
+#define PAL_IO_BLOCK_TOKEN                  0x1
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Ipf/SalApi.h

@@ -0,0 +1,724 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  SalApi.h
+
+Abstract:
+
+  Main SAL API's defined in SAL 3.0 specification. 
+
+
+Revision History:
+
+--*/
+
+#ifndef _SAL_API_H_
+#define _SAL_API_H_
+
+typedef UINTN EFI_SAL_STATUS;
+
+//
+// EFI_SAL_STATUS defines
+//
+#define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)
+#define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)
+#define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)
+#define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)
+#define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)
+#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
+#define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)
+#define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)
+
+//
+//  Delivery Mode of IPF CPU.
+//
+typedef enum {
+  INT,
+  MPreserved1,
+  PMI,
+  MPreserved2,
+  NMI,
+  INIT,
+  MPreserved3,
+  ExtINT
+} EFI_DELIVERY_MODE;
+
+//
+//  Return values from SAL
+//
+typedef struct {
+  EFI_SAL_STATUS  Status; // register r8
+  UINTN           r9;
+  UINTN           r10;
+  UINTN           r11;
+} SAL_RETURN_REGS;
+
+typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)
+  (
+    IN UINT64 FunctionId,
+    IN UINT64 Arg2,
+    IN UINT64 Arg3,
+    IN UINT64 Arg4,
+    IN UINT64 Arg5,
+    IN UINT64 Arg6,
+    IN UINT64 Arg7,
+    IN UINT64 Arg8
+  );
+
+//
+// SAL Procedure FunctionId definition
+//
+#define EFI_SAL_SET_VECTORS             0x01000000
+#define EFI_SAL_GET_STATE_INFO          0x01000001
+#define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002
+#define EFI_SAL_CLEAR_STATE_INFO        0x01000003
+#define EFI_SAL_MC_RENDEZ               0x01000004
+#define EFI_SAL_MC_SET_PARAMS           0x01000005
+#define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006
+#define EFI_SAL_CACHE_FLUSH             0x01000008
+#define EFI_SAL_CACHE_INIT              0x01000009
+#define EFI_SAL_PCI_CONFIG_READ         0x01000010
+#define EFI_SAL_PCI_CONFIG_WRITE        0x01000011
+#define EFI_SAL_FREQ_BASE               0x01000012
+#define EFI_SAL_UPDATE_PAL              0x01000020
+
+#define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff
+#define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021
+
+//
+// SAL Procedure parameter definitions
+// Not much point in using typedefs or enums because all params
+// are UINT64 and the entry point is common
+//
+// EFI_SAL_SET_VECTORS
+//
+#define EFI_SAL_SET_MCA_VECTOR          0x0
+#define EFI_SAL_SET_INIT_VECTOR         0x1
+#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2
+
+typedef struct {
+  UINT64  Length : 32;
+  UINT64  ChecksumValid : 1;
+  UINT64  Reserved1 : 7;
+  UINT64  ByteChecksum : 8;
+  UINT64  Reserved2 : 16;
+} SAL_SET_VECTORS_CS_N;
+
+//
+// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
+// EFI_SAL_CLEAR_STATE_INFO
+//
+#define EFI_SAL_MCA_STATE_INFO  0x0
+#define EFI_SAL_INIT_STATE_INFO 0x1
+#define EFI_SAL_CMC_STATE_INFO  0x2
+#define EFI_SAL_CP_STATE_INFO   0x3
+
+//
+// EFI_SAL_MC_SET_PARAMS
+//
+#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
+#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
+#define EFI_SAL_MC_SET_CPE_PARAM    0x3
+
+#define EFI_SAL_MC_SET_INTR_PARAM   0x1
+#define EFI_SAL_MC_SET_MEM_PARAM    0x2
+
+//
+// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
+//
+#define EFI_SAL_REGISTER_PAL_ADDR 0x0
+
+//
+// EFI_SAL_CACHE_FLUSH
+//
+#define EFI_SAL_FLUSH_I_CACHE       0x01
+#define EFI_SAL_FLUSH_D_CACHE       0x02
+#define EFI_SAL_FLUSH_BOTH_CACHE    0x03
+#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
+
+//
+// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
+//
+#define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1
+#define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2
+#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
+
+typedef struct {
+  UINT64  Register : 8;
+  UINT64  Function : 3;
+  UINT64  Device : 5;
+  UINT64  Bus : 8;
+  UINT64  Segment : 8;
+  UINT64  Reserved : 32;
+} SAL_PCI_ADDRESS;
+
+//
+// EFI_SAL_FREQ_BASE
+//
+#define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0
+#define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1
+#define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2
+
+//
+// EFI_SAL_UPDATE_PAL
+//
+#define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)
+#define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)
+#define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)
+#define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)
+#define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)
+#define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)
+#define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)
+#define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)
+
+typedef struct {
+  UINT32  Size;
+  UINT32  MmddyyyyDate;
+  UINT16  Version;
+  UINT8   Type;
+  UINT8   Reserved[5];
+  UINT64  FwVendorId;
+} SAL_UPDATE_PAL_DATA_BLOCK;
+
+typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
+  struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
+  struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;
+  UINT8                             StoreChecksum;
+  UINT8                             Reserved[15];
+} SAL_UPDATE_PAL_INFO_BLOCK;
+
+//
+// SAL System Table Definitions
+//
+#pragma pack(1)
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT16  SalRevision;
+  UINT16  EntryCount;
+  UINT8   CheckSum;
+  UINT8   Reserved[7];
+  UINT16  SalAVersion;
+  UINT16  SalBVersion;
+  UINT8   OemId[32];
+  UINT8   ProductId[32];
+  UINT8   Reserved2[8];
+} SAL_SYSTEM_TABLE_HEADER;
+#pragma pack()
+
+#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
+#define EFI_SAL_REVISION            0x0300
+//
+// SAL System Types
+//
+#define EFI_SAL_ST_ENTRY_POINT        0
+#define EFI_SAL_ST_MEMORY_DESCRIPTOR  1
+#define EFI_SAL_ST_PLATFORM_FEATURES  2
+#define EFI_SAL_ST_TR_USAGE           3
+#define EFI_SAL_ST_PTC                4
+#define EFI_SAL_ST_AP_WAKEUP          5
+
+#pragma pack(1)
+typedef struct {
+  UINT8   Type; //  Type == 0
+  UINT8   Reserved[7];
+  UINT64  PalProcEntry;
+  UINT64  SalProcEntry;
+  UINT64  SalGlobalDataPointer;
+  UINT64  Reserved2[2];
+} SAL_ST_ENTRY_POINT_DESCRIPTOR;
+
+//
+// Not needed for Itanium-based OS boot
+//
+typedef struct {
+  UINT8   Type; //  Type == 1
+  UINT8   NeedVirtualRegistration;
+  UINT8   MemoryAttributes;
+  UINT8   PageAccessRights;
+  UINT8   SupportedAttributes;
+  UINT8   Reserved;
+  UINT8   MemoryType;
+  UINT8   MemoryUsage;
+  UINT64  PhysicalMemoryAddress;
+  UINT32  Length;
+  UINT32  Reserved1;
+  UINT64  OemReserved;
+} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;
+
+#pragma pack()
+//
+// Memory Attributes
+//
+#define SAL_MDT_ATTRIB_WB 0x00
+//
+// #define SAL_MDT_ATTRIB_UC   0x02
+//
+#define SAL_MDT_ATTRIB_UC   0x04
+#define SAL_MDT_ATTRIB_UCE  0x05
+#define SAL_MDT_ATTRIB_WC   0x06
+
+//
+// Supported memory Attributes
+//
+#define SAL_MDT_SUPPORT_WB  0x1
+#define SAL_MDT_SUPPORT_UC  0x2
+#define SAL_MDT_SUPPORT_UCE 0x4
+#define SAL_MDT_SUPPORT_WC  0x8
+
+//
+// Virtual address registration
+//
+#define SAL_MDT_NO_VA   0x00
+#define SAL_MDT_NEED_VA 0x01
+//
+// MemoryType info
+//
+#define SAL_REGULAR_MEMORY  0x0000
+#define SAL_MMIO_MAPPING    0x0001
+#define SAL_SAPIC_IPI_BLOCK 0x0002
+#define SAL_IO_PORT_MAPPING 0x0003
+#define SAL_FIRMWARE_MEMORY 0x0004
+#define SAL_BLACK_HOLE      0x000A
+//
+// Memory Usage info
+//
+#define SAL_MDT_USAGE_UNSPECIFIED 0x00
+#define SAL_PAL_CODE              0x01
+#define SAL_BOOTSERVICE_CODE      0x02
+#define SAL_BOOTSERVICE_DATA      0x03
+#define SAL_RUNTIMESERVICE_CODE   0x04
+#define SAL_RUNTIMESERVICE_DATA   0x05
+#define SAL_IA32_OPTIONROM        0x06
+#define SAL_IA32_SYSTEMROM        0x07
+#define SAL_PMI_CODE              0x0a
+#define SAL_PMI_DATA              0x0b
+
+#pragma pack(1)
+typedef struct {
+  UINT8 Type;                     // Type == 2
+  UINT8 PlatformFeatures;
+  UINT8 Reserved[14];
+} SAL_ST_PLATFORM_FEATURES;
+#pragma pack()
+
+#define SAL_PLAT_FEAT_BUS_LOCK      0x01
+#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
+#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
+
+#pragma pack(1)
+typedef struct {
+  UINT8   Type;                   // Type == 3
+  UINT8   TRType;
+  UINT8   TRNumber;
+  UINT8   Reserved[5];
+  UINT64  VirtualAddress;
+  UINT64  EncodedPageSize;
+  UINT64  Reserved1;
+} SAL_ST_TR_DECRIPTOR;
+#pragma pack()
+
+#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
+#define EFI_SAL_ST_TR_USAGE_DATA        01
+
+#pragma pack(1)
+typedef struct {
+  UINT64  NumberOfProcessors;
+  UINT64  LocalIDRegister;
+} SAL_COHERENCE_DOMAIN_INFO;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+  UINT8                     Type; // Type == 4
+  UINT8                     Reserved[3];
+  UINT32                    NumberOfDomains;
+  SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
+} SAL_ST_CACHE_COHERENCE_DECRIPTOR;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+  UINT8   Type;                   // Type == 5
+  UINT8   WakeUpType;
+  UINT8   Reserved[6];
+  UINT64  ExternalInterruptVector;
+} SAL_ST_AP_WAKEUP_DECRIPTOR;
+#pragma pack()
+//
+// FIT Entry
+//
+#define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24
+#define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32
+#define EFI_SAL_FIT_PALB_TYPE   01
+
+typedef struct {
+  UINT64  Address;
+  UINT8   Size[3];
+  UINT8   Reserved;
+  UINT16  Revision;
+  UINT8   Type : 7;
+  UINT8   CheckSumValid : 1;
+  UINT8   CheckSum;
+} EFI_SAL_FIT_ENTRY;
+
+//
+//  SAL Common Record Header
+//
+typedef struct {
+  UINT16  Length;
+  UINT8   Data[1024];
+} SAL_OEM_DATA;
+
+typedef struct {
+  UINT8 Seconds;
+  UINT8 Minutes;
+  UINT8 Hours;
+  UINT8 Reserved;
+  UINT8 Day;
+  UINT8 Month;
+  UINT8 Year;
+  UINT8 Century;
+} SAL_TIME_STAMP;
+
+typedef struct {
+  UINT64          RecordId;
+  UINT16          Revision;
+  UINT8           ErrorSeverity;
+  UINT8           ValidationBits;
+  UINT32          RecordLength;
+  SAL_TIME_STAMP  TimeStamp;
+  UINT8           OemPlatformId[16];
+} SAL_RECORD_HEADER;
+
+typedef struct {
+  EFI_GUID  Guid;
+  UINT16    Revision;
+  UINT8     ErrorRecoveryInfo;
+  UINT8     Reserved;
+  UINT32    SectionLength;
+} SAL_SEC_HEADER;
+
+//
+// SAL Processor Record
+//
+#define SAL_PROCESSOR_ERROR_RECORD_INFO \
+  { \
+    0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+  }
+
+#define CHECK_INFO_VALID_BIT_MASK   0x1
+#define REQUESTOR_ID_VALID_BIT_MASK 0x2
+#define RESPONDER_ID_VALID_BIT_MASK 0x4
+#define TARGER_ID_VALID_BIT_MASK    0x8
+#define PRECISE_IP_VALID_BIT_MASK   0x10
+
+typedef struct {
+  UINT64  InfoValid : 1;
+  UINT64  ReqValid : 1;
+  UINT64  RespValid : 1;
+  UINT64  TargetValid : 1;
+  UINT64  IpValid : 1;
+  UINT64  Reserved : 59;
+  UINT64  Info;
+  UINT64  Req;
+  UINT64  Resp;
+  UINT64  Target;
+  UINT64  Ip;
+} MOD_ERROR_INFO;
+
+typedef struct {
+  UINT8 CpuidInfo[40];
+  UINT8 Reserved;
+} CPUID_INFO;
+
+typedef struct {
+  UINT64  FrLow;
+  UINT64  FrHigh;
+} FR_STRUCT;
+
+#define MIN_STATE_VALID_BIT_MASK  0x1
+#define BR_VALID_BIT_MASK         0x2
+#define CR_VALID_BIT_MASK         0x4
+#define AR_VALID_BIT_MASK         0x8
+#define RR_VALID_BIT_MASK         0x10
+#define FR_VALID_BIT_MASK         0x20
+
+typedef struct {
+  UINT64    ValidFieldBits;
+  UINT8     MinStateInfo[1024];
+  UINT64    Br[8];
+  UINT64    Cr[128];
+  UINT64    Ar[128];
+  UINT64    Rr[8];
+  FR_STRUCT Fr[128];
+} PSI_STATIC_STRUCT;
+
+#define PROC_ERROR_MAP_VALID_BIT_MASK       0x1
+#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
+#define PROC_CR_LID_VALID_BIT_MASK          0x4
+#define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8
+#define CPU_INFO_VALID_BIT_MASK             0x1000000
+
+typedef struct {
+  SAL_SEC_HEADER    SectionHeader;
+  UINT64            ValidationBits;
+  UINT64            ProcErrorMap;
+  UINT64            ProcStateParameter;
+  UINT64            ProcCrLid;
+  MOD_ERROR_INFO    CacheError[15];
+  MOD_ERROR_INFO    TlbError[15];
+  MOD_ERROR_INFO    BusError[15];
+  MOD_ERROR_INFO    RegFileCheck[15];
+  MOD_ERROR_INFO    MsCheck[15];
+  CPUID_INFO        CpuInfo;
+  PSI_STATIC_STRUCT PsiValidData;
+} SAL_PROCESSOR_ERROR_RECORD;
+
+//
+//  Sal Platform memory Error Record
+//
+#define SAL_MEMORY_ERROR_RECORD_INFO \
+  { \
+    0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+  }
+
+#define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1
+#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2
+#define MEMORY_ADDR_BIT_MASK                              0x4
+#define MEMORY_NODE_VALID_BIT_MASK                        0x8
+#define MEMORY_CARD_VALID_BIT_MASK                        0x10
+#define MEMORY_MODULE_VALID_BIT_MASK                      0x20
+#define MEMORY_BANK_VALID_BIT_MASK                        0x40
+#define MEMORY_DEVICE_VALID_BIT_MASK                      0x80
+#define MEMORY_ROW_VALID_BIT_MASK                         0x100
+#define MEMORY_COLUMN_VALID_BIT_MASK                      0x200
+#define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400
+#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800
+#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000
+#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000
+#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000
+#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000
+#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000
+
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT64          MemErrorStatus;
+  UINT64          MemPhysicalAddress;
+  UINT64          MemPhysicalAddressMask;
+  UINT16          MemNode;
+  UINT16          MemCard;
+  UINT16          MemModule;
+  UINT16          MemBank;
+  UINT16          MemDevice;
+  UINT16          MemRow;
+  UINT16          MemColumn;
+  UINT16          MemBitPosition;
+  UINT64          ModRequestorId;
+  UINT64          ModResponderId;
+  UINT64          ModTargetId;
+  UINT64          BusSpecificData;
+  UINT8           MemPlatformOemId[16];
+} SAL_MEMORY_ERROR_RECORD;
+
+//
+//  PCI BUS Errors
+//
+#define SAL_PCI_BUS_ERROR_RECORD_INFO \
+  { \
+    0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+  }
+
+#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1
+#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2
+#define PCI_BUS_ID_VALID_BIT_MASK               0x4
+#define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8
+#define PCI_BUS_DATA_VALID_BIT_MASK             0x10
+#define PCI_BUS_CMD_VALID_BIT_MASK              0x20
+#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40
+#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80
+#define PCI_BUS_TARGET_VALID_BIT_MASK           0x100
+#define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200
+#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400
+
+typedef enum {
+  Unknown,
+  DataParityError,
+  SystemError,
+  MasterAbort,
+  BusTimeout,
+  MasterDataParityError,
+  AddressParityError,
+  CommandParityError
+} PCI_BUS_ERROR_TYPE;
+
+typedef struct {
+  UINT8 BusNumber;
+  UINT8 SegmentNumber;
+} PCI_BUS_ID;
+
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT64          PciBusErrorStatus;
+  UINT16          PciBusErrorType;
+  PCI_BUS_ID      PciBusId;
+  UINT32          Reserved;
+  UINT64          PciBusAddress;
+  UINT64          PciBusData;
+  UINT64          PciBusCommand;
+  UINT64          PciBusRequestorId;
+  UINT64          PciBusResponderId;
+  UINT64          PciBusTargetId;
+  UINT8           PciBusOemId[16];
+} SAL_PCI_BUS_ERROR_RECORD;
+
+//
+//  PCI Component Errors
+//
+#define SAL_PCI_COMP_ERROR_RECORD_INFO \
+  { \
+    0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+  }
+
+#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1
+#define PCI_COMP_INFO_VALID_BIT_MASK            0x2
+#define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4
+#define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8
+#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10
+#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
+
+typedef struct {
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT8   ClassCode[3];
+  UINT8   FunctionNumber;
+  UINT8   DeviceNumber;
+  UINT8   BusNumber;
+  UINT8   SegmentNumber;
+  UINT8   Reserved[5];
+} PCI_COMP_INFO;
+
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT64          PciComponentErrorStatus;
+  PCI_COMP_INFO   PciComponentInfo;
+  UINT32          PciComponentMemNum;
+  UINT32          PciComponentIoNum;
+  UINT8           PciBusOemId[16];
+} SAL_PCI_COMPONENT_ERROR_RECORD;
+
+//
+//  Sal Device Errors Info.
+//
+#define SAL_DEVICE_ERROR_RECORD_INFO \
+  { \
+    0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+  }
+
+#define SEL_RECORD_ID_VALID_BIT_MASK      0x1;
+#define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;
+#define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;
+#define SEL_EVM_REV_VALID_BIT_MASK        0x8;
+#define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;
+#define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;
+#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
+#define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;
+#define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;
+#define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;
+
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT16          SelRecordId;
+  UINT8           SelRecordType;
+  UINT32          TimeStamp;
+  UINT16          GeneratorId;
+  UINT8           EvmRevision;
+  UINT8           SensorType;
+  UINT8           SensorNum;
+  UINT8           EventDirType;
+  UINT8           Data1;
+  UINT8           Data2;
+  UINT8           Data3;
+} SAL_DEVICE_ERROR_RECORD;
+
+//
+//  Sal SMBIOS Device Errors Info.
+//
+#define SAL_SMBIOS_ERROR_RECORD_INFO \
+  { \
+    0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+  }
+
+#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1
+#define SMBIOS_LENGTH_VALID_BIT_MASK      0x2
+#define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4
+#define SMBIOS_DATA_VALID_BIT_MASK        0x8
+
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT8           SmbiosEventType;
+  UINT8           SmbiosLength;
+  UINT8           SmbiosBcdTimeStamp[6];
+} SAL_SMBIOS_DEVICE_ERROR_RECORD;
+
+//
+//  Sal Platform Specific Errors Info.
+//
+#define SAL_PLATFORM_ERROR_RECORD_INFO \
+  { \
+    0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+  }
+
+#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1
+#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2
+#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4
+#define PLATFORM_TARGET_VALID_BIT_MASK          0x8
+#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10
+#define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20
+#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
+#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
+
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT64          PlatformErrorStatus;
+  UINT64          PlatformRequestorId;
+  UINT64          PlatformResponderId;
+  UINT64          PlatformTargetId;
+  UINT64          PlatformBusSpecificData;
+  UINT8           OemComponentId[16];
+} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
+
+//
+// Union of all the possible Sal Record Types
+//
+typedef union {
+  SAL_RECORD_HEADER                   *RecordHeader;
+  SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;
+  SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;
+  SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;
+  SAL_DEVICE_ERROR_RECORD             *ImpiRecord;
+  SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;
+  SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;
+  SAL_MEMORY_ERROR_RECORD             *MemoryRecord;
+  UINT8                               *Raw;
+} SAL_ERROR_RECORDS_POINTERS;
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Ipf/TianoBind.h

@@ -0,0 +1,30 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  TianoBind.h
+
+Abstract:
+
+  Tiano's Processor or Compiler specific defines and types for Intel?Itanium(TM) 
+  besides EfiBind.h.
+
+--*/
+
+#ifndef _TIANO_BIND_H_
+#define _TIANO_BIND_H_
+
+#include "EfiBind.h"
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Pei/Pei.h

@@ -0,0 +1,58 @@
+/*++
+
+Copyright (c) 2004 - 2005, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  Pei.h
+
+Abstract:
+
+  Framework PEI master include file.
+
+  This is the main include file for Framework PEI components. There should be
+  no defines or macros added to this file, other than the EFI version 
+  information already in this file.
+
+  Don't add include files to the list for convenience, only add things
+  that are architectural. Don't add Protocols or GUID include files here
+
+--*/
+
+#ifndef _PEI_H_
+#define _PEI_H_
+
+//
+// PEI Specification Revision information
+//
+#include "TianoCommon.h"
+
+#include "PeiBind.h"
+#include "PeiApi.h"
+#include "EfiDebug.h"
+#include "PeiDebug.h"
+
+//
+// Enable code sharing with DXE by removing ASSERT and DEBUG
+//
+// #define ASSERT(a)
+// #define DEBUG (a)
+//
+
+#ifdef EFI_PEI_REPORT_STATUS_CODE_ON
+#define PEI_REPORT_STATUS_CODE_CODE(Code) Code
+#define PEI_REPORT_STATUS_CODE(PeiServices, CodeType, Value, Instance, CallerId, Data) \
+          (*PeiServices)->PeiReportStatusCode (PeiServices, CodeType, Value, Instance, CallerId, Data)
+#else
+#define PEI_REPORT_STATUS_CODE_CODE(Code)
+#define PEI_REPORT_STATUS_CODE(PeiServices, CodeType, Value, Instance, CallerId, Data)
+#endif
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Pei/PeiBind.h

@@ -0,0 +1,160 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  PeiBind.h
+
+Abstract:
+
+  Tiano PEI core and PEIM binding macros
+
+--*/
+
+#ifndef _PEI_BIND_H_
+#define _PEI_BIND_H_
+
+#ifdef EFI_DEBUG
+
+#ifdef EFI_NT_EMULATOR
+
+#if (PI_SPECIFICATION_VERSION < 0x00010000)
+
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction)                \
+          UINTN                                               \
+          __stdcall                                           \
+          _DllMainCRTStartup (                                \
+              UINTN    Inst,                                  \
+              UINTN    reason_for_call,                       \
+              VOID    *rserved                                \
+              )                                               \
+          {                                                   \
+              return 1;                                       \
+          }                                                   \
+                                                              \
+          EFI_STATUS                                          \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+            IN EFI_PEI_STARTUP_DESCRIPTOR *PeiStartup         \
+              )                                               \
+          {                                                   \
+              return InitFunction(PeiStartup);                \
+          }
+
+#else
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction)                \
+          UINTN                                               \
+          __stdcall                                           \
+          _DllMainCRTStartup (                                \
+              UINTN    Inst,                                  \
+              UINTN    reason_for_call,                       \
+              VOID    *rserved                                \
+              )                                               \
+          {                                                   \
+              return 1;                                       \
+          }                                                   \
+                                                              \
+          EFI_STATUS                                          \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+            IN CONST EFI_SEC_PEI_HAND_OFF   *SecCoreData,    \
+            IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList         \
+              )                                               \
+          {                                                   \
+              return InitFunction(SecCoreData, PpiList);      \
+          }
+
+#endif
+
+#define EFI_PEIM_ENTRY_POINT(InitFunction)                    \
+          UINTN                                               \
+          __stdcall                                           \
+          _DllMainCRTStartup (                                \
+              UINTN    Inst,                                  \
+              UINTN    reason_for_call,                       \
+              VOID    *rserved                                \
+              )                                               \
+          {                                                   \
+              return 1;                                       \
+          }                                                   \
+                                                              \
+          EFI_STATUS                                          \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+              IN EFI_FFS_FILE_HEADER       *FfsHeader,        \
+              IN EFI_PEI_SERVICES          **PeiServices      \
+              )                                               \
+          {                                                   \
+              return InitFunction(FfsHeader, PeiServices);    \
+          }
+
+#else
+
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction)                
+#define EFI_PEIM_ENTRY_POINT(InitFunction)
+
+#endif
+
+#else
+
+#ifdef EFI_NT_EMULATOR
+
+#if (PI_SPECIFICATION_VERSION < 0x00010000)
+
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction)                \
+          EFI_STATUS                                          \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+            IN EFI_PEI_STARTUP_DESCRIPTOR *PeiStartup         \
+              )                                               \
+          {                                                   \
+              return InitFunction(PeiStartup);                \
+          }
+
+#else
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction)                \
+          EFI_STATUS                                          \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+            IN CONST EFI_SEC_PEI_HAND_OFF   *SecCoreData,    \
+            IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList         \
+            )                                               \
+          {                                                   \
+              return InitFunction(SecCoreData, PpiList);     \
+          }
+
+#endif
+
+          
+#define EFI_PEIM_ENTRY_POINT(InitFunction)                    \
+          EFI_STATUS                                          \
+          __declspec( dllexport  )                            \
+          __cdecl                                             \
+          InitializeDriver (                                  \
+              IN EFI_FFS_FILE_HEADER       *FfsHeader,        \
+              IN EFI_PEI_SERVICES          **PeiServices      \
+              )                                               \
+          {                                                   \
+              return InitFunction(FfsHeader, PeiServices);    \
+          }
+#else
+
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction)                
+#define EFI_PEIM_ENTRY_POINT(InitFunction)
+
+#endif
+#endif
+#endif

EdkCompatibilityPkg/Foundation/Include/Pei/PeiDebug.h

@@ -0,0 +1,104 @@
+/*++
+
+Copyright (c) 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  PeiDebug.h
+
+Abstract:
+
+  PEI Debug macros. The work needs to be done in library. The Debug
+  macros them selves are standard for all files, including the core.
+  
+  There needs to be code linked in that produces the following macros:
+  
+  PeiDebugAssert(file, linenumber, assertion string) - worker function for 
+      ASSERT. filename and line number of where this ASSERT() is located
+      is passed in along with the stringized version of the assertion.
+  
+  PeiDebugPrint - Worker function for debug print
+
+  _DEBUG_SET_MEM(address, length, value) - Set memory at address to value
+    for legnth bytes. This macro is used to initialzed uninitialized memory
+    or memory that is free'ed, so it will not be used by mistake. 
+
+--*/
+
+#ifndef _PEIDEBUG_H_
+#define _PEIDEBUG_H_
+
+#ifdef EFI_DEBUG
+
+  VOID
+  PeiDebugAssert (
+    IN CONST EFI_PEI_SERVICES   **PeiServices,
+    IN CHAR8              *FileName,
+    IN INTN               LineNumber,
+    IN CHAR8              *Description
+    );
+
+  VOID
+  PeiDebugPrint (
+    IN CONST EFI_PEI_SERVICES   **PeiServices,
+    IN UINTN              ErrorLevel,
+    IN CHAR8              *Format,
+    ...
+    );
+
+  #define _PEI_DEBUG_ASSERT(PeiST, assertion)  \
+            PeiDebugAssert (PeiST, __FILE__, __LINE__, #assertion)
+
+  #define _PEI_DEBUG(PeiST, arg) PeiDebugPrint (PeiST, arg)
+
+  //
+  // Define ASSERT() macro, if assertion is FALSE trigger the ASSERT
+  //
+  #define PEI_ASSERT(PeiST, assertion)   if(!(assertion))  \
+                                            _PEI_DEBUG_ASSERT(PeiST, assertion)
+    
+  #define PEI_ASSERT_LOCKED(PeiST, l)    if(!(l)->Lock) _PEI_DEBUG_ASSERT(PeiST, l not locked)
+
+  //
+  // DEBUG((DebugLevel, "format string", ...)) - if DebugLevel is active do 
+  //   the a debug print.
+  //
+  
+  #define PEI_DEBUG(arg)        PeiDebugPrint arg
+
+  #define PEI_DEBUG_CODE(code)  code
+
+  #define PEI_CR(Record, TYPE, Field, Signature)   \
+            _CR(Record, TYPE, Field)                           
+
+
+  #define _PEI_DEBUG_SET_MEM(address, length, data) SetMem(address, length, data)
+
+#else
+  #define PEI_ASSERT(PeiST, a)               
+  #define PEI_ASSERT_LOCKED(PeiST, l)    
+  #define PEI_DEBUG(arg) 
+  #define PEI_DEBUG_CODE(code)  
+  #define PEI_CR(Record, TYPE, Field, Signature)   \
+            _CR(Record, TYPE, Field)                           
+  #define _PEI_DEBUG_SET_MEM(address, length, data) 
+#endif
+
+#define ASSERT_PEI_ERROR(PeiST, status)  PEI_ASSERT(PeiST, !EFI_ERROR(status))
+
+#ifdef EFI_DEBUG_CLEAR_MEMORY
+  #define PEI_DEBUG_SET_MEMORY(address,length)  \
+            _PEI_DEBUG_SET_MEM(address, length, EFI_BAD_POINTER_AS_BYTE)
+#else
+  #define PEI_DEBUG_SET_MEMORY(address,length)
+#endif
+
+
+#endif

EdkCompatibilityPkg/Foundation/Include/Tiano.h

@@ -0,0 +1,56 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  Tiano.h
+
+Abstract:
+
+  Tiano master include file.
+
+  This is the main include file for Tiano components. 
+
+  Don't add include files to the list for convenience, only add things
+  that are architectural. Don't add Protocols or GUID include files here
+
+--*/
+
+#ifndef _TIANO_H_
+#define _TIANO_H_
+
+//
+// Check to make sure EFI_SPECIFICATION_VERSION and TIANO_RELEASE_VERSION are defined.
+//
+#if !defined(EFI_SPECIFICATION_VERSION)
+  #error EFI_SPECIFICATION_VERSION not defined
+#elif !defined(TIANO_RELEASE_VERSION)
+  #error TIANO_RELEASE_VERSION not defined
+#elif (TIANO_RELEASE_VERSION == 0)
+  #error TIANO_RELEASE_VERSION can not be zero
+#elif (EFI_SPECIFICATION_VERSION <= 0x00020000)
+  #define TIANO_EXTENSION_FLAG
+#endif
+
+#include "TianoCommon.h"
+#include "TianoApi.h"
+#include "EfiDebug.h"
+#include "TianoDevicePath.h"
+#include "EfiSpec.h"
+
+//
+// EFI Revision information
+//
+#define EFI_FIRMWARE_MAJOR_REVISION 0x1000
+#define EFI_FIRMWARE_MINOR_REVISION 1
+#define EFI_FIRMWARE_REVISION       ((EFI_FIRMWARE_MAJOR_REVISION << 16) | (EFI_FIRMWARE_MINOR_REVISION))
+
+#endif

EdkCompatibilityPkg/Foundation/Include/TianoApi.h

@@ -0,0 +1,46 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  TianoApi.h
+
+Abstract:
+
+  Tiano intrinsic definitions. 
+
+
+--*/
+
+#ifndef _TIANO_API_H_
+#define _TIANO_API_H_
+
+#include "EfiApi.h"
+#include "TianoSpecApi.h"
+
+//
+// Pointer to internal runtime function
+//
+#define EFI_INTERNAL_FUNCTION 0x00000002
+
+//
+// Pointer to internal runtime pointer
+//
+#define EFI_INTERNAL_POINTER  0x00000004
+
+//
+// Pointer to internal runtime pointer
+//
+#define EFI_IPF_GP_POINTER  0x00000008
+
+#define EFI_TPL_DRIVER      6
+
+#endif

EdkCompatibilityPkg/Foundation/Include/TianoCommon.h

@@ -0,0 +1,51 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+  
+  TianoCommon.h
+
+Abstract:
+
+  Tiano specific common definitions besides EfiCommon.h
+
+--*/
+
+#ifndef _TIANO_COMMON_H_
+#define _TIANO_COMMON_H_
+
+#include "TianoBind.h"
+#include "TianoTypes.h"
+#include "EfiStdArg.h"
+#include "TianoError.h"
+#include "EfiStatusCode.h"
+#include "EfiCommon.h"
+
+//
+// Define macros for including Architectural Protocols and PPIs
+//
+#define EFI_ARCH_PROTOCOL_DEFINITION(a) EFI_STRINGIZE (ArchProtocol/a/a.h)
+#define EFI_PPI_DEFINITION(a)           EFI_STRINGIZE (Ppi/a/a.h)
+
+//
+// These should be used to include protocols.  If they are followed,
+// intelligent build tools can be created to check dependencies at build
+// time.
+//
+#define EFI_ARCH_PROTOCOL_PRODUCER(a)   EFI_ARCH_PROTOCOL_DEFINITION (a)
+#define EFI_ARCH_PROTOCOL_CONSUMER(a)   EFI_ARCH_PROTOCOL_DEFINITION (a)
+#define EFI_ARCH_PROTOCOL_DEPENDENCY(a) EFI_ARCH_PROTOCOL_DEFINITION (a)
+
+#define EFI_PPI_PRODUCER(a)             EFI_PPI_DEFINITION (a)
+#define EFI_PPI_CONSUMER(a)             EFI_PPI_DEFINITION (a)
+#define EFI_PPI_DEPENDENCY(a)           EFI_PPI_DEFINITION (a)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/TianoDevicePath.h

@@ -0,0 +1,130 @@
+/*++
+ 
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  TianoDevicePath.h
+
+Abstract:
+
+  Tiano Device Path definitions
+
+--*/
+
+#ifndef _TIANO_DEVICE_PATH_H
+#define _TIANO_DEVICE_PATH_H
+
+#include "EfiDevicePath.h"
+#include "TianoSpecDevicePath.h"
+
+#pragma pack(1)
+
+typedef struct _USB_PORT_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           PciBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} USB_PORT_DEVICE_PATH;
+
+//
+// IDE
+//
+typedef struct _IDE_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           PciBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} IDE_DEVICE_PATH;
+
+//
+// RMC Connector
+//
+typedef struct _RMC_CONN_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           PciBridgeDevicePath;
+  PCI_DEVICE_PATH           PciBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} RMC_CONN_DEVICE_PATH;
+
+//
+// RIDE
+//
+typedef struct _RIDE_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           PciBridgeDevicePath;
+  PCI_DEVICE_PATH           PciBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} RIDE_DEVICE_PATH;
+
+//
+// Gigabit NIC
+//
+typedef struct _GB_NIC_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           PciBridgeDevicePath;
+  PCI_DEVICE_PATH           PciXBridgeDevicePath;
+  PCI_DEVICE_PATH           PciXBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} GB_NIC_DEVICE_PATH;
+
+//
+// P/S2 Connector
+//
+typedef struct _PS2_CONN_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           LpcBridgeDevicePath;
+  ACPI_HID_DEVICE_PATH      LpcBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} PS2_CONN_DEVICE_PATH;
+
+//
+// Serial Port Connector
+//
+typedef struct _SERIAL_CONN_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           LpcBridgeDevicePath;
+  ACPI_HID_DEVICE_PATH      LpcBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} SERIAL_CONN_DEVICE_PATH;
+
+//
+// Parallel Port Connector
+//
+typedef struct _PARALLEL_CONN_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           LpcBridgeDevicePath;
+  ACPI_HID_DEVICE_PATH      LpcBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} PARALLEL_CONN_DEVICE_PATH;
+
+//
+// Floopy Connector
+//
+typedef struct _FLOOPY_CONN_DEVICE_PATH {
+  ACPI_HID_DEVICE_PATH      PciRootBridgeDevicePath;
+  PCI_DEVICE_PATH           LpcBridgeDevicePath;
+  ACPI_HID_DEVICE_PATH      LpcBusDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} FLOOPY_CONN_DEVICE_PATH;
+
+typedef union _EFI_MISC_PORT_DEVICE_PATH {
+  USB_PORT_DEVICE_PATH      UsbDevicePath;
+  IDE_DEVICE_PATH           IdeDevicePath;
+  RMC_CONN_DEVICE_PATH      RmcConnDevicePath;
+  RIDE_DEVICE_PATH          RideDevicePath;
+  GB_NIC_DEVICE_PATH        GbNicDevicePath;
+  PS2_CONN_DEVICE_PATH      Ps2ConnDevicePath;
+  SERIAL_CONN_DEVICE_PATH   SerialConnDevicePath;
+  PARALLEL_CONN_DEVICE_PATH ParallelConnDevicePath;
+  FLOOPY_CONN_DEVICE_PATH   FloppyConnDevicePath;
+} EFI_MISC_PORT_DEVICE_PATH;
+
+#pragma pack()
+
+#endif

EdkCompatibilityPkg/Foundation/Include/TianoError.h

@@ -0,0 +1,30 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  TianoError.h
+
+Abstract:
+
+  Tiano error levels and their associated defines
+
+--*/
+
+#ifndef _TIANO_ERROR_H_
+#define _TIANO_ERROR_H_
+
+#include "EfiError.h"
+#include "TianoSpecError.h"
+
+#define EFI_WARN_RETURN_FROM_LONG_JUMP  EFIWARN (5)
+
+#endif

EdkCompatibilityPkg/Foundation/Include/TianoTypes.h

@@ -0,0 +1,48 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  TianoTypes.h
+
+Abstract:
+
+  Tiano specific part besides EfiTypes.h
+
+--*/
+
+#ifndef _TIANO_TYPES_H_
+#define _TIANO_TYPES_H_
+
+#include "EfiTypes.h"
+#include "TianoSpecTypes.h"
+
+//
+// attributes for reserved memory before it is promoted to system memory
+//
+#define EFI_MEMORY_PRESENT      0x0100000000000000
+#define EFI_MEMORY_INITIALIZED  0x0200000000000000
+#define EFI_MEMORY_TESTED       0x0400000000000000
+
+//
+// range for memory mapped port I/O on IPF
+//
+#define EFI_MEMORY_PORT_IO  0x4000000000000000
+
+//
+// A pointer to a function in IPF points to a plabel.
+//
+typedef struct {
+  UINT64  EntryPoint;
+  UINT64  GP;
+} EFI_PLABEL;
+
+#endif

EdkCompatibilityPkg/Foundation/Include/x64/EfiBind.h

@@ -0,0 +1,222 @@
+/*++
+
+Copyright (c) 2005 - 2007, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiBind.h
+
+Abstract:
+
+  Processor or Compiler specific defines and types for x64.
+  We are using the ANSI C 2000 _t type definitions for basic types.
+  This it technically a violation of the coding standard, but they
+  are used to make EfiTypes.h portable. Code other than EfiTypes.h
+  should never use any ANSI C 2000 _t integer types.
+
+--*/
+
+#ifndef _EFI_BIND_H_
+#define _EFI_BIND_H_
+
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)                  
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+
+
+//
+// Make sure we are useing the correct packing rules per EFI specification
+//
+#pragma pack()
+
+#if _MSC_EXTENSIONS
+
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft* tools
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// Int64ShllMod32 unreferenced inline function
+//
+#pragma warning ( disable : 4514 )
+
+//
+// Unreferenced formal parameter - We are object oriented, so we pass This even
+//  if we  don't need them.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// This warning is caused by empty (after preprocessing) souce file.
+//
+#pragma warning ( disable : 4206 )
+
+//
+// Warning: The result of the unary '&' operator may be unaligned. Ignore it.
+//
+#pragma warning ( disable : 4366 )
+
+#endif
+
+
+#if (__STDC_VERSION__ < 199901L)
+  //
+  // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
+  //
+ 
+  #if _MSC_EXTENSIONS 
+    
+    //
+    // use Microsoft* C complier dependent interger width types 
+    //
+    typedef unsigned __int64    uint64_t;
+    typedef __int64             int64_t;
+    typedef unsigned __int32    uint32_t;
+    typedef __int32             int32_t;
+    typedef unsigned short      uint16_t;
+    typedef short               int16_t;
+    typedef unsigned char       uint8_t;
+    typedef char                int8_t;
+  #else
+
+    //
+    // Assume standard IA-32 alignment. 
+    // BugBug: Need to check portability of long long
+    //
+    typedef unsigned long long  uint64_t;
+    typedef long long           int64_t;
+    typedef unsigned int        uint32_t;
+    typedef int                 int32_t;
+    typedef unsigned short      uint16_t;
+    typedef short               int16_t;
+    typedef unsigned char       uint8_t;
+    typedef char                int8_t;
+  #endif
+#else
+  //
+  // Use ANSI C 2000 stdint.h integer width declarations
+  //
+  #include "stdint.h"
+#endif
+
+//
+// Native integer size in stdint.h
+//
+typedef uint64_t  uintn_t;
+typedef int64_t   intn_t;
+
+//
+// Processor specific defines
+//
+#define EFI_MAX_BIT       0x8000000000000000
+#define MAX_2_BITS        0xC000000000000000
+
+//
+// Maximum legal IA-32 address
+//
+#define EFI_MAX_ADDRESS   0xFFFFFFFFFFFFFFFF
+
+//
+//  Bad pointer value to use in check builds.
+//  if you see this value you are using uninitialized or free'ed data
+//
+#define EFI_BAD_POINTER          0xAFAFAFAFAFAFAFAF
+#define EFI_BAD_POINTER_AS_BYTE  0xAF
+
+//
+// Inject a break point in the code to assist debugging.
+//
+#define EFI_DEADLOOP()    { volatile int __iii; __iii = 1; while (__iii); }
+#define EFI_BREAKPOINT()  __debugbreak()
+
+//
+// Memory Fence forces serialization, and is needed to support out of order
+//  memory transactions. The Memory Fence is mainly used to make sure IO
+//  transactions complete in a deterministic sequence, and to syncronize locks
+//  an other MP code. Currently no memory fencing is required.
+//
+#define MEMORY_FENCE()
+
+//
+// Some compilers don't support the forward reference construct:
+//  typedef struct XXXXX. The forward reference is required for 
+//  ANSI compatibility.
+//
+// The following macro provide a workaround for such cases.
+//
+
+
+#ifdef EFI_NO_INTERFACE_DECL
+  #define EFI_FORWARD_DECLARATION(x)
+#else
+  #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#endif
+
+
+//
+// Some C compilers optimize the calling conventions to increase performance.
+// _EFIAPI is used to make all public APIs follow the standard C calling 
+// convention.
+//
+#if _MSC_EXTENSIONS
+  //
+  // Microsoft* compiler requires _EFIAPI useage, __cdecl is Microsoft* specific C.
+  // 
+
+  #define _EFIAPI __cdecl  
+#else
+  #define _EFIAPI       
+#endif
+
+
+#ifdef _EFI_WINNT
+
+  #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( disable : 4142 )
+
+  #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( default : 4142 )
+#else
+
+  #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( disable : 4068 )
+
+  #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING()  \
+           warning ( default : 4068 )
+
+#endif
+
+
+
+#endif
+

EdkCompatibilityPkg/Foundation/Include/x64/EfiPeOptionalHeader.h

@@ -0,0 +1,42 @@
+/*++
+
+Copyright (c) 2005 - 2006, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  EfiPeOptionalHeader.h
+
+Abstract:
+  Defines the optional header in the PE image per the PE specification.  This
+  file must be included only from within EfiImage.h since 
+  EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
+  there.
+
+--*/
+
+#ifndef _EFI_PE_OPTIONAL_HEADER_H_
+#define _EFI_PE_OPTIONAL_HEADER_H_
+
+#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_X64)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+  (((Machine) == EFI_IMAGE_MACHINE_X64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32) 
+
+//
+// Assume we can use IPF values
+//
+#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC
+typedef EFI_IMAGE_OPTIONAL_HEADER64     EFI_IMAGE_OPTIONAL_HEADER;
+typedef EFI_IMAGE_NT_HEADERS64          EFI_IMAGE_NT_HEADERS;
+
+#endif
+

EdkCompatibilityPkg/Foundation/Include/x64/TianoBind.h

@@ -0,0 +1,30 @@
+/*++
+
+Copyright (c) 2005, Intel Corporation                                                         
+All rights reserved. This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Module Name:
+
+  TianoBind.h
+
+Abstract:
+
+  Tiano's Processor or Compiler specific defines and types for Intel?Itanium(TM) 
+  besides EfiBind.h.
+
+--*/
+
+#ifndef _TIANO_BIND_H_
+#define _TIANO_BIND_H_
+
+#include "EfiBind.h"
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+
+#endif