Add in the 1st version of ECP.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2832 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
qwang12
@@ -0,0 +1,31 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2004 - 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
Acpi.h
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||||
|
||||
Abstract:
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||||
|
||||
This file contains some basic ACPI definitions that are consumed by drivers
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||||
that do not care about ACPI versions.
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||||
|
||||
--*/
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||||
|
||||
#ifndef _ACPI_H_
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||||
#define _ACPI_H_
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||||
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||||
#include "AcpiCommon.h"
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||||
#include "Acpi1_0.h"
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||||
#include "Acpi2_0.h"
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||||
#include "Acpi3_0.h"
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|
||||
#endif
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||||
@@ -0,0 +1,299 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
Acpi1_0.h
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||||
|
||||
Abstract:
|
||||
|
||||
ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
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||||
|
||||
--*/
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||||
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#ifndef _ACPI_1_0_H_
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#define _ACPI_1_0_H_
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||||
|
||||
//
|
||||
// Statements that include other files
|
||||
//
|
||||
#include "AcpiCommon.h"
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||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack(1)
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||||
//
|
||||
// ACPI 1.0b table structures
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||||
//
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||||
//
|
||||
// Root System Description Pointer Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 Signature;
|
||||
UINT8 Checksum;
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||||
UINT8 OemId[6];
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||||
UINT8 Reserved;
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||||
UINT32 RsdtAddress;
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||||
} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
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||||
|
||||
//
|
||||
// Root System Description Table
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||||
// No definition needed as it is a common description table header followed by a
|
||||
// variable number of UINT32 table pointers.
|
||||
//
|
||||
//
|
||||
// RSDT Revision (as defined in ACPI 1.0b spec.)
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||||
//
|
||||
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
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||||
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||||
//
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||||
// Fixed ACPI Description Table Structure (FADT)
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||||
//
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||||
typedef struct {
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||||
EFI_ACPI_DESCRIPTION_HEADER Header;
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||||
UINT32 FirmwareCtrl;
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UINT32 Dsdt;
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||||
UINT8 IntModel;
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||||
UINT8 Reserved1;
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||||
UINT16 SciInt;
|
||||
UINT32 SmiCmd;
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||||
UINT8 AcpiEnable;
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UINT8 AcpiDisable;
|
||||
UINT8 S4BiosReq;
|
||||
UINT8 Reserved2;
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||||
UINT32 Pm1aEvtBlk;
|
||||
UINT32 Pm1bEvtBlk;
|
||||
UINT32 Pm1aCntBlk;
|
||||
UINT32 Pm1bCntBlk;
|
||||
UINT32 Pm2CntBlk;
|
||||
UINT32 PmTmrBlk;
|
||||
UINT32 Gpe0Blk;
|
||||
UINT32 Gpe1Blk;
|
||||
UINT8 Pm1EvtLen;
|
||||
UINT8 Pm1CntLen;
|
||||
UINT8 Pm2CntLen;
|
||||
UINT8 PmTmLen;
|
||||
UINT8 Gpe0BlkLen;
|
||||
UINT8 Gpe1BlkLen;
|
||||
UINT8 Gpe1Base;
|
||||
UINT8 Reserved3;
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||||
UINT16 PLvl2Lat;
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||||
UINT16 PLvl3Lat;
|
||||
UINT16 FlushSize;
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||||
UINT16 FlushStride;
|
||||
UINT8 DutyOffset;
|
||||
UINT8 DutyWidth;
|
||||
UINT8 DayAlrm;
|
||||
UINT8 MonAlrm;
|
||||
UINT8 Century;
|
||||
UINT8 Reserved4;
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||||
UINT8 Reserved5;
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||||
UINT8 Reserved6;
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||||
UINT32 Flags;
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||||
} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
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||||
|
||||
//
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||||
// FADT Version (as defined in ACPI 1.0b spec.)
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||||
//
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||||
#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01
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||||
|
||||
//
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||||
// Fixed ACPI Description Table Fixed Feature Flags
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||||
// All other bits are reserved and must be set to 0.
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||||
//
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||||
#define EFI_ACPI_1_0_WBINVD (1 << 0)
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#define EFI_ACPI_1_0_WBINVD_FLUSH (1 << 1)
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#define EFI_ACPI_1_0_PROC_C1 (1 << 2)
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||||
#define EFI_ACPI_1_0_P_LVL2_UP (1 << 3)
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||||
#define EFI_ACPI_1_0_PWR_BUTTON (1 << 4)
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#define EFI_ACPI_1_0_SLP_BUTTON (1 << 5)
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||||
#define EFI_ACPI_1_0_FIX_RTC (1 << 6)
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||||
#define EFI_ACPI_1_0_RTC_S4 (1 << 7)
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||||
#define EFI_ACPI_1_0_TMR_VAL_EXT (1 << 8)
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||||
#define EFI_ACPI_1_0_DCK_CAP (1 << 9)
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||||
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||||
//
|
||||
// Firmware ACPI Control Structure
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||||
//
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||||
typedef struct {
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||||
UINT32 Signature;
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||||
UINT32 Length;
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||||
UINT32 HardwareSignature;
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||||
UINT32 FirmwareWakingVector;
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||||
UINT32 GlobalLock;
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||||
UINT32 Flags;
|
||||
UINT8 Reserved[40];
|
||||
} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
|
||||
|
||||
//
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||||
// Firmware Control Structure Feature Flags
|
||||
// All other bits are reserved and must be set to 0.
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||||
//
|
||||
#define EFI_ACPI_1_0_S4BIOS_F (1 << 0)
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||||
|
||||
//
|
||||
// Multiple APIC Description Table header definition. The rest of the table
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||||
// must be defined in a platform specific manner.
|
||||
//
|
||||
typedef struct {
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||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 LocalApicAddress;
|
||||
UINT32 Flags;
|
||||
} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
|
||||
|
||||
//
|
||||
// MADT Revision (as defined in ACPI 1.0b spec.)
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||||
//
|
||||
#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Multiple APIC Flags
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||||
// All other bits are reserved and must be set to 0.
|
||||
//
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||||
#define EFI_ACPI_1_0_PCAT_COMPAT (1 << 0)
|
||||
|
||||
//
|
||||
// Multiple APIC Description Table APIC structure types
|
||||
// All other values between 0x09 an 0xFF are reserved and
|
||||
// will be ignored by OSPM.
|
||||
//
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||||
#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00
|
||||
#define EFI_ACPI_1_0_IO_APIC 0x01
|
||||
#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02
|
||||
#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
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||||
#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04
|
||||
|
||||
//
|
||||
// APIC Structure Definitions
|
||||
//
|
||||
//
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||||
// Processor Local APIC Structure Definition
|
||||
//
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||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 AcpiProcessorId;
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||||
UINT8 ApicId;
|
||||
UINT32 Flags;
|
||||
} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC Flags. All other bits are reserved and must be 0.
|
||||
//
|
||||
#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED (1 << 0)
|
||||
|
||||
//
|
||||
// IO APIC Structure
|
||||
//
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||||
typedef struct {
|
||||
UINT8 Type;
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||||
UINT8 Length;
|
||||
UINT8 IoApicId;
|
||||
UINT8 Reserved;
|
||||
UINT32 IoApicAddress;
|
||||
UINT32 SystemVectorBase;
|
||||
} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
|
||||
|
||||
//
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||||
// Interrupt Source Override Structure
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||||
//
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||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 Bus;
|
||||
UINT8 Source;
|
||||
UINT32 GlobalSystemInterruptVector;
|
||||
UINT16 Flags;
|
||||
} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
|
||||
|
||||
//
|
||||
// Non-Maskable Interrupt Source Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Flags;
|
||||
UINT32 GlobalSystemInterruptVector;
|
||||
} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC NMI Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 AcpiProcessorId;
|
||||
UINT16 Flags;
|
||||
UINT8 LocalApicInti;
|
||||
} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
|
||||
|
||||
//
|
||||
// Smart Battery Description Table (SBST)
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 WarningEnergyLevel;
|
||||
UINT32 LowEnergyLevel;
|
||||
UINT32 CriticalEnergyLevel;
|
||||
} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
|
||||
|
||||
//
|
||||
// Known table signatures
|
||||
//
|
||||
//
|
||||
// "RSD PTR " Root System Description Pointer
|
||||
//
|
||||
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
|
||||
|
||||
//
|
||||
// "APIC" Multiple APIC Description Table
|
||||
//
|
||||
#define EFI_ACPI_1_0_APIC_SIGNATURE 0x43495041
|
||||
|
||||
//
|
||||
// "DSDT" Differentiated System Description Table
|
||||
//
|
||||
#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
|
||||
|
||||
//
|
||||
// "FACS" Firmware ACPI Control Structure
|
||||
//
|
||||
#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
|
||||
|
||||
//
|
||||
// "FACP" Fixed ACPI Description Table
|
||||
//
|
||||
#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
|
||||
|
||||
//
|
||||
// "PSDT" Persistent System Description Table
|
||||
//
|
||||
#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
|
||||
|
||||
//
|
||||
// "RSDT" Root System Description Table
|
||||
//
|
||||
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
|
||||
|
||||
//
|
||||
// "SBST" Smart Battery Specification Table
|
||||
//
|
||||
#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
|
||||
|
||||
//
|
||||
// "SSDT" Secondary System Description Table
|
||||
//
|
||||
#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,513 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
Acpi2_0.h
|
||||
|
||||
Abstract:
|
||||
|
||||
ACPI 2.0 definitions from the ACPI Specification, revision 2.0
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _ACPI_2_0_H_
|
||||
#define _ACPI_2_0_H_
|
||||
|
||||
//
|
||||
// Statements that include other files
|
||||
//
|
||||
#include "AcpiCommon.h"
|
||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack(1)
|
||||
//
|
||||
// ACPI Specification Revision
|
||||
//
|
||||
#define EFI_ACPI_2_0_REVISION 0x02
|
||||
|
||||
//
|
||||
// ACPI 2.0 Generic Address Space definition
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 AddressSpaceId;
|
||||
UINT8 RegisterBitWidth;
|
||||
UINT8 RegisterBitOffset;
|
||||
UINT8 Reserved;
|
||||
UINT64 Address;
|
||||
} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
|
||||
|
||||
//
|
||||
// Generic Address Space Address IDs
|
||||
//
|
||||
#define EFI_ACPI_2_0_SYSTEM_MEMORY 0
|
||||
#define EFI_ACPI_2_0_SYSTEM_IO 1
|
||||
#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2
|
||||
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3
|
||||
#define EFI_ACPI_2_0_SMBUS 4
|
||||
#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
|
||||
|
||||
//
|
||||
// ACPI 2.0 table structures
|
||||
//
|
||||
//
|
||||
// Root System Description Pointer Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 Signature;
|
||||
UINT8 Checksum;
|
||||
UINT8 OemId[6];
|
||||
UINT8 Revision;
|
||||
UINT32 RsdtAddress;
|
||||
UINT32 Length;
|
||||
UINT64 XsdtAddress;
|
||||
UINT8 ExtendedChecksum;
|
||||
UINT8 Reserved[3];
|
||||
} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
|
||||
|
||||
//
|
||||
// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
|
||||
|
||||
//
|
||||
// Common table header, this prefaces all ACPI tables, including FACS, but
|
||||
// excluding the RSD PTR structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
UINT32 Length;
|
||||
} EFI_ACPI_2_0_COMMON_HEADER;
|
||||
|
||||
//
|
||||
// Root System Description Table
|
||||
// No definition needed as it is a common description table header followed by a
|
||||
// variable number of UINT32 table pointers.
|
||||
//
|
||||
//
|
||||
// RSDT Revision (as defined in ACPI 2.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Extended System Description Table
|
||||
// No definition needed as it is a common description table header followed by a
|
||||
// variable number of UINT64 table pointers.
|
||||
//
|
||||
//
|
||||
// XSDT Revision (as defined in ACPI 2.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Fixed ACPI Description Table Structure (FADT)
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 FirmwareCtrl;
|
||||
UINT32 Dsdt;
|
||||
UINT8 Reserved0;
|
||||
UINT8 PreferredPmProfile;
|
||||
UINT16 SciInt;
|
||||
UINT32 SmiCmd;
|
||||
UINT8 AcpiEnable;
|
||||
UINT8 AcpiDisable;
|
||||
UINT8 S4BiosReq;
|
||||
UINT8 PstateCnt;
|
||||
UINT32 Pm1aEvtBlk;
|
||||
UINT32 Pm1bEvtBlk;
|
||||
UINT32 Pm1aCntBlk;
|
||||
UINT32 Pm1bCntBlk;
|
||||
UINT32 Pm2CntBlk;
|
||||
UINT32 PmTmrBlk;
|
||||
UINT32 Gpe0Blk;
|
||||
UINT32 Gpe1Blk;
|
||||
UINT8 Pm1EvtLen;
|
||||
UINT8 Pm1CntLen;
|
||||
UINT8 Pm2CntLen;
|
||||
UINT8 PmTmrLen;
|
||||
UINT8 Gpe0BlkLen;
|
||||
UINT8 Gpe1BlkLen;
|
||||
UINT8 Gpe1Base;
|
||||
UINT8 CstCnt;
|
||||
UINT16 PLvl2Lat;
|
||||
UINT16 PLvl3Lat;
|
||||
UINT16 FlushSize;
|
||||
UINT16 FlushStride;
|
||||
UINT8 DutyOffset;
|
||||
UINT8 DutyWidth;
|
||||
UINT8 DayAlrm;
|
||||
UINT8 MonAlrm;
|
||||
UINT8 Century;
|
||||
UINT16 IaPcBootArch;
|
||||
UINT8 Reserved1;
|
||||
UINT32 Flags;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
|
||||
UINT8 ResetValue;
|
||||
UINT8 Reserved2[3];
|
||||
UINT64 XFirmwareCtrl;
|
||||
UINT64 XDsdt;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
|
||||
} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
|
||||
|
||||
//
|
||||
// FADT Version (as defined in ACPI 2.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03
|
||||
|
||||
//
|
||||
// Fixed ACPI Description Table Boot Architecture Flags
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)
|
||||
#define EFI_ACPI_2_0_8042 (1 << 1)
|
||||
|
||||
//
|
||||
// Fixed ACPI Description Table Fixed Feature Flags
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_2_0_WBINVD (1 << 0)
|
||||
#define EFI_ACPI_2_0_WBINVD_FLUSH (1 << 1)
|
||||
#define EFI_ACPI_2_0_PROC_C1 (1 << 2)
|
||||
#define EFI_ACPI_2_0_P_LVL2_UP (1 << 3)
|
||||
#define EFI_ACPI_2_0_PWR_BUTTON (1 << 4)
|
||||
#define EFI_ACPI_2_0_SLP_BUTTON (1 << 5)
|
||||
#define EFI_ACPI_2_0_FIX_RTC (1 << 6)
|
||||
#define EFI_ACPI_2_0_RTC_S4 (1 << 7)
|
||||
#define EFI_ACPI_2_0_TMR_VAL_EXT (1 << 8)
|
||||
#define EFI_ACPI_2_0_DCK_CAP (1 << 9)
|
||||
#define EFI_ACPI_2_0_RESET_REG_SUP (1 << 10)
|
||||
#define EFI_ACPI_2_0_SEALED_CASE (1 << 11)
|
||||
#define EFI_ACPI_2_0_HEADLESS (1 << 12)
|
||||
#define EFI_ACPI_2_0_CPU_SW_SLP (1 << 13)
|
||||
|
||||
//
|
||||
// Firmware ACPI Control Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
UINT32 Length;
|
||||
UINT32 HardwareSignature;
|
||||
UINT32 FirmwareWakingVector;
|
||||
UINT32 GlobalLock;
|
||||
UINT32 Flags;
|
||||
UINT64 XFirmwareWakingVector;
|
||||
UINT8 Version;
|
||||
UINT8 Reserved[31];
|
||||
} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
|
||||
|
||||
//
|
||||
// FACS Version (as defined in ACPI 2.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
|
||||
|
||||
//
|
||||
// Firmware Control Structure Feature Flags
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)
|
||||
|
||||
//
|
||||
// Multiple APIC Description Table header definition. The rest of the table
|
||||
// must be defined in a platform specific manner.
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 LocalApicAddress;
|
||||
UINT32 Flags;
|
||||
} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
|
||||
|
||||
//
|
||||
// MADT Revision (as defined in ACPI 2.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Multiple APIC Flags
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_2_0_PCAT_COMPAT (1 << 0)
|
||||
|
||||
//
|
||||
// Multiple APIC Description Table APIC structure types
|
||||
// All other values between 0x09 an 0xFF are reserved and
|
||||
// will be ignored by OSPM.
|
||||
//
|
||||
#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00
|
||||
#define EFI_ACPI_2_0_IO_APIC 0x01
|
||||
#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02
|
||||
#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
|
||||
#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04
|
||||
#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
|
||||
#define EFI_ACPI_2_0_IO_SAPIC 0x06
|
||||
#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07
|
||||
#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08
|
||||
|
||||
//
|
||||
// APIC Structure Definitions
|
||||
//
|
||||
//
|
||||
// Processor Local APIC Structure Definition
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 AcpiProcessorId;
|
||||
UINT8 ApicId;
|
||||
UINT32 Flags;
|
||||
} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC Flags. All other bits are reserved and must be 0.
|
||||
//
|
||||
#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)
|
||||
|
||||
//
|
||||
// IO APIC Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 IoApicId;
|
||||
UINT8 Reserved;
|
||||
UINT32 IoApicAddress;
|
||||
UINT32 GlobalSystemInterruptBase;
|
||||
} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Interrupt Source Override Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 Bus;
|
||||
UINT8 Source;
|
||||
UINT32 GlobalSystemInterrupt;
|
||||
UINT16 Flags;
|
||||
} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
|
||||
|
||||
//
|
||||
// Non-Maskable Interrupt Source Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Flags;
|
||||
UINT32 GlobalSystemInterrupt;
|
||||
} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC NMI Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 AcpiProcessorId;
|
||||
UINT16 Flags;
|
||||
UINT8 LocalApicLint;
|
||||
} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC Address Override Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Reserved;
|
||||
UINT64 LocalApicAddress;
|
||||
} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
|
||||
|
||||
//
|
||||
// IO SAPIC Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 IoApicId;
|
||||
UINT8 Reserved;
|
||||
UINT32 GlobalSystemInterruptBase;
|
||||
UINT64 IoSapicAddress;
|
||||
} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local SAPIC Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 AcpiProcessorId;
|
||||
UINT8 LocalSapicId;
|
||||
UINT8 LocalSapicEid;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 Flags;
|
||||
} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Platform Interrupt Sources Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Flags;
|
||||
UINT8 InterruptType;
|
||||
UINT8 ProcessorId;
|
||||
UINT8 ProcessorEid;
|
||||
UINT8 IoSapicVector;
|
||||
UINT32 GlobalSystemInterrupt;
|
||||
UINT32 Reserved;
|
||||
} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
|
||||
|
||||
//
|
||||
// Smart Battery Description Table (SBST)
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 WarningEnergyLevel;
|
||||
UINT32 LowEnergyLevel;
|
||||
UINT32 CriticalEnergyLevel;
|
||||
} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
|
||||
|
||||
//
|
||||
// SBST Version (as defined in ACPI 2.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Embedded Controller Boot Resources Table (ECDT)
|
||||
// The table is followed by a null terminated ASCII string that contains
|
||||
// a fully qualified reference to the name space object.
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
|
||||
UINT32 Uid;
|
||||
UINT8 GpeBit;
|
||||
} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
|
||||
|
||||
//
|
||||
// ECDT Version (as defined in ACPI 2.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Known table signatures
|
||||
//
|
||||
//
|
||||
// "RSD PTR " Root System Description Pointer
|
||||
//
|
||||
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
|
||||
|
||||
//
|
||||
// "SPIC" Multiple SAPIC Description Table
|
||||
//
|
||||
// BUGBUG: Don't know where this came from except SR870BN4 uses it.
|
||||
// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
|
||||
//
|
||||
#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
|
||||
|
||||
//
|
||||
// "BOOT" MS Simple Boot Spec
|
||||
//
|
||||
#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
|
||||
|
||||
//
|
||||
// "DBGP" MS Bebug Port Spec
|
||||
//
|
||||
#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
|
||||
|
||||
//
|
||||
// "DSDT" Differentiated System Description Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
|
||||
|
||||
//
|
||||
// "ECDT" Embedded Controller Boot Resources Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
|
||||
|
||||
//
|
||||
// "ETDT" Event Timer Description Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445
|
||||
|
||||
//
|
||||
// "FACS" Firmware ACPI Control Structure
|
||||
//
|
||||
#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
|
||||
|
||||
//
|
||||
// "FACP" Fixed ACPI Description Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
|
||||
|
||||
//
|
||||
// "APIC" Multiple APIC Description Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
|
||||
|
||||
//
|
||||
// "PSDT" Persistent System Description Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
|
||||
|
||||
//
|
||||
// "RSDT" Root System Description Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
|
||||
|
||||
//
|
||||
// "SBST" Smart Battery Specification Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
|
||||
|
||||
//
|
||||
// "SLIT" System Locality Information Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53
|
||||
|
||||
//
|
||||
// "SPCR" Serial Port Concole Redirection Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053
|
||||
|
||||
//
|
||||
// "SRAT" Static Resource Affinity Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
|
||||
|
||||
//
|
||||
// "SSDT" Secondary System Description Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
|
||||
|
||||
//
|
||||
// "SPMI" Server Platform Management Interface Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE 0x494D5053
|
||||
|
||||
//
|
||||
// "XSDT" Extended System Description Table
|
||||
//
|
||||
#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,681 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
Acpi3_0.h
|
||||
|
||||
Abstract:
|
||||
|
||||
ACPI 3.0 definitions from the ACPI Specification Revision 3.0
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _ACPI_3_0_H_
|
||||
#define _ACPI_3_0_H_
|
||||
|
||||
//
|
||||
// Statements that include other files
|
||||
//
|
||||
#include "AcpiCommon.h"
|
||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack(1)
|
||||
//
|
||||
// ACPI Specification Revision
|
||||
//
|
||||
#define EFI_ACPI_3_0_REVISION 0x03
|
||||
|
||||
//
|
||||
// ACPI 3.0 Generic Address Space definition
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 AddressSpaceId;
|
||||
UINT8 RegisterBitWidth;
|
||||
UINT8 RegisterBitOffset;
|
||||
UINT8 AccessSize;
|
||||
UINT64 Address;
|
||||
} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
|
||||
|
||||
//
|
||||
// Generic Address Space Address IDs
|
||||
//
|
||||
#define EFI_ACPI_3_0_SYSTEM_MEMORY 0
|
||||
#define EFI_ACPI_3_0_SYSTEM_IO 1
|
||||
#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2
|
||||
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3
|
||||
#define EFI_ACPI_3_0_SMBUS 4
|
||||
#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
|
||||
|
||||
//
|
||||
// Generic Address Space Access Sizes
|
||||
//
|
||||
#define EFI_ACPI_3_0_UNDEFINED 0
|
||||
#define EFI_ACPI_3_0_BYTE 1
|
||||
#define EFI_ACPI_3_0_WORD 2
|
||||
#define EFI_ACPI_3_0_DWORD 3
|
||||
#define EFI_ACPI_3_0_QWORD 4
|
||||
|
||||
//
|
||||
// ACPI 3.0 table structures
|
||||
//
|
||||
//
|
||||
// Root System Description Pointer Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 Signature;
|
||||
UINT8 Checksum;
|
||||
UINT8 OemId[6];
|
||||
UINT8 Revision;
|
||||
UINT32 RsdtAddress;
|
||||
UINT32 Length;
|
||||
UINT64 XsdtAddress;
|
||||
UINT8 ExtendedChecksum;
|
||||
UINT8 Reserved[3];
|
||||
} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
|
||||
|
||||
//
|
||||
// RSD_PTR Revision (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 // ACPISpec30 (Revision 3.0) says current value is 2
|
||||
//
|
||||
// Common table header, this prefaces all ACPI tables, including FACS, but
|
||||
// excluding the RSD PTR structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
UINT32 Length;
|
||||
} EFI_ACPI_3_0_COMMON_HEADER;
|
||||
|
||||
//
|
||||
// Root System Description Table
|
||||
// No definition needed as it is a common description table header followed by a
|
||||
// variable number of UINT32 table pointers.
|
||||
//
|
||||
//
|
||||
// RSDT Revision (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Extended System Description Table
|
||||
// No definition needed as it is a common description table header followed by a
|
||||
// variable number of UINT64 table pointers.
|
||||
//
|
||||
//
|
||||
// XSDT Revision (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Fixed ACPI Description Table Structure (FADT)
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 FirmwareCtrl;
|
||||
UINT32 Dsdt;
|
||||
UINT8 Reserved0;
|
||||
UINT8 PreferredPmProfile;
|
||||
UINT16 SciInt;
|
||||
UINT32 SmiCmd;
|
||||
UINT8 AcpiEnable;
|
||||
UINT8 AcpiDisable;
|
||||
UINT8 S4BiosReq;
|
||||
UINT8 PstateCnt;
|
||||
UINT32 Pm1aEvtBlk;
|
||||
UINT32 Pm1bEvtBlk;
|
||||
UINT32 Pm1aCntBlk;
|
||||
UINT32 Pm1bCntBlk;
|
||||
UINT32 Pm2CntBlk;
|
||||
UINT32 PmTmrBlk;
|
||||
UINT32 Gpe0Blk;
|
||||
UINT32 Gpe1Blk;
|
||||
UINT8 Pm1EvtLen;
|
||||
UINT8 Pm1CntLen;
|
||||
UINT8 Pm2CntLen;
|
||||
UINT8 PmTmrLen;
|
||||
UINT8 Gpe0BlkLen;
|
||||
UINT8 Gpe1BlkLen;
|
||||
UINT8 Gpe1Base;
|
||||
UINT8 CstCnt;
|
||||
UINT16 PLvl2Lat;
|
||||
UINT16 PLvl3Lat;
|
||||
UINT16 FlushSize;
|
||||
UINT16 FlushStride;
|
||||
UINT8 DutyOffset;
|
||||
UINT8 DutyWidth;
|
||||
UINT8 DayAlrm;
|
||||
UINT8 MonAlrm;
|
||||
UINT8 Century;
|
||||
UINT16 IaPcBootArch;
|
||||
UINT8 Reserved1;
|
||||
UINT32 Flags;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
|
||||
UINT8 ResetValue;
|
||||
UINT8 Reserved2[3];
|
||||
UINT64 XFirmwareCtrl;
|
||||
UINT64 XDsdt;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
|
||||
} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
|
||||
|
||||
//
|
||||
// FADT Version (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04
|
||||
|
||||
//
|
||||
// Fixed ACPI Description Table Preferred Power Management Profile
|
||||
//
|
||||
#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0
|
||||
#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1
|
||||
#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2
|
||||
#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3
|
||||
#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4
|
||||
#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5
|
||||
#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6
|
||||
#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7
|
||||
|
||||
//
|
||||
// Fixed ACPI Description Table Boot Architecture Flags
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_LEGACY_DEVICES (1 << 0)
|
||||
#define EFI_ACPI_3_0_8042 (1 << 1)
|
||||
#define EFI_ACPI_3_0_VGA_NOT_PRESENT (1 << 2)
|
||||
#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED (1 << 3)
|
||||
#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS (1 << 4)
|
||||
//
|
||||
// Fixed ACPI Description Table Fixed Feature Flags
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_WBINVD (1 << 0)
|
||||
#define EFI_ACPI_3_0_WBINVD_FLUSH (1 << 1)
|
||||
#define EFI_ACPI_3_0_PROC_C1 (1 << 2)
|
||||
#define EFI_ACPI_3_0_P_LVL2_UP (1 << 3)
|
||||
#define EFI_ACPI_3_0_PWR_BUTTON (1 << 4)
|
||||
#define EFI_ACPI_3_0_SLP_BUTTON (1 << 5)
|
||||
#define EFI_ACPI_3_0_FIX_RTC (1 << 6)
|
||||
#define EFI_ACPI_3_0_RTC_S4 (1 << 7)
|
||||
#define EFI_ACPI_3_0_TMR_VAL_EXT (1 << 8)
|
||||
#define EFI_ACPI_3_0_DCK_CAP (1 << 9)
|
||||
#define EFI_ACPI_3_0_RESET_REG_SUP (1 << 10)
|
||||
#define EFI_ACPI_3_0_SEALED_CASE (1 << 11)
|
||||
#define EFI_ACPI_3_0_HEADLESS (1 << 12)
|
||||
#define EFI_ACPI_3_0_CPU_SW_SLP (1 << 13)
|
||||
#define EFI_ACPI_3_0_PCI_EXP_WAK (1 << 14)
|
||||
#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK (1 << 15)
|
||||
#define EFI_ACPI_3_0_S4_RTC_STS_VALID (1 << 16)
|
||||
#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE (1 << 17)
|
||||
#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL (1 << 18)
|
||||
#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE (1 << 19)
|
||||
|
||||
//
|
||||
// Firmware ACPI Control Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
UINT32 Length;
|
||||
UINT32 HardwareSignature;
|
||||
UINT32 FirmwareWakingVector;
|
||||
UINT32 GlobalLock;
|
||||
UINT32 Flags;
|
||||
UINT64 XFirmwareWakingVector;
|
||||
UINT8 Version;
|
||||
UINT8 Reserved[31];
|
||||
} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
|
||||
|
||||
//
|
||||
// FACS Version (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
|
||||
|
||||
//
|
||||
// Firmware Control Structure Feature Flags
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_S4BIOS_F (1 << 0)
|
||||
|
||||
//
|
||||
// Differentiated System Description Table,
|
||||
// Secondary System Description Table
|
||||
// and Persistent System Description Table,
|
||||
// no definition needed as they are common description table header followed by a
|
||||
// definition block.
|
||||
//
|
||||
#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
|
||||
#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
|
||||
|
||||
//
|
||||
// Multiple APIC Description Table header definition. The rest of the table
|
||||
// must be defined in a platform specific manner.
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 LocalApicAddress;
|
||||
UINT32 Flags;
|
||||
} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
|
||||
|
||||
//
|
||||
// MADT Revision (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
|
||||
|
||||
//
|
||||
// Multiple APIC Flags
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_PCAT_COMPAT (1 << 0)
|
||||
|
||||
//
|
||||
// Multiple APIC Description Table APIC structure types
|
||||
// All other values between 0x09 an 0xFF are reserved and
|
||||
// will be ignored by OSPM.
|
||||
//
|
||||
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00
|
||||
#define EFI_ACPI_3_0_IO_APIC 0x01
|
||||
#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02
|
||||
#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
|
||||
#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04
|
||||
#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
|
||||
#define EFI_ACPI_3_0_IO_SAPIC 0x06
|
||||
#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07
|
||||
#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08
|
||||
|
||||
//
|
||||
// APIC Structure Definitions
|
||||
//
|
||||
//
|
||||
// Processor Local APIC Structure Definition
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 AcpiProcessorId;
|
||||
UINT8 ApicId;
|
||||
UINT32 Flags;
|
||||
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC Flags. All other bits are reserved and must be 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED (1 << 0)
|
||||
|
||||
//
|
||||
// IO APIC Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 IoApicId;
|
||||
UINT8 Reserved;
|
||||
UINT32 IoApicAddress;
|
||||
UINT32 GlobalSystemInterruptBase;
|
||||
} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Interrupt Source Override Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 Bus;
|
||||
UINT8 Source;
|
||||
UINT32 GlobalSystemInterrupt;
|
||||
UINT16 Flags;
|
||||
} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
|
||||
|
||||
//
|
||||
// Platform Interrupt Sources Structure Definition
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Flags;
|
||||
UINT8 InterruptType;
|
||||
UINT8 ProcessorId;
|
||||
UINT8 ProcessorEid;
|
||||
UINT8 IoSapicVector;
|
||||
UINT32 GlobalSystemInterrupt;
|
||||
UINT32 PlatformInterruptSourceFlags;
|
||||
UINT8 CpeiProcessorOverride;
|
||||
UINT8 Reserved[31];
|
||||
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// MPS INTI flags.
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_POLARITY (3 << 0)
|
||||
#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2)
|
||||
|
||||
//
|
||||
// Non-Maskable Interrupt Source Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Flags;
|
||||
UINT32 GlobalSystemInterrupt;
|
||||
} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC NMI Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 AcpiProcessorId;
|
||||
UINT16 Flags;
|
||||
UINT8 LocalApicLint;
|
||||
} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC Address Override Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Reserved;
|
||||
UINT64 LocalApicAddress;
|
||||
} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
|
||||
|
||||
//
|
||||
// IO SAPIC Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 IoApicId;
|
||||
UINT8 Reserved;
|
||||
UINT32 GlobalSystemInterruptBase;
|
||||
UINT64 IoSapicAddress;
|
||||
} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local SAPIC Structure
|
||||
// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 AcpiProcessorId;
|
||||
UINT8 LocalSapicId;
|
||||
UINT8 LocalSapicEid;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 Flags;
|
||||
UINT32 ACPIProcessorUIDValue;
|
||||
} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
|
||||
|
||||
//
|
||||
// Platform Interrupt Sources Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Flags;
|
||||
UINT8 InterruptType;
|
||||
UINT8 ProcessorId;
|
||||
UINT8 ProcessorEid;
|
||||
UINT8 IoSapicVector;
|
||||
UINT32 GlobalSystemInterrupt;
|
||||
UINT32 PlatformInterruptSourceFlags;
|
||||
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
|
||||
|
||||
//
|
||||
// Platform Interrupt Source Flags.
|
||||
// All other bits are reserved and must be set to 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE (1 << 0)
|
||||
|
||||
//
|
||||
// Smart Battery Description Table (SBST)
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 WarningEnergyLevel;
|
||||
UINT32 LowEnergyLevel;
|
||||
UINT32 CriticalEnergyLevel;
|
||||
} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
|
||||
|
||||
//
|
||||
// SBST Version (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Embedded Controller Boot Resources Table (ECDT)
|
||||
// The table is followed by a null terminated ASCII string that contains
|
||||
// a fully qualified reference to the name space object.
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
|
||||
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
|
||||
UINT32 Uid;
|
||||
UINT8 GpeBit;
|
||||
} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
|
||||
|
||||
//
|
||||
// ECDT Version (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// System Resource Affinity Table (SRAT. The rest of the table
|
||||
// must be defined in a platform specific manner.
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 Reserved1; // Must be set to 1
|
||||
UINT64 Reserved2;
|
||||
} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
|
||||
|
||||
//
|
||||
// SRAT Version (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02
|
||||
|
||||
//
|
||||
// SRAT structure types.
|
||||
// All other values between 0x02 an 0xFF are reserved and
|
||||
// will be ignored by OSPM.
|
||||
//
|
||||
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
|
||||
#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01
|
||||
|
||||
//
|
||||
// Processor Local APIC/SAPIC Affinity Structure Definition
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT8 ProximityDomain7To0;
|
||||
UINT8 ApicId;
|
||||
UINT32 Flags;
|
||||
UINT8 LocalSapicEid;
|
||||
UINT8 ProximityDomain31To8[3];
|
||||
UINT8 Reserved[4];
|
||||
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
|
||||
|
||||
//
|
||||
// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
|
||||
|
||||
//
|
||||
// Memory Affinity Structure Definition
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT32 ProximityDomain;
|
||||
UINT16 Reserved1;
|
||||
UINT32 AddressBaseLow;
|
||||
UINT32 AddressBaseHigh;
|
||||
UINT32 LengthLow;
|
||||
UINT32 LengthHigh;
|
||||
UINT32 Reserved2;
|
||||
UINT32 Flags;
|
||||
UINT64 Reserved3;
|
||||
} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
|
||||
|
||||
//
|
||||
// Memory Flags. All other bits are reserved and must be 0.
|
||||
//
|
||||
#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
|
||||
#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
|
||||
#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
|
||||
|
||||
//
|
||||
// System Locality Distance Information Table (SLIT).
|
||||
// The rest of the table is a matrix.
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT64 NumberOfSystemLocalities;
|
||||
} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
|
||||
|
||||
//
|
||||
// SLIT Version (as defined in ACPI 3.0 spec.)
|
||||
//
|
||||
#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Known table signatures
|
||||
//
|
||||
//
|
||||
// "RSD PTR " Root System Description Pointer
|
||||
//
|
||||
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
|
||||
|
||||
//
|
||||
// "APIC" Multiple APIC Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
|
||||
|
||||
//
|
||||
// "DSDT" Differentiated System Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
|
||||
|
||||
//
|
||||
// "ECDT" Embedded Controller Boot Resources Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
|
||||
|
||||
//
|
||||
// "FACP" Fixed ACPI Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
|
||||
|
||||
//
|
||||
// "FACS" Firmware ACPI Control Structure
|
||||
//
|
||||
#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
|
||||
|
||||
//
|
||||
// "PSDT" Persistent System Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
|
||||
|
||||
//
|
||||
// "RSDT" Root System Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
|
||||
|
||||
//
|
||||
// "SBST" Smart Battery Specification Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
|
||||
|
||||
//
|
||||
// "SLIT" System Locality Information Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53
|
||||
|
||||
//
|
||||
// "SRAT" System Resource Affinity Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
|
||||
|
||||
//
|
||||
// "SSDT" Secondary System Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
|
||||
|
||||
//
|
||||
// "XSDT" Extended System Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358
|
||||
|
||||
//
|
||||
// "BOOT" MS Simple Boot Spec
|
||||
//
|
||||
#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
|
||||
|
||||
//
|
||||
// "CPEP" Corrected Platform Error Polling Table
|
||||
// See
|
||||
//
|
||||
#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE 0x50455043
|
||||
|
||||
//
|
||||
// "DBGP" MS Debug Port Spec
|
||||
//
|
||||
#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
|
||||
|
||||
//
|
||||
// "ETDT" Event Timer Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445
|
||||
|
||||
//
|
||||
// "HPET" IA-PC High Precision Event Timer Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE 0x54455048
|
||||
|
||||
//
|
||||
// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE 0x4746434D
|
||||
|
||||
//
|
||||
// "SPCR" Serial Port Concole Redirection Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053
|
||||
|
||||
//
|
||||
// "SPMI" Server Platform Management Interface Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE 0x494D5053
|
||||
|
||||
//
|
||||
// "TCPA" Trusted Computing Platform Alliance Capabilities Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE 0x41504354
|
||||
|
||||
//
|
||||
// "WDRT" Watchdog Resource Table
|
||||
//
|
||||
#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE 0x54524457
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,98 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
AcpiCommon.h
|
||||
|
||||
Abstract:
|
||||
|
||||
This file contains some basic ACPI definitions that are consumed by drivers
|
||||
that do not care about ACPI versions.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _ACPI_COMMON_H_
|
||||
#define _ACPI_COMMON_H_
|
||||
|
||||
#include "Tiano.h"
|
||||
|
||||
//
|
||||
// Common table header, this prefaces all ACPI tables, including FACS, but
|
||||
// excluding the RSD PTR structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
UINT32 Length;
|
||||
} EFI_ACPI_COMMON_HEADER;
|
||||
|
||||
//
|
||||
// Common ACPI description table header. This structure prefaces most ACPI tables.
|
||||
//
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
UINT32 Length;
|
||||
UINT8 Revision;
|
||||
UINT8 Checksum;
|
||||
UINT8 OemId[6];
|
||||
UINT64 OemTableId;
|
||||
UINT32 OemRevision;
|
||||
UINT32 CreatorId;
|
||||
UINT32 CreatorRevision;
|
||||
} EFI_ACPI_DESCRIPTION_HEADER;
|
||||
|
||||
#pragma pack()
|
||||
//
|
||||
// Define for Pci Host Bridge Resource Allocation
|
||||
//
|
||||
#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
|
||||
#define ACPI_END_TAG_DESCRIPTOR 0x79
|
||||
|
||||
#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
|
||||
#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
|
||||
#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
|
||||
|
||||
//
|
||||
// Make sure structures match spec
|
||||
//
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct {
|
||||
UINT8 Desc;
|
||||
UINT16 Len;
|
||||
UINT8 ResType;
|
||||
UINT8 GenFlag;
|
||||
UINT8 SpecificFlag;
|
||||
UINT64 AddrSpaceGranularity;
|
||||
UINT64 AddrRangeMin;
|
||||
UINT64 AddrRangeMax;
|
||||
UINT64 AddrTranslationOffset;
|
||||
UINT64 AddrLen;
|
||||
} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Desc;
|
||||
UINT8 Checksum;
|
||||
} EFI_ACPI_END_TAG_DESCRIPTOR;
|
||||
|
||||
//
|
||||
// General use definitions
|
||||
//
|
||||
#define EFI_ACPI_RESERVED_BYTE 0x00
|
||||
#define EFI_ACPI_RESERVED_WORD 0x0000
|
||||
#define EFI_ACPI_RESERVED_DWORD 0x00000000
|
||||
#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,123 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
AlertStandardFormatTable.h
|
||||
|
||||
Abstract:
|
||||
|
||||
ACPI Alert Standard Format Description Table ASF! as described
|
||||
in the ASF2.0 Specification
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _ALERT_STANDARD_FORMAT_TABLE_H
|
||||
#define _ALERT_STANDARD_FORMAT_TABLE_H
|
||||
|
||||
#include "Acpi2_0.h"
|
||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack (1)
|
||||
|
||||
//
|
||||
// Information Record header that appears at the beginning of each record
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Reserved;
|
||||
UINT16 RecordLength;
|
||||
} EFI_ACPI_ASF_RECORD_HEADER;
|
||||
|
||||
//
|
||||
// This structure contains information that identifies the system type
|
||||
// and configuration
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
|
||||
UINT8 MinWatchDogResetValue;
|
||||
UINT8 MinPollingInterval;
|
||||
UINT16 SystemID;
|
||||
UINT32 IANAManufactureID;
|
||||
UINT8 FeatureFlags;
|
||||
UINT8 Reserved[3];
|
||||
} EFI_ACPI_ASF_INFO;
|
||||
|
||||
//
|
||||
// Alert sensors definition
|
||||
//
|
||||
#define ASF_ALRT_SENSOR_ARRAY_LENGTH 36
|
||||
|
||||
typedef struct {
|
||||
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
|
||||
UINT8 AssertionEventBitMask;
|
||||
UINT8 DeassertionEventBitMask;
|
||||
UINT8 NumberOfAlerts;
|
||||
UINT8 ArrayElementLength;
|
||||
UINT8 DeviceArray[ASF_ALRT_SENSOR_ARRAY_LENGTH];
|
||||
} EFI_ACPI_ASF_ALRT;
|
||||
|
||||
//
|
||||
// Alert Remote Control System Actions
|
||||
//
|
||||
#define ASF_RCTL_DEVICES_ARRAY_LENGTH 16
|
||||
typedef struct {
|
||||
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
|
||||
UINT8 NumberOfControls;
|
||||
UINT8 ArrayElementLength;
|
||||
UINT16 RctlReserved;
|
||||
UINT8 ControlArray[ASF_RCTL_DEVICES_ARRAY_LENGTH];
|
||||
} EFI_ACPI_ASF_RCTL;
|
||||
|
||||
//
|
||||
// Remote Control Capabilities
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
|
||||
UINT8 RemoteControlCapabilities[7];
|
||||
UINT8 RMCPCompletionCode;
|
||||
UINT32 RMCPIANA;
|
||||
UINT8 RMCPSpecialCommand;
|
||||
UINT8 RMCPSpecialCommandParameter[2];
|
||||
UINT8 RMCPBootOptions[2];
|
||||
UINT8 RMCPOEMParameters[2];
|
||||
} EFI_ACPI_ASF_RMCP;
|
||||
|
||||
//
|
||||
// SMBus Devices with fixed addresses
|
||||
//
|
||||
#define ASF_ADDR_DEVICE_ARRAY_LENGTH 16
|
||||
typedef struct {
|
||||
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
|
||||
UINT8 SEEPROMAddress;
|
||||
UINT8 NumberOfDevices;
|
||||
UINT8 FixedSmbusAddresses[ASF_ADDR_DEVICE_ARRAY_LENGTH];
|
||||
} EFI_ACPI_ASF_ADDR;
|
||||
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
EFI_ACPI_ASF_INFO AsfInfo;
|
||||
EFI_ACPI_ASF_ALRT AsfAlert;
|
||||
EFI_ACPI_ASF_RCTL AsfRctl;
|
||||
EFI_ACPI_ASF_RMCP AsfRmcp;
|
||||
EFI_ACPI_ASF_ADDR AsfAddr;
|
||||
} EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE;
|
||||
|
||||
//
|
||||
// "ASF!" ASF Description Table Signature
|
||||
//
|
||||
#define EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE 0x21465341
|
||||
|
||||
#pragma pack ()
|
||||
|
||||
#endif // _ALERT_STANDARD_FORMAT_TABLE_H
|
||||
@@ -0,0 +1,202 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
DMARemappingReportingTable.h
|
||||
|
||||
Abstract:
|
||||
|
||||
The definition for ACPI DMA-Remapping Reporting (DMAR) Table.
|
||||
It is defined in "Intel VT for Direct IO Architecture Specification".
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
|
||||
#define _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
|
||||
|
||||
#include "AcpiCommon.h"
|
||||
|
||||
//
|
||||
// "DMAR" DMAR Description Table Signature
|
||||
//
|
||||
#define EFI_ACPI_DMAR_DESCRIPTION_TABLE_SIGNATURE 0x52414d44
|
||||
|
||||
//
|
||||
// DMAR Revision
|
||||
//
|
||||
#define EFI_ACPI_DMAR_DESCRIPTION_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack (1)
|
||||
|
||||
//
|
||||
// Definition for DMA Remapping Structure Types
|
||||
//
|
||||
#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_DRHD 0
|
||||
#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_RMRR 1
|
||||
#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_ATSR 2
|
||||
|
||||
//
|
||||
// Definition for DMA Remapping Structure Header
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Type;
|
||||
UINT16 Length;
|
||||
} EFI_ACPI_DMAR_STRUCTURE_HEADER;
|
||||
|
||||
//
|
||||
// Definition for DMA-Remapping PCI Path
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Device;
|
||||
UINT8 Function;
|
||||
} EFI_ACPI_DMAR_PCI_PATH;
|
||||
|
||||
//
|
||||
// Definition for DMA-Remapping Device Scope Entry Structure
|
||||
//
|
||||
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ENDPOINT 0x01
|
||||
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_BRIDGE 0x02
|
||||
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03
|
||||
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04
|
||||
typedef struct {
|
||||
UINT8 DeviceScopeEntryType;
|
||||
UINT8 Length;
|
||||
UINT16 Reserved_2;
|
||||
UINT8 EnumerationID;
|
||||
UINT8 StartingBusNumber;
|
||||
} EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
|
||||
|
||||
//
|
||||
// Definition for DMA-Remapping Hardware Definition (DRHD) Structure
|
||||
//
|
||||
#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_SET 0x1
|
||||
#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_CLEAR 0x0
|
||||
typedef struct {
|
||||
UINT16 Type;
|
||||
UINT16 Length;
|
||||
UINT8 Flags;
|
||||
UINT8 Reserved_5;
|
||||
UINT16 SegmentNumber;
|
||||
UINT64 RegisterBaseAddress;
|
||||
} EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
|
||||
|
||||
//
|
||||
// Definition for Reserved Memory Region Reporting (RMRR) Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Type;
|
||||
UINT16 Length;
|
||||
UINT8 Reserved_4[2];
|
||||
UINT16 SegmentNumber;
|
||||
UINT64 ReservedMemoryRegionBaseAddress;
|
||||
UINT64 ReservedMemoryRegionLimitAddress;
|
||||
} EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
|
||||
|
||||
//
|
||||
// Definition for Root Port ATS Capability Reporting (ATSR) Structure
|
||||
//
|
||||
#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_SET 0x1
|
||||
#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_CLEAR 0x0
|
||||
typedef struct {
|
||||
UINT16 Type;
|
||||
UINT16 Length;
|
||||
UINT8 Flags;
|
||||
UINT8 Reserved_5;
|
||||
UINT16 SegmentNumber;
|
||||
} EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
|
||||
|
||||
//
|
||||
// Definition for DMA Remapping Structure
|
||||
//
|
||||
typedef union {
|
||||
EFI_ACPI_DMAR_STRUCTURE_HEADER DMARStructureHeader;
|
||||
EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE DMARHardwareUnitDefinition;
|
||||
EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE DMARReservedMemoryRegionReporting;
|
||||
EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE DMARRootPortATSCapabilityReporting;
|
||||
} EFI_ACPI_DMA_REMAPPING_STRUCTURE;
|
||||
|
||||
//
|
||||
// Definition for DMA-Remapping Reporting ACPI Table
|
||||
//
|
||||
#define EFI_ACPI_DMAR_TABLE_FLAGS_INTR_REMAP_SET 0x01
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT8 HostAddressWidth;
|
||||
UINT8 Flags;
|
||||
UINT8 Reserved_38[10];
|
||||
} EFI_ACPI_DMAR_DESCRIPTION_TABLE;
|
||||
|
||||
//
|
||||
// The Platform specific definition can be as follows:
|
||||
// NOTE: we use /**/ as comment for user convenience to copy it.
|
||||
//
|
||||
|
||||
/*
|
||||
|
||||
//
|
||||
// Dmar.h
|
||||
//
|
||||
|
||||
#define EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES 0x01 // user need to update
|
||||
typedef struct {
|
||||
EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE Header;
|
||||
EFI_ACPI_DMAR_PCI_PATH PciPath[EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES];
|
||||
} EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
|
||||
|
||||
#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY 0x01 // user need to update
|
||||
typedef struct {
|
||||
EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE Header;
|
||||
EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY];
|
||||
} EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
|
||||
|
||||
#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY 0x01 // user need to update
|
||||
typedef struct {
|
||||
EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE Header;
|
||||
EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY];
|
||||
} EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
|
||||
|
||||
#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY 0x01 // user need to update
|
||||
typedef struct {
|
||||
EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE Header;
|
||||
EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY];
|
||||
} EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
|
||||
|
||||
#define EFI_ACPI_DMAR_DHRD_ENTRY_COUNT 0x1 // user need to update
|
||||
#define EFI_ACPI_DMAR_RMRR_ENTRY_COUNT 0x1 // user need to update
|
||||
#define EFI_ACPI_DMAR_ATSR_ENTRY_COUNT 0x1 // user need to update
|
||||
|
||||
typedef struct {
|
||||
EFI_ACPI_DMAR_DESCRIPTION_TABLE Header;
|
||||
|
||||
#if EFI_ACPI_3_0_DMAR_DHRD_ENTRY_COUNT > 0
|
||||
EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE Dhrd[EFI_ACPI_DMAR_DHRD_ENTRY_COUNT];
|
||||
#endif
|
||||
|
||||
#if EFI_ACPI_3_0_DMAR_RMRR_ENTRY_COUNT > 0
|
||||
EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE Rmrr[EFI_ACPI_DMAR_RMRR_ENTRY_COUNT];
|
||||
#endif
|
||||
|
||||
#if EFI_ACPI_3_0_DMAR_ATSR_ENTRY_COUNT > 0
|
||||
EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE Atsr[EFI_ACPI_DMAR_ATSR_ENTRY_COUNT];
|
||||
#endif
|
||||
|
||||
} EFI_ACPI_3_0_DMA_REMAPPING_REPORTING_TABLE;
|
||||
|
||||
*/
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
HighPrecisionEventTimerTable.h
|
||||
|
||||
Abstract:
|
||||
|
||||
ACPI high precision event timer table definition, defined at
|
||||
Intel IA-PC HPET (High Precision Event Timers) Specification.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
|
||||
#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
|
||||
|
||||
//
|
||||
// Include files
|
||||
//
|
||||
#include "Acpi2_0.h"
|
||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack(1)
|
||||
//
|
||||
// High Precision Event Timer Table header definition.
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT32 EventTimerBlockId;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;
|
||||
UINT8 HpetNumber;
|
||||
UINT16 MainCounterMinimumClockTickInPeriodicMode;
|
||||
UINT8 PageProtectionAndOemAttribute;
|
||||
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
|
||||
|
||||
//
|
||||
// HPET Revision (defined in spec)
|
||||
//
|
||||
#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// Page protection setting
|
||||
// Values 3 through 15 are reserved for use by the specification
|
||||
//
|
||||
#define EFI_ACPI_NO_PAGE_PROTECTION 0
|
||||
#define EFI_ACPI_4KB_PAGE_PROTECTION 1
|
||||
#define EFI_ACPI_64KB_PAGE_PROTECTION 2
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,283 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
LegacyBiosMpTable.h
|
||||
|
||||
Abstract:
|
||||
Defives data structures per Multi Processor Specification Ver 1.4.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef LEGACY_BIOS_MPTABLE_H_
|
||||
#define LEGACY_BIOS_MPTABLE_H_
|
||||
|
||||
#include "Tiano.h"
|
||||
|
||||
#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
|
||||
|
||||
//
|
||||
// Define MP table structures. All are packed.
|
||||
//
|
||||
#pragma pack(push, 1)
|
||||
|
||||
#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE EFI_SIGNATURE_32 ('_', 'M', 'P', '_')
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
UINT32 PhysicalAddress;
|
||||
UINT8 Length;
|
||||
UINT8 SpecRev;
|
||||
UINT8 Checksum;
|
||||
UINT8 FeatureByte1;
|
||||
struct {
|
||||
UINT32 Reserved1 : 6;
|
||||
UINT32 MutipleClk : 1;
|
||||
UINT32 Imcr : 1;
|
||||
UINT32 Reserved2 : 24;
|
||||
} FeatureByte2_5;
|
||||
} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;
|
||||
|
||||
#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'M', 'P')
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
UINT16 BaseTableLength;
|
||||
UINT8 SpecRev;
|
||||
UINT8 Checksum;
|
||||
CHAR8 OemId[8];
|
||||
CHAR8 OemProductId[12];
|
||||
UINT32 OemTablePointer;
|
||||
UINT16 OemTableSize;
|
||||
UINT16 EntryCount;
|
||||
UINT32 LocalApicAddress;
|
||||
UINT16 ExtendedTableLength;
|
||||
UINT8 ExtendedChecksum;
|
||||
UINT8 Reserved;
|
||||
} EFI_LEGACY_MP_TABLE_HEADER;
|
||||
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;
|
||||
|
||||
//
|
||||
// Entry Type 0: Processor.
|
||||
//
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
UINT8 Id;
|
||||
UINT8 Ver;
|
||||
struct {
|
||||
UINT8 Enabled : 1;
|
||||
UINT8 Bsp : 1;
|
||||
UINT8 Reserved : 6;
|
||||
} Flags;
|
||||
struct {
|
||||
UINT32 Stepping : 4;
|
||||
UINT32 Model : 4;
|
||||
UINT32 Family : 4;
|
||||
UINT32 Reserved : 20;
|
||||
} Signature;
|
||||
struct {
|
||||
UINT32 Fpu : 1;
|
||||
UINT32 Reserved1 : 6;
|
||||
UINT32 Mce : 1;
|
||||
UINT32 Cx8 : 1;
|
||||
UINT32 Apic : 1;
|
||||
UINT32 Reserved2 : 22;
|
||||
} Features;
|
||||
UINT32 Reserved1;
|
||||
UINT32 Reserved2;
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;
|
||||
|
||||
//
|
||||
// Entry Type 1: Bus.
|
||||
//
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
UINT8 Id;
|
||||
CHAR8 TypeString[6];
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_BUS;
|
||||
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus
|
||||
//
|
||||
// Entry Type 2: I/O APIC.
|
||||
//
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
UINT8 Id;
|
||||
UINT8 Ver;
|
||||
struct {
|
||||
UINT8 Enabled : 1;
|
||||
UINT8 Reserved : 7;
|
||||
} Flags;
|
||||
UINT32 Address;
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;
|
||||
|
||||
//
|
||||
// Entry Type 3: I/O Interrupt Assignment.
|
||||
//
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
UINT8 IntType;
|
||||
struct {
|
||||
UINT16 Polarity : 2;
|
||||
UINT16 Trigger : 2;
|
||||
UINT16 Reserved : 12;
|
||||
} Flags;
|
||||
UINT8 SourceBusId;
|
||||
union {
|
||||
struct {
|
||||
UINT8 IntNo : 2;
|
||||
UINT8 Dev : 5;
|
||||
UINT8 Reserved : 1;
|
||||
} fields;
|
||||
UINT8 byte;
|
||||
} SourceBusIrq;
|
||||
UINT8 DestApicId;
|
||||
UINT8 DestApicIntIn;
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;
|
||||
|
||||
typedef enum {
|
||||
EfiLegacyMpTableEntryIoIntTypeInt = 0,
|
||||
EfiLegacyMpTableEntryIoIntTypeNmi = 1,
|
||||
EfiLegacyMpTableEntryIoIntTypeSmi = 2,
|
||||
EfiLegacyMpTableEntryIoIntTypeExtInt= 3,
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;
|
||||
|
||||
typedef enum {
|
||||
EfiLegacyMpTableEntryIoIntFlagsPolaritySpec = 0x0,
|
||||
EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1,
|
||||
EfiLegacyMpTableEntryIoIntFlagsPolarityReserved = 0x2,
|
||||
EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow = 0x3,
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;
|
||||
|
||||
typedef enum {
|
||||
EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0,
|
||||
EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1,
|
||||
EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2,
|
||||
EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3,
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;
|
||||
|
||||
//
|
||||
// Entry Type 4: Local Interrupt Assignment.
|
||||
//
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
UINT8 IntType;
|
||||
struct {
|
||||
UINT16 Polarity : 2;
|
||||
UINT16 Trigger : 2;
|
||||
UINT16 Reserved : 12;
|
||||
} Flags;
|
||||
UINT8 SourceBusId;
|
||||
UINT8 SourceBusIrq;
|
||||
UINT8 DestApicId;
|
||||
UINT8 DestApicIntIn;
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;
|
||||
|
||||
typedef enum {
|
||||
EfiLegacyMpTableEntryLocalIntTypeInt = 0,
|
||||
EfiLegacyMpTableEntryLocalIntTypeNmi = 1,
|
||||
EfiLegacyMpTableEntryLocalIntTypeSmi = 2,
|
||||
EfiLegacyMpTableEntryLocalIntTypeExtInt = 3,
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;
|
||||
|
||||
typedef enum {
|
||||
EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0,
|
||||
EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1,
|
||||
EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2,
|
||||
EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;
|
||||
|
||||
typedef enum {
|
||||
EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0,
|
||||
EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1,
|
||||
EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2,
|
||||
EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3,
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;
|
||||
|
||||
//
|
||||
// Entry Type 128: System Address Space Mapping.
|
||||
//
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
UINT8 Length;
|
||||
UINT8 BusId;
|
||||
UINT8 AddressType;
|
||||
UINT64 AddressBase;
|
||||
UINT64 AddressLength;
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;
|
||||
|
||||
typedef enum {
|
||||
EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo = 0,
|
||||
EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory = 1,
|
||||
EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2,
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE;
|
||||
|
||||
//
|
||||
// Entry Type 129: Bus Hierarchy.
|
||||
//
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
UINT8 Length;
|
||||
UINT8 BusId;
|
||||
struct {
|
||||
UINT8 SubtractiveDecode : 1;
|
||||
UINT8 Reserved : 7;
|
||||
} BusInfo;
|
||||
UINT8 ParentBus;
|
||||
UINT8 Reserved1;
|
||||
UINT8 Reserved2;
|
||||
UINT8 Reserved3;
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;
|
||||
|
||||
//
|
||||
// Entry Type 130: Compatibility Bus Address Space Modifier.
|
||||
//
|
||||
#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
|
||||
typedef struct {
|
||||
UINT8 EntryType;
|
||||
UINT8 Length;
|
||||
UINT8 BusId;
|
||||
struct {
|
||||
UINT8 RangeMode : 1;
|
||||
UINT8 Reserved : 7;
|
||||
} AddrMode;
|
||||
UINT32 PredefinedRangeList;
|
||||
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,56 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
MemoryMappedConfigurationSpaceAccessTable.h
|
||||
|
||||
Abstract:
|
||||
|
||||
ACPI memory mapped configuration space access table definition, defined at
|
||||
in the PCI Firmware Specification, version 3.0.
|
||||
Specification is available at http://www.pcisig.com.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
|
||||
#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
|
||||
|
||||
//
|
||||
// Include files
|
||||
//
|
||||
#include "AcpiCommon.h"
|
||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack(1)
|
||||
//
|
||||
// Memory Mapped Configuration Space Access Table (MCFG)
|
||||
// This table is a basic description table header followed by
|
||||
// a number of base address allocation structures.
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 BaseAddress;
|
||||
UINT16 PciSegmentGroupNumber;
|
||||
UINT8 StartBusNumber;
|
||||
UINT8 EndBusNumber;
|
||||
UINT32 Reserved;
|
||||
} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
|
||||
|
||||
//
|
||||
// MCFG Revision (defined in spec)
|
||||
//
|
||||
#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,73 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
SdramSpd.h
|
||||
|
||||
Abstract:
|
||||
|
||||
This file contains definitions for the SPD fields on an SDRAM.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _SDRAM_SPD_H
|
||||
#define _SDRAM_SPD_H
|
||||
|
||||
//
|
||||
// SDRAM SPD field definitions
|
||||
//
|
||||
#define SPD_MEMORY_TYPE 2
|
||||
#define SPD_SDRAM_ROW_ADDR 3
|
||||
#define SPD_SDRAM_COL_ADDR 4
|
||||
#define SPD_SDRAM_MODULE_ROWS 5
|
||||
#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
|
||||
#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
|
||||
#define SPD_SDRAM_ECC_SUPPORT 11
|
||||
#define SPD_SDRAM_REFRESH 12
|
||||
#define SPD_SDRAM_WIDTH 13
|
||||
#define SPD_SDRAM_ERROR_WIDTH 14
|
||||
#define SPD_SDRAM_BURST_LENGTH 16
|
||||
#define SPD_SDRAM_NO_OF_BANKS 17
|
||||
#define SPD_SDRAM_CAS_LATENCY 18
|
||||
#define SPD_SDRAM_MODULE_ATTR 21
|
||||
|
||||
#define SPD_SDRAM_TCLK1_PULSE 9 // cycle time for highest cas latency
|
||||
#define SPD_SDRAM_TAC1_PULSE 10 // access time for highest cas latency
|
||||
#define SPD_SDRAM_TCLK2_PULSE 23 // cycle time for 2nd highest cas latency
|
||||
#define SPD_SDRAM_TAC2_PULSE 24 // access time for 2nd highest cas latency
|
||||
#define SPD_SDRAM_TCLK3_PULSE 25 // cycle time for 3rd highest cas latency
|
||||
#define SPD_SDRAM_TAC3_PULSE 26 // access time for 3rd highest cas latency
|
||||
#define SPD_SDRAM_MIN_PRECHARGE 27
|
||||
#define SPD_SDRAM_ACTIVE_MIN 28
|
||||
#define SPD_SDRAM_RAS_CAS 29
|
||||
#define SPD_SDRAM_RAS_PULSE 30
|
||||
#define SPD_SDRAM_DENSITY 31
|
||||
|
||||
//
|
||||
// Memory Type Definitions
|
||||
//
|
||||
#define SPD_VAL_SDR_TYPE 4 // SDR SDRAM memory
|
||||
#define SPD_VAL_DDR_TYPE 7 // DDR SDRAM memory
|
||||
#define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory
|
||||
//
|
||||
// ECC Type Definitions
|
||||
//
|
||||
#define SPD_ECC_TYPE_NONE 0x00 // No error checking
|
||||
#define SPD_ECC_TYPE_PARITY 0x01 // No error checking
|
||||
#define SPD_ECC_TYPE_ECC 0x02 // Error checking only
|
||||
//
|
||||
// Module Attributes (Bit positions)
|
||||
//
|
||||
#define SPD_BUFFERED 0x01
|
||||
#define SPD_REGISTERED 0x02
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,80 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
ServerProcessorManagementInterfaceTable.h
|
||||
|
||||
Abstract:
|
||||
|
||||
ACPI Server Processor Management Interface Table SPMI as described
|
||||
in the IPMI2.0 Specification Revistion 1.5
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
|
||||
#define _SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
|
||||
|
||||
#include "Acpi2_0.h"
|
||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack (1)
|
||||
|
||||
//
|
||||
// Server Processor Management Interface Table definition.
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT8 Reserved_36;
|
||||
UINT8 InterfaceType;
|
||||
UINT16 SpecificationRevision;
|
||||
UINT8 InterruptType;
|
||||
UINT8 GPE;
|
||||
UINT8 Reserved_42;
|
||||
UINT8 PCIDeviceFlag;
|
||||
UINT32 GlobalSystemInterrupt;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
|
||||
UINT8 PCISegmentGroup_UID1;
|
||||
UINT8 PCIBusNumber_UID2;
|
||||
UINT8 PCIDeviceNumber_UID3;
|
||||
UINT8 PCIFunctionNumber_UID4;
|
||||
} EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_DESCRIPTION_TABLE;
|
||||
|
||||
#pragma pack ()
|
||||
|
||||
//
|
||||
// SPMI Revision
|
||||
//
|
||||
#define EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISION 0x05
|
||||
|
||||
//
|
||||
// Interface Type
|
||||
//
|
||||
#define EFI_ACPI_SPMI_INTERFACE_TYPE_RESERVED 0
|
||||
#define EFI_ACPI_SPMI_INTERFACE_TYPE_KCS 1
|
||||
#define EFI_ACPI_SPMI_INTERFACE_TYPE_SMIC 2
|
||||
#define EFI_ACPI_SPMI_INTERFACE_TYPE_BT 3
|
||||
#define EFI_ACPI_SPMI_INTERFACE_TYPE_SSIF 4
|
||||
|
||||
//
|
||||
// SPMI Specfication Revision
|
||||
//
|
||||
#define EFI_ACPI_SPMI_SPECIFICATION_REVISION 0x0150
|
||||
|
||||
//
|
||||
// SPMI Interrupt Type
|
||||
//
|
||||
#define EFI_ACPI_SPMI_INTERRUPT_TYPE_SCI 0x1
|
||||
#define EFI_ACPI_SPMI_INTERRUPT_TYPE_IOAPIC 0x2
|
||||
|
||||
#endif
|
||||
576
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h
Normal file
576
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h
Normal file
@@ -0,0 +1,576 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
Smbios.h
|
||||
|
||||
Abstract:
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _SMBIOS_TABLE_H_
|
||||
#define _SMBIOS_TABLE_H_
|
||||
|
||||
#include "Tiano.h"
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
typedef UINT8 SMBIOS_TABLE_STRING;
|
||||
|
||||
typedef struct {
|
||||
UINT8 AnchorString[4];
|
||||
UINT8 EntryPointStructureChecksum;
|
||||
UINT8 EntryPointLength;
|
||||
UINT8 MajorVersion;
|
||||
UINT8 MinorVersion;
|
||||
UINT16 MaxStructureSize;
|
||||
UINT8 EntryPointRevision;
|
||||
UINT8 FormattedArea[5];
|
||||
UINT8 IntermediateAnchorString[5];
|
||||
UINT8 IntermediateChecksum;
|
||||
UINT16 TableLength;
|
||||
UINT32 TableAddress;
|
||||
UINT16 NumberOfSmbiosStructures;
|
||||
UINT8 SmbiosBcdRevision;
|
||||
} SMBIOS_TABLE_STRUCTURE;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Handle;
|
||||
} SMBIOS_TABLE_HEADER;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Vendor;
|
||||
SMBIOS_TABLE_STRING BiosVersion;
|
||||
UINT16 BiosSegment;
|
||||
SMBIOS_TABLE_STRING BiosReleaseDate;
|
||||
UINT8 BiosSize;
|
||||
UINT64 BiosCharacteristics;
|
||||
UINT8 BIOSCharacteristicsExtensionBytes[2];
|
||||
UINT8 SystemBiosMajorRelease;
|
||||
UINT8 SystemBiosMinorRelease;
|
||||
UINT8 EmbeddedControllerFirmwareMajorRelease;
|
||||
UINT8 EmbeddedControllerFirmwareMinorRelease;
|
||||
} SMBIOS_TABLE_TYPE0;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Manufacturer;
|
||||
SMBIOS_TABLE_STRING ProductName;
|
||||
SMBIOS_TABLE_STRING Version;
|
||||
SMBIOS_TABLE_STRING SerialNumber;
|
||||
EFI_GUID Uuid;
|
||||
UINT8 WakeUpType;
|
||||
SMBIOS_TABLE_STRING SKUNumber;
|
||||
SMBIOS_TABLE_STRING Family;
|
||||
} SMBIOS_TABLE_TYPE1;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Manufacturer;
|
||||
SMBIOS_TABLE_STRING ProductName;
|
||||
SMBIOS_TABLE_STRING Version;
|
||||
SMBIOS_TABLE_STRING SerialNumber;
|
||||
SMBIOS_TABLE_STRING AssetTag;
|
||||
UINT8 FeatureFlag;
|
||||
SMBIOS_TABLE_STRING LocationInChassis;
|
||||
UINT16 ChassisHandle;
|
||||
UINT8 BoardType;
|
||||
UINT8 NumberOfContainedObjectHandles;
|
||||
UINT16 ContainedObjectHandles[1];
|
||||
} SMBIOS_TABLE_TYPE2;
|
||||
|
||||
typedef struct {
|
||||
UINT8 ContainedElementType;
|
||||
UINT8 ContainedElementMinimum;
|
||||
UINT8 ContainedElementMaximum;
|
||||
} CONTAINED_ELEMENT;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Manufacturer;
|
||||
UINT8 Type;
|
||||
SMBIOS_TABLE_STRING Version;
|
||||
SMBIOS_TABLE_STRING SerialNumber;
|
||||
SMBIOS_TABLE_STRING AssetTag;
|
||||
UINT8 BootupState;
|
||||
UINT8 PowerSupplyState;
|
||||
UINT8 ThermalState;
|
||||
UINT8 SecurityStatus;
|
||||
UINT8 OemDefined[4];
|
||||
UINT8 Height;
|
||||
UINT8 NumberofPowerCords;
|
||||
UINT8 ContainedElementCount;
|
||||
UINT8 ContainedElementRecordLength;
|
||||
CONTAINED_ELEMENT ContainedElements[1];
|
||||
} SMBIOS_TABLE_TYPE3;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 Socket;
|
||||
UINT8 ProcessorType;
|
||||
UINT8 ProcessorFamily;
|
||||
SMBIOS_TABLE_STRING ProcessorManufacture;
|
||||
UINT8 ProcessorId[8];
|
||||
SMBIOS_TABLE_STRING ProcessorVersion;
|
||||
UINT8 Voltage;
|
||||
UINT16 ExternalClock;
|
||||
UINT16 MaxSpeed;
|
||||
UINT16 CurrentSpeed;
|
||||
UINT8 Status;
|
||||
UINT8 ProcessorUpgrade;
|
||||
UINT16 L1CacheHandle;
|
||||
UINT16 L2CacheHandle;
|
||||
UINT16 L3CacheHandle;
|
||||
SMBIOS_TABLE_STRING SerialNumber;
|
||||
SMBIOS_TABLE_STRING AssetTag;
|
||||
SMBIOS_TABLE_STRING PartNumber;
|
||||
} SMBIOS_TABLE_TYPE4;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 ErrDetectMethod;
|
||||
UINT8 ErrCorrectCapability;
|
||||
UINT8 SupportInterleave;
|
||||
UINT8 CurrentInterleave;
|
||||
UINT8 MaxMemoryModuleSize;
|
||||
UINT16 SupportSpeed;
|
||||
UINT16 SupportMemoryType;
|
||||
UINT8 MemoryModuleVoltage;
|
||||
UINT8 AssociatedMemorySlotNum;
|
||||
UINT16 MemoryModuleConfigHandles[1];
|
||||
// UINT8 EnableErrCorrectCapabilities;
|
||||
} SMBIOS_TABLE_TYPE5;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING SocketDesignation;
|
||||
UINT8 BankConnections;
|
||||
UINT8 CurrentSpeed;
|
||||
UINT16 CurrentMemoryType;
|
||||
UINT8 InstalledSize;
|
||||
UINT8 EnabledSize;
|
||||
UINT8 ErrorStatus;
|
||||
} SMBIOS_TABLE_TYPE6;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING SocketDesignation;
|
||||
UINT16 CacheConfiguration;
|
||||
UINT16 MaximumCacheSize;
|
||||
UINT16 InstalledSize;
|
||||
UINT16 SupportedSRAMType;
|
||||
UINT16 CurrentSRAMType;
|
||||
UINT8 CacheSpeed;
|
||||
UINT8 ErrorCorrectionType;
|
||||
UINT8 SystemCacheType;
|
||||
UINT8 Associativity;
|
||||
} SMBIOS_TABLE_TYPE7;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING InternalReferenceDesignator;
|
||||
UINT8 InternalConnectorType;
|
||||
SMBIOS_TABLE_STRING ExternalReferenceDesignator;
|
||||
UINT8 ExternalConnectorType;
|
||||
UINT8 PortType;
|
||||
} SMBIOS_TABLE_TYPE8;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING SlotDesignation;
|
||||
UINT8 SlotType;
|
||||
UINT8 SlotDataBusWidth;
|
||||
UINT8 CurrentUsage;
|
||||
UINT8 SlotLength;
|
||||
UINT16 SlotID;
|
||||
UINT8 SlotCharacteristics1;
|
||||
UINT8 SlotCharacteristics2;
|
||||
} SMBIOS_TABLE_TYPE9;
|
||||
|
||||
typedef struct {
|
||||
UINT8 DeviceType;
|
||||
SMBIOS_TABLE_STRING DescriptionString;
|
||||
} DEVICE_STRUCT;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
DEVICE_STRUCT Device[1];
|
||||
} SMBIOS_TABLE_TYPE10;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 StringCount;
|
||||
} SMBIOS_TABLE_TYPE11;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 StringCount;
|
||||
} SMBIOS_TABLE_TYPE12;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 InstallableLanguages;
|
||||
UINT8 Flags;
|
||||
UINT8 reserved[15];
|
||||
SMBIOS_TABLE_STRING CurrentLanguages;
|
||||
} SMBIOS_TABLE_TYPE13;
|
||||
|
||||
typedef struct {
|
||||
UINT8 ItemType;
|
||||
UINT16 ItemHandle;
|
||||
} GROUP_STRUCT;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING GroupName;
|
||||
GROUP_STRUCT Group[1];
|
||||
} SMBIOS_TABLE_TYPE14;
|
||||
|
||||
typedef struct {
|
||||
UINT8 LogType;
|
||||
UINT8 DataFormatType;
|
||||
} EVENT_LOG_TYPE;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT16 LogAreaLength;
|
||||
UINT16 LogHeaderStartOffset;
|
||||
UINT16 LogDataStartOffset;
|
||||
UINT8 AccessMethod;
|
||||
UINT8 LogStatus;
|
||||
UINT32 LogChangeToken;
|
||||
UINT32 AccessMethodAddress;
|
||||
UINT8 LogHeaderFormat;
|
||||
UINT8 NumberOfSupportedLogTypeDescriptors;
|
||||
UINT8 LengthOfLogTypeDescriptor;
|
||||
EVENT_LOG_TYPE EventLogTypeDescriptors[1];
|
||||
} SMBIOS_TABLE_TYPE15;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 Location;
|
||||
UINT8 Use;
|
||||
UINT8 MemoryErrorCorrection;
|
||||
UINT32 MaximumCapacity;
|
||||
UINT16 MemoryErrorInformationHandle;
|
||||
UINT16 NumberOfMemoryDevices;
|
||||
} SMBIOS_TABLE_TYPE16;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT16 MemoryArrayHandle;
|
||||
UINT16 MemoryErrorInformationHandle;
|
||||
UINT16 TotalWidth;
|
||||
UINT16 DataWidth;
|
||||
UINT16 Size;
|
||||
UINT8 FormFactor;
|
||||
UINT8 DeviceSet;
|
||||
SMBIOS_TABLE_STRING DeviceLocator;
|
||||
SMBIOS_TABLE_STRING BankLocator;
|
||||
UINT8 MemoryType;
|
||||
UINT16 TypeDetail;
|
||||
UINT16 Speed;
|
||||
SMBIOS_TABLE_STRING Manufacturer;
|
||||
SMBIOS_TABLE_STRING SerialNumber;
|
||||
SMBIOS_TABLE_STRING AssetTag;
|
||||
SMBIOS_TABLE_STRING PartNumber;
|
||||
} SMBIOS_TABLE_TYPE17;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 ErrorType;
|
||||
UINT8 ErrorGranularity;
|
||||
UINT8 ErrorOperation;
|
||||
UINT32 VendorSyndrome;
|
||||
UINT32 MemoryArrayErrorAddress;
|
||||
UINT32 DeviceErrorAddress;
|
||||
UINT32 ErrorResolution;
|
||||
} SMBIOS_TABLE_TYPE18;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT32 StartingAddress;
|
||||
UINT32 EndingAddress;
|
||||
UINT16 MemoryArrayHandle;
|
||||
UINT8 PartitionWidth;
|
||||
} SMBIOS_TABLE_TYPE19;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT32 StartingAddress;
|
||||
UINT32 EndingAddress;
|
||||
UINT16 MemoryDeviceHandle;
|
||||
UINT16 MemoryArrayMappedAddressHandle;
|
||||
UINT8 PartitionRowPosition;
|
||||
UINT8 InterleavePosition;
|
||||
UINT8 InterleavedDataDepth;
|
||||
} SMBIOS_TABLE_TYPE20;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 Type;
|
||||
UINT8 Interface;
|
||||
UINT8 NumberOfButtons;
|
||||
} SMBIOS_TABLE_TYPE21;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Location;
|
||||
SMBIOS_TABLE_STRING Manufacturer;
|
||||
SMBIOS_TABLE_STRING ManufactureDate;
|
||||
SMBIOS_TABLE_STRING SerialNumber;
|
||||
SMBIOS_TABLE_STRING DeviceName;
|
||||
UINT8 DeviceChemistry;
|
||||
UINT16 DeviceCapacity;
|
||||
UINT16 DesignVoltage;
|
||||
SMBIOS_TABLE_STRING SBDSVersionNumber;
|
||||
UINT8 MaximumErrorInBatteryData;
|
||||
UINT16 SBDSSerialNumber;
|
||||
UINT16 SBDSManufactureDate;
|
||||
SMBIOS_TABLE_STRING SBDSDeviceChemistry;
|
||||
UINT8 DesignCapacityMultiplier;
|
||||
UINT32 OEMSpecific;
|
||||
} SMBIOS_TABLE_TYPE22;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 Capabilities;
|
||||
UINT16 ResetCount;
|
||||
UINT16 ResetLimit;
|
||||
UINT16 TimerInterval;
|
||||
UINT16 Timeout;
|
||||
} SMBIOS_TABLE_TYPE23;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 HardwareSecuritySettings;
|
||||
} SMBIOS_TABLE_TYPE24;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 NextScheduledPowerOnMonth;
|
||||
UINT8 NextScheduledPowerOnDayOfMonth;
|
||||
UINT8 NextScheduledPowerOnHour;
|
||||
UINT8 NextScheduledPowerOnMinute;
|
||||
UINT8 NextScheduledPowerOnSecond;
|
||||
} SMBIOS_TABLE_TYPE25;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Description;
|
||||
UINT8 LocationAndStatus;
|
||||
UINT16 MaximumValue;
|
||||
UINT16 MinimumValue;
|
||||
UINT16 Resolution;
|
||||
UINT16 Tolerance;
|
||||
UINT16 Accuracy;
|
||||
UINT32 OEMDefined;
|
||||
UINT16 NominalValue;
|
||||
} SMBIOS_TABLE_TYPE26;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT16 TemperatureProbeHandle;
|
||||
UINT8 DeviceTypeAndStatus;
|
||||
UINT8 CoolingUnitGroup;
|
||||
UINT32 OEMDefined;
|
||||
UINT16 NominalSpeed;
|
||||
} SMBIOS_TABLE_TYPE27;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Description;
|
||||
UINT8 LocationAndStatus;
|
||||
UINT16 MaximumValue;
|
||||
UINT16 MinimumValue;
|
||||
UINT16 Resolution;
|
||||
UINT16 Tolerance;
|
||||
UINT16 Accuracy;
|
||||
UINT32 OEMDefined;
|
||||
UINT16 NominalValue;
|
||||
} SMBIOS_TABLE_TYPE28;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Description;
|
||||
UINT8 LocationAndStatus;
|
||||
UINT16 MaximumValue;
|
||||
UINT16 MinimumValue;
|
||||
UINT16 Resolution;
|
||||
UINT16 Tolerance;
|
||||
UINT16 Accuracy;
|
||||
UINT32 OEMDefined;
|
||||
UINT16 NominalValue;
|
||||
} SMBIOS_TABLE_TYPE29;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING ManufacturerName;
|
||||
UINT8 Connections;
|
||||
} SMBIOS_TABLE_TYPE30;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 Checksum;
|
||||
UINT8 Reserved1;
|
||||
UINT16 Reserved2;
|
||||
UINT32 BisEntry16;
|
||||
UINT32 BisEntry32;
|
||||
UINT64 Reserved3;
|
||||
UINT32 Reserved4;
|
||||
} SMBIOS_TABLE_TYPE31;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 Reserved[6];
|
||||
UINT8 BootStatus[1];
|
||||
} SMBIOS_TABLE_TYPE32;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 ErrorType;
|
||||
UINT8 ErrorGranularity;
|
||||
UINT8 ErrorOperation;
|
||||
UINT32 VendorSyndrome;
|
||||
UINT64 MemoryArrayErrorAddress;
|
||||
UINT64 DeviceErrorAddress;
|
||||
UINT32 ErrorResolution;
|
||||
} SMBIOS_TABLE_TYPE33;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Description;
|
||||
UINT8 Type;
|
||||
UINT32 Address;
|
||||
UINT8 AddressType;
|
||||
} SMBIOS_TABLE_TYPE34;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
SMBIOS_TABLE_STRING Description;
|
||||
UINT16 ManagementDeviceHandle;
|
||||
UINT16 ComponentHandle;
|
||||
UINT16 ThresholdHandle;
|
||||
} SMBIOS_TABLE_TYPE35;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT16 LowerThresholdNonCritical;
|
||||
UINT16 UpperThresholdNonCritical;
|
||||
UINT16 LowerThresholdCritical;
|
||||
UINT16 UpperThresholdCritical;
|
||||
UINT16 LowerThresholdNonRecoverable;
|
||||
UINT16 UpperThresholdNonRecoverable;
|
||||
} SMBIOS_TABLE_TYPE36;
|
||||
|
||||
typedef struct {
|
||||
UINT8 DeviceLoad;
|
||||
UINT16 DeviceHandle;
|
||||
} MEMORY_DEVICE;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 ChannelType;
|
||||
UINT8 MaximumChannelLoad;
|
||||
UINT8 MemoryDeviceCount;
|
||||
MEMORY_DEVICE MemoryDevice[1];
|
||||
} SMBIOS_TABLE_TYPE37;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 InterfaceType;
|
||||
UINT8 IPMISpecificationRevision;
|
||||
UINT8 I2CSlaveAddress;
|
||||
UINT8 NVStorageDeviceAddress;
|
||||
UINT64 BaseAddress;
|
||||
UINT8 BaseAddressModifier_InterruptInfo;
|
||||
UINT8 InterruptNumber;
|
||||
} SMBIOS_TABLE_TYPE38;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
UINT8 PowerUnitGroup;
|
||||
SMBIOS_TABLE_STRING Location;
|
||||
SMBIOS_TABLE_STRING DeviceName;
|
||||
SMBIOS_TABLE_STRING Manufacturer;
|
||||
SMBIOS_TABLE_STRING SerialNumber;
|
||||
SMBIOS_TABLE_STRING AssetTagNumber;
|
||||
SMBIOS_TABLE_STRING ModelPartNumber;
|
||||
SMBIOS_TABLE_STRING RevisionLevel;
|
||||
UINT16 MaxPowerCapacity;
|
||||
UINT16 PowerSupplyCharacteristics;
|
||||
UINT16 InputVoltageProbeHandle;
|
||||
UINT16 CoolingDeviceHandle;
|
||||
UINT16 InputCurrentProbeHandle;
|
||||
} SMBIOS_TABLE_TYPE39;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
} SMBIOS_TABLE_TYPE126;
|
||||
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_HEADER Hdr;
|
||||
} SMBIOS_TABLE_TYPE127;
|
||||
|
||||
typedef union {
|
||||
SMBIOS_TABLE_HEADER *Hdr;
|
||||
SMBIOS_TABLE_TYPE0 *Type0;
|
||||
SMBIOS_TABLE_TYPE1 *Type1;
|
||||
SMBIOS_TABLE_TYPE2 *Type2;
|
||||
SMBIOS_TABLE_TYPE3 *Type3;
|
||||
SMBIOS_TABLE_TYPE4 *Type4;
|
||||
SMBIOS_TABLE_TYPE5 *Type5;
|
||||
SMBIOS_TABLE_TYPE6 *Type6;
|
||||
SMBIOS_TABLE_TYPE7 *Type7;
|
||||
SMBIOS_TABLE_TYPE8 *Type8;
|
||||
SMBIOS_TABLE_TYPE9 *Type9;
|
||||
SMBIOS_TABLE_TYPE10 *Type10;
|
||||
SMBIOS_TABLE_TYPE11 *Type11;
|
||||
SMBIOS_TABLE_TYPE12 *Type12;
|
||||
SMBIOS_TABLE_TYPE13 *Type13;
|
||||
SMBIOS_TABLE_TYPE14 *Type14;
|
||||
SMBIOS_TABLE_TYPE15 *Type15;
|
||||
SMBIOS_TABLE_TYPE16 *Type16;
|
||||
SMBIOS_TABLE_TYPE17 *Type17;
|
||||
SMBIOS_TABLE_TYPE18 *Type18;
|
||||
SMBIOS_TABLE_TYPE19 *Type19;
|
||||
SMBIOS_TABLE_TYPE20 *Type20;
|
||||
SMBIOS_TABLE_TYPE21 *Type21;
|
||||
SMBIOS_TABLE_TYPE22 *Type22;
|
||||
SMBIOS_TABLE_TYPE23 *Type23;
|
||||
SMBIOS_TABLE_TYPE24 *Type24;
|
||||
SMBIOS_TABLE_TYPE25 *Type25;
|
||||
SMBIOS_TABLE_TYPE26 *Type26;
|
||||
SMBIOS_TABLE_TYPE27 *Type27;
|
||||
SMBIOS_TABLE_TYPE28 *Type28;
|
||||
SMBIOS_TABLE_TYPE29 *Type29;
|
||||
SMBIOS_TABLE_TYPE30 *Type30;
|
||||
SMBIOS_TABLE_TYPE31 *Type31;
|
||||
SMBIOS_TABLE_TYPE32 *Type32;
|
||||
SMBIOS_TABLE_TYPE33 *Type33;
|
||||
SMBIOS_TABLE_TYPE34 *Type34;
|
||||
SMBIOS_TABLE_TYPE35 *Type35;
|
||||
SMBIOS_TABLE_TYPE36 *Type36;
|
||||
SMBIOS_TABLE_TYPE37 *Type37;
|
||||
SMBIOS_TABLE_TYPE38 *Type38;
|
||||
SMBIOS_TABLE_TYPE39 *Type39;
|
||||
SMBIOS_TABLE_TYPE126 *Type126;
|
||||
SMBIOS_TABLE_TYPE127 *Type127;
|
||||
UINT8 *Raw;
|
||||
} SMBIOS_STRUCTURE_POINTER;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
1847
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Tpm12.h
Normal file
1847
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Tpm12.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,94 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
WatchdogDescriptionTable.h
|
||||
|
||||
Abstract:
|
||||
|
||||
ACPI Watchdog Description Table as defined in Intel
|
||||
ICH Family Watchdog Timer (WDT) Application Note (AP-725)
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _WATCH_DOG_DESCRIPTION_TABLE_H_
|
||||
#define _WATCH_DOG_DESCRIPTION_TABLE_H_
|
||||
|
||||
//
|
||||
// Include files
|
||||
//
|
||||
#include "Acpi2_0.h"
|
||||
|
||||
//
|
||||
// Ensure proper structure formats
|
||||
//
|
||||
#pragma pack(1)
|
||||
//
|
||||
// WDDT structure
|
||||
//
|
||||
typedef struct {
|
||||
EFI_ACPI_DESCRIPTION_HEADER Header;
|
||||
UINT16 SpecVersion;
|
||||
UINT16 TableVersion;
|
||||
UINT16 Vid;
|
||||
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
|
||||
UINT16 TimerMaxCount;
|
||||
UINT16 TimerMinCount;
|
||||
UINT16 TimerCountPeriod;
|
||||
UINT16 Status;
|
||||
UINT16 Capability;
|
||||
} EFI_ACPI_1_0_WATCH_DOG_DESCRIPTION_TABLE;
|
||||
|
||||
//
|
||||
// "WDDT" Watchdog Description Table signatures
|
||||
//
|
||||
#define EFI_ACPI_1_0_WDDT_SIGNATURE 0x54444457
|
||||
|
||||
#pragma pack()
|
||||
|
||||
//
|
||||
// WDDT Revision
|
||||
//
|
||||
#define EFI_ACPI_WATCHDOG_DESCRIPTION_1_0_TABLE_REVISION 0x01
|
||||
|
||||
//
|
||||
// WDDT Spec Version
|
||||
//
|
||||
#define EFI_ACPI_WDDT_SPEC_1_0_VERSION 0x01
|
||||
|
||||
//
|
||||
// WDDT Description Table Version
|
||||
//
|
||||
#define EFI_ACPI_WDDT_TABLE_1_0_VERSION 0x01
|
||||
|
||||
//
|
||||
// WDT Status
|
||||
//
|
||||
#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001
|
||||
#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002
|
||||
#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000
|
||||
#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004
|
||||
#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800
|
||||
#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000
|
||||
#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000
|
||||
#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000
|
||||
|
||||
//
|
||||
// WDT Capability
|
||||
//
|
||||
#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001
|
||||
#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002
|
||||
#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004
|
||||
#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008
|
||||
#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010
|
||||
|
||||
#endif
|
||||
331
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h
Normal file
331
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h
Normal file
@@ -0,0 +1,331 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
Atapi.h
|
||||
|
||||
Abstract:
|
||||
|
||||
|
||||
Revision History
|
||||
--*/
|
||||
|
||||
#ifndef _ATAPI_H
|
||||
#define _ATAPI_H
|
||||
|
||||
#include "Tiano.h"
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct {
|
||||
UINT16 config; /* General Configuration */
|
||||
UINT16 cylinders; /* Number of Cylinders */
|
||||
UINT16 reserved_2;
|
||||
UINT16 heads; /* Number of logical heads */
|
||||
UINT16 vendor_data1;
|
||||
UINT16 vendoe_data2;
|
||||
UINT16 sectors_per_track;
|
||||
UINT16 vendor_specific_7_9[3];
|
||||
CHAR8 SerialNo[20]; /* ASCII */
|
||||
UINT16 vendor_specific_20_21[2];
|
||||
UINT16 ecc_bytes_available;
|
||||
CHAR8 FirmwareVer[8]; /* ASCII */
|
||||
CHAR8 ModelName[40]; /* ASCII */
|
||||
UINT16 multi_sector_cmd_max_sct_cnt;
|
||||
UINT16 reserved_48;
|
||||
UINT16 capabilities;
|
||||
UINT16 reserved_50;
|
||||
UINT16 pio_cycle_timing;
|
||||
UINT16 reserved_52;
|
||||
UINT16 field_validity;
|
||||
UINT16 current_cylinders;
|
||||
UINT16 current_heads;
|
||||
UINT16 current_sectors;
|
||||
UINT16 CurrentCapacityLsb;
|
||||
UINT16 CurrentCapacityMsb;
|
||||
UINT16 reserved_59;
|
||||
UINT16 user_addressable_sectors_lo;
|
||||
UINT16 user_addressable_sectors_hi;
|
||||
UINT16 reserved_62;
|
||||
UINT16 multi_word_dma_mode;
|
||||
UINT16 advanced_pio_modes;
|
||||
UINT16 min_multi_word_dma_cycle_time;
|
||||
UINT16 rec_multi_word_dma_cycle_time;
|
||||
UINT16 min_pio_cycle_time_without_flow_control;
|
||||
UINT16 min_pio_cycle_time_with_flow_control;
|
||||
UINT16 reserved_69_79[11];
|
||||
UINT16 major_version_no;
|
||||
UINT16 minor_version_no;
|
||||
UINT16 reserved_82_127[46];
|
||||
UINT16 security_status;
|
||||
UINT16 vendor_data_129_159[31];
|
||||
UINT16 reserved_160_255[96];
|
||||
} IDENTIFY;
|
||||
|
||||
typedef struct {
|
||||
UINT8 peripheral_type;
|
||||
UINT8 RMB;
|
||||
UINT8 version;
|
||||
UINT8 response_data_format;
|
||||
UINT8 addnl_length;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 vendor_info[8];
|
||||
UINT8 product_id[12];
|
||||
UINT8 eeprom_product_code[4];
|
||||
UINT8 firmware_rev_level[4];
|
||||
UINT8 firmware_sub_rev_level[1];
|
||||
UINT8 reserved_37;
|
||||
UINT8 reserved_38;
|
||||
UINT8 reserved_39;
|
||||
UINT8 max_capacity_hi;
|
||||
UINT8 max_capacity_mid;
|
||||
UINT8 max_capacity_lo;
|
||||
UINT8 reserved_43_95[95 - 43 + 1];
|
||||
UINT8 vendor_id[20];
|
||||
UINT8 eeprom_drive_sno[12];
|
||||
} INQUIRY_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 error_code : 7;
|
||||
UINT8 valid : 1;
|
||||
UINT8 reserved_1;
|
||||
UINT8 sense_key : 4;
|
||||
UINT8 reserved_21 : 1;
|
||||
UINT8 ILI : 1;
|
||||
UINT8 reserved_22 : 2;
|
||||
UINT8 vendor_specific_3;
|
||||
UINT8 vendor_specific_4;
|
||||
UINT8 vendor_specific_5;
|
||||
UINT8 vendor_specific_6;
|
||||
UINT8 addnl_sense_length; // n - 7
|
||||
UINT8 vendor_specific_8;
|
||||
UINT8 vendor_specific_9;
|
||||
UINT8 vendor_specific_10;
|
||||
UINT8 vendor_specific_11;
|
||||
UINT8 addnl_sense_code; // mandatory
|
||||
UINT8 addnl_sense_code_qualifier; // mandatory
|
||||
UINT8 field_replaceable_unit_code; // optional
|
||||
UINT8 reserved_15;
|
||||
UINT8 reserved_16;
|
||||
UINT8 reserved_17;
|
||||
//
|
||||
// Followed by additional sense bytes : FIXME
|
||||
//
|
||||
} REQUEST_SENSE_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 LastLba3;
|
||||
UINT8 LastLba2;
|
||||
UINT8 LastLba1;
|
||||
UINT8 LastLba0;
|
||||
UINT8 BlockSize3;
|
||||
UINT8 BlockSize2;
|
||||
UINT8 BlockSize1;
|
||||
UINT8 BlockSize0;
|
||||
} READ_CAPACITY_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 reserved_0;
|
||||
UINT8 reserved_1;
|
||||
UINT8 reserved_2;
|
||||
UINT8 Capacity_Length;
|
||||
UINT8 LastLba3;
|
||||
UINT8 LastLba2;
|
||||
UINT8 LastLba1;
|
||||
UINT8 LastLba0;
|
||||
UINT8 DesCode : 2;
|
||||
UINT8 reserved_9 : 6;
|
||||
UINT8 BlockSize2;
|
||||
UINT8 BlockSize1;
|
||||
UINT8 BlockSize0;
|
||||
} READ_FORMAT_CAPACITY_DATA;
|
||||
|
||||
#pragma pack()
|
||||
//
|
||||
// ATAPI Command
|
||||
//
|
||||
#define ATAPI_SOFT_RESET_CMD 0x08
|
||||
#define PACKET_CMD 0xA0
|
||||
#define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
|
||||
#define ATAPI_SERVICE_CMD 0xA2
|
||||
|
||||
//
|
||||
// ATAPI Packet Command
|
||||
//
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1;
|
||||
UINT8 reserved_2;
|
||||
UINT8 reserved_3;
|
||||
UINT8 reserved_4;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 reserved_8;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} TEST_UNIT_READY_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1 : 4;
|
||||
UINT8 lun : 4;
|
||||
UINT8 page_code;
|
||||
UINT8 reserved_3;
|
||||
UINT8 allocation_length;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 reserved_8;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} INQUIRY_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1 : 4;
|
||||
UINT8 lun : 4;
|
||||
UINT8 reserved_2;
|
||||
UINT8 reserved_3;
|
||||
UINT8 allocation_length;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 reserved_8;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} REQUEST_SENSE_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1 : 5;
|
||||
UINT8 lun : 3;
|
||||
UINT8 Lba0;
|
||||
UINT8 Lba1;
|
||||
UINT8 Lba2;
|
||||
UINT8 Lba3;
|
||||
UINT8 reserved_6;
|
||||
UINT8 TranLen0;
|
||||
UINT8 TranLen1;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} READ10_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1;
|
||||
UINT8 reserved_2;
|
||||
UINT8 reserved_3;
|
||||
UINT8 reserved_4;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 allocation_length_hi;
|
||||
UINT8 allocation_length_lo;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} READ_FORMAT_CAP_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 peripheral_type;
|
||||
UINT8 RMB;
|
||||
UINT8 version;
|
||||
UINT8 response_data_format;
|
||||
UINT8 addnl_length;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 vendor_info[8];
|
||||
UINT8 product_id[12];
|
||||
UINT8 eeprom_product_code[4];
|
||||
UINT8 firmware_rev_level[4];
|
||||
} USB_INQUIRY_DATA;
|
||||
|
||||
typedef union {
|
||||
UINT16 Data16[6];
|
||||
TEST_UNIT_READY_CMD TestUnitReady;
|
||||
READ10_CMD Read10;
|
||||
REQUEST_SENSE_CMD RequestSence;
|
||||
INQUIRY_CMD Inquiry;
|
||||
READ_FORMAT_CAP_CMD ReadFormatCapacity;
|
||||
} ATAPI_PACKET_COMMAND;
|
||||
|
||||
#pragma pack()
|
||||
//
|
||||
// Packet Command Code
|
||||
//
|
||||
#define TEST_UNIT_READY 0x00
|
||||
#define REQUEST_SENSE 0x03
|
||||
#define INQUIRY 0x12
|
||||
#define READ_FORMAT_CAPACITY 0x23
|
||||
#define READ_CAPACITY 0x25
|
||||
#define READ_10 0x28
|
||||
|
||||
#define DEFAULT_CTL (0x0a) // default content of device control register, disable INT
|
||||
#define DEFAULT_CMD (0xa0)
|
||||
|
||||
#define MAX_ATAPI_BYTE_COUNT (0xfffe)
|
||||
|
||||
//
|
||||
// Sense Key
|
||||
//
|
||||
#define REQUEST_SENSE_ERROR (0x70)
|
||||
#define SK_NO_SENSE (0x0)
|
||||
#define SK_RECOVERY_ERROR (0x1)
|
||||
#define SK_NOT_READY (0x2)
|
||||
#define SK_MEDIUM_ERROR (0x3)
|
||||
#define SK_HARDWARE_ERROR (0x4)
|
||||
#define SK_ILLEGAL_REQUEST (0x5)
|
||||
#define SK_UNIT_ATTENTION (0x6)
|
||||
#define SK_DATA_PROTECT (0x7)
|
||||
#define SK_BLANK_CHECK (0x8)
|
||||
#define SK_VENDOR_SPECIFIC (0x9)
|
||||
#define SK_RESERVED_A (0xA)
|
||||
#define SK_ABORT (0xB)
|
||||
#define SK_RESERVED_C (0xC)
|
||||
#define SK_OVERFLOW (0xD)
|
||||
#define SK_MISCOMPARE (0xE)
|
||||
#define SK_RESERVED_F (0xF)
|
||||
|
||||
//
|
||||
// Additional Sense Codes
|
||||
//
|
||||
#define ASC_NOT_READY (0x04)
|
||||
#define ASC_MEDIA_ERR1 (0x10)
|
||||
#define ASC_MEDIA_ERR2 (0x11)
|
||||
#define ASC_MEDIA_ERR3 (0x14)
|
||||
#define ASC_MEDIA_ERR4 (0x30)
|
||||
#define ASC_MEDIA_UPSIDE_DOWN (0x06)
|
||||
#define ASC_INVALID_CMD (0x20)
|
||||
#define ASC_LBA_OUT_OF_RANGE (0x21)
|
||||
#define ASC_INVALID_FIELD (0x24)
|
||||
#define ASC_WRITE_PROTECTED (0x27)
|
||||
#define ASC_MEDIA_CHANGE (0x28)
|
||||
#define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
|
||||
#define ASC_ILLEGAL_FIELD (0x26)
|
||||
#define ASC_NO_MEDIA (0x3A)
|
||||
#define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
|
||||
|
||||
//
|
||||
// Additional Sense Code Qualifier
|
||||
//
|
||||
#define ASCQ_IN_PROGRESS (0x01)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,31 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
pci.h
|
||||
|
||||
Abstract:
|
||||
Support for PCI standard.
|
||||
|
||||
Revision History
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PCI_H
|
||||
#define _PCI_H
|
||||
|
||||
#include "pci22.h"
|
||||
#include "pci23.h"
|
||||
#include "pci30.h"
|
||||
#include "EfiPci.h"
|
||||
|
||||
#endif
|
||||
555
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h
Normal file
555
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h
Normal file
@@ -0,0 +1,555 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2004 - 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
pci22.h
|
||||
|
||||
Abstract:
|
||||
Support for PCI 2.2 standard.
|
||||
|
||||
Revision History
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PCI22_H
|
||||
#define _PCI22_H
|
||||
|
||||
#define PCI_MAX_SEGMENT 0
|
||||
|
||||
#define PCI_MAX_BUS 255
|
||||
|
||||
#define PCI_MAX_DEVICE 31
|
||||
#define PCI_MAX_FUNC 7
|
||||
|
||||
//
|
||||
// Command
|
||||
//
|
||||
#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
|
||||
|
||||
#pragma pack(push, 1)
|
||||
typedef struct {
|
||||
UINT16 VendorId;
|
||||
UINT16 DeviceId;
|
||||
UINT16 Command;
|
||||
UINT16 Status;
|
||||
UINT8 RevisionID;
|
||||
UINT8 ClassCode[3];
|
||||
UINT8 CacheLineSize;
|
||||
UINT8 LatencyTimer;
|
||||
UINT8 HeaderType;
|
||||
UINT8 BIST;
|
||||
} PCI_DEVICE_INDEPENDENT_REGION;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Bar[6];
|
||||
UINT32 CISPtr;
|
||||
UINT16 SubsystemVendorID;
|
||||
UINT16 SubsystemID;
|
||||
UINT32 ExpansionRomBar;
|
||||
UINT8 CapabilityPtr;
|
||||
UINT8 Reserved1[3];
|
||||
UINT32 Reserved2;
|
||||
UINT8 InterruptLine;
|
||||
UINT8 InterruptPin;
|
||||
UINT8 MinGnt;
|
||||
UINT8 MaxLat;
|
||||
} PCI_DEVICE_HEADER_TYPE_REGION;
|
||||
|
||||
typedef struct {
|
||||
PCI_DEVICE_INDEPENDENT_REGION Hdr;
|
||||
PCI_DEVICE_HEADER_TYPE_REGION Device;
|
||||
} PCI_TYPE00;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Bar[2];
|
||||
UINT8 PrimaryBus;
|
||||
UINT8 SecondaryBus;
|
||||
UINT8 SubordinateBus;
|
||||
UINT8 SecondaryLatencyTimer;
|
||||
UINT8 IoBase;
|
||||
UINT8 IoLimit;
|
||||
UINT16 SecondaryStatus;
|
||||
UINT16 MemoryBase;
|
||||
UINT16 MemoryLimit;
|
||||
UINT16 PrefetchableMemoryBase;
|
||||
UINT16 PrefetchableMemoryLimit;
|
||||
UINT32 PrefetchableBaseUpper32;
|
||||
UINT32 PrefetchableLimitUpper32;
|
||||
UINT16 IoBaseUpper16;
|
||||
UINT16 IoLimitUpper16;
|
||||
UINT8 CapabilityPtr;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 ExpansionRomBAR;
|
||||
UINT8 InterruptLine;
|
||||
UINT8 InterruptPin;
|
||||
UINT16 BridgeControl;
|
||||
} PCI_BRIDGE_CONTROL_REGISTER;
|
||||
|
||||
typedef struct {
|
||||
PCI_DEVICE_INDEPENDENT_REGION Hdr;
|
||||
PCI_BRIDGE_CONTROL_REGISTER Bridge;
|
||||
} PCI_TYPE01;
|
||||
|
||||
typedef union {
|
||||
PCI_TYPE00 Device;
|
||||
PCI_TYPE01 Bridge;
|
||||
} PCI_TYPE_GENERIC;
|
||||
|
||||
typedef struct {
|
||||
UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
|
||||
// Address Register
|
||||
//
|
||||
UINT16 Reserved;
|
||||
UINT16 SecondaryStatus; // Secondary Status
|
||||
UINT8 PciBusNumber; // PCI Bus Number
|
||||
UINT8 CardBusBusNumber; // CardBus Bus Number
|
||||
UINT8 SubordinateBusNumber; // Subordinate Bus Number
|
||||
UINT8 CardBusLatencyTimer; // CardBus Latency Timer
|
||||
UINT32 MemoryBase0; // Memory Base Register 0
|
||||
UINT32 MemoryLimit0; // Memory Limit Register 0
|
||||
UINT32 MemoryBase1;
|
||||
UINT32 MemoryLimit1;
|
||||
UINT32 IoBase0;
|
||||
UINT32 IoLimit0; // I/O Base Register 0
|
||||
UINT32 IoBase1; // I/O Limit Register 0
|
||||
UINT32 IoLimit1;
|
||||
UINT8 InterruptLine; // Interrupt Line
|
||||
UINT8 InterruptPin; // Interrupt Pin
|
||||
UINT16 BridgeControl; // Bridge Control
|
||||
} PCI_CARDBUS_CONTROL_REGISTER;
|
||||
|
||||
//
|
||||
// Definitions of PCI class bytes and manipulation macros.
|
||||
//
|
||||
#define PCI_CLASS_OLD 0x00
|
||||
#define PCI_CLASS_OLD_OTHER 0x00
|
||||
#define PCI_CLASS_OLD_VGA 0x01
|
||||
|
||||
#define PCI_CLASS_MASS_STORAGE 0x01
|
||||
#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
|
||||
#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
|
||||
#define PCI_CLASS_IDE 0x01
|
||||
#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
|
||||
#define PCI_CLASS_MASS_STORAGE_IPI 0x03
|
||||
#define PCI_CLASS_MASS_STORAGE_RAID 0x04
|
||||
#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_NETWORK 0x02
|
||||
#define PCI_CLASS_NETWORK_ETHERNET 0x00
|
||||
#define PCI_CLASS_ETHERNET 0x00 // obsolete
|
||||
#define PCI_CLASS_NETWORK_TOKENRING 0x01
|
||||
#define PCI_CLASS_NETWORK_FDDI 0x02
|
||||
#define PCI_CLASS_NETWORK_ATM 0x03
|
||||
#define PCI_CLASS_NETWORK_ISDN 0x04
|
||||
#define PCI_CLASS_NETWORK_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_DISPLAY 0x03
|
||||
#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
|
||||
#define PCI_CLASS_DISPLAY_VGA 0x00
|
||||
#define PCI_CLASS_VGA 0x00 // obsolete
|
||||
#define PCI_CLASS_DISPLAY_XGA 0x01
|
||||
#define PCI_CLASS_DISPLAY_3D 0x02
|
||||
#define PCI_CLASS_DISPLAY_OTHER 0x80
|
||||
#define PCI_CLASS_DISPLAY_GFX 0x80
|
||||
#define PCI_CLASS_GFX 0x80 // obsolete
|
||||
|
||||
#define PCI_CLASS_BRIDGE 0x06
|
||||
#define PCI_CLASS_BRIDGE_HOST 0x00
|
||||
#define PCI_CLASS_BRIDGE_ISA 0x01
|
||||
#define PCI_CLASS_ISA 0x01 // obsolete
|
||||
#define PCI_CLASS_BRIDGE_EISA 0x02
|
||||
#define PCI_CLASS_BRIDGE_MCA 0x03
|
||||
#define PCI_CLASS_BRIDGE_P2P 0x04
|
||||
#define PCI_CLASS_BRIDGE_PCMCIA 0x05
|
||||
#define PCI_CLASS_BRIDGE_NUBUS 0x06
|
||||
#define PCI_CLASS_BRIDGE_CARDBUS 0x07
|
||||
#define PCI_CLASS_BRIDGE_RACEWAY 0x08
|
||||
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
|
||||
#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
|
||||
|
||||
#define PCI_CLASS_SCC 0x07 // Simple communications controllers
|
||||
#define PCI_SUBCLASS_SERIAL 0x00
|
||||
#define PCI_IF_GENERIC_XT 0x00
|
||||
#define PCI_IF_16450 0x01
|
||||
#define PCI_IF_16550 0x02
|
||||
#define PCI_IF_16650 0x03
|
||||
#define PCI_IF_16750 0x04
|
||||
#define PCI_IF_16850 0x05
|
||||
#define PCI_IF_16950 0x06
|
||||
#define PCI_SUBCLASS_PARALLEL 0x01
|
||||
#define PCI_IF_PARALLEL_PORT 0x00
|
||||
#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
|
||||
#define PCI_IF_ECP_PARALLEL_PORT 0x02
|
||||
#define PCI_IF_1284_CONTROLLER 0x03
|
||||
#define PCI_IF_1284_DEVICE 0xFE
|
||||
#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
|
||||
#define PCI_SUBCLASS_MODEM 0x03
|
||||
#define PCI_IF_GENERIC_MODEM 0x00
|
||||
#define PCI_IF_16450_MODEM 0x01
|
||||
#define PCI_IF_16550_MODEM 0x02
|
||||
#define PCI_IF_16650_MODEM 0x03
|
||||
#define PCI_IF_16750_MODEM 0x04
|
||||
#define PCI_SUBCLASS_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
|
||||
#define PCI_SUBCLASS_PIC 0x00
|
||||
#define PCI_IF_8259_PIC 0x00
|
||||
#define PCI_IF_ISA_PIC 0x01
|
||||
#define PCI_IF_EISA_PIC 0x02
|
||||
#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
|
||||
#define PCI_IF_APIC_CONTROLLER2 0x20
|
||||
#define PCI_SUBCLASS_TIMER 0x02
|
||||
#define PCI_IF_8254_TIMER 0x00
|
||||
#define PCI_IF_ISA_TIMER 0x01
|
||||
#define PCI_EISA_TIMER 0x02
|
||||
#define PCI_SUBCLASS_RTC 0x03
|
||||
#define PCI_IF_GENERIC_RTC 0x00
|
||||
#define PCI_IF_ISA_RTC 0x00
|
||||
#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
|
||||
|
||||
#define PCI_CLASS_INPUT_DEVICE 0x09
|
||||
#define PCI_SUBCLASS_KEYBOARD 0x00
|
||||
#define PCI_SUBCLASS_PEN 0x01
|
||||
#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
|
||||
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
|
||||
#define PCI_SUBCLASS_GAMEPORT 0x04
|
||||
|
||||
#define PCI_CLASS_DOCKING_STATION 0x0A
|
||||
|
||||
#define PCI_CLASS_PROCESSOR 0x0B
|
||||
#define PCI_SUBCLASS_PROC_386 0x00
|
||||
#define PCI_SUBCLASS_PROC_486 0x01
|
||||
#define PCI_SUBCLASS_PROC_PENTIUM 0x02
|
||||
#define PCI_SUBCLASS_PROC_ALPHA 0x10
|
||||
#define PCI_SUBCLASS_PROC_POWERPC 0x20
|
||||
#define PCI_SUBCLASS_PROC_MIPS 0x30
|
||||
#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
|
||||
|
||||
#define PCI_CLASS_SERIAL 0x0C
|
||||
#define PCI_CLASS_SERIAL_FIREWIRE 0x00
|
||||
#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
|
||||
#define PCI_CLASS_SERIAL_SSA 0x02
|
||||
#define PCI_CLASS_SERIAL_USB 0x03
|
||||
#define PCI_IF_EHCI 0x20
|
||||
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
|
||||
#define PCI_CLASS_SERIAL_SMB 0x05
|
||||
|
||||
#define PCI_CLASS_WIRELESS 0x0D
|
||||
#define PCI_SUBCLASS_IRDA 0x00
|
||||
#define PCI_SUBCLASS_IR 0x01
|
||||
#define PCI_SUBCLASS_RF 0x02
|
||||
|
||||
#define PCI_CLASS_INTELLIGENT_IO 0x0E
|
||||
|
||||
#define PCI_CLASS_SATELLITE 0x0F
|
||||
#define PCI_SUBCLASS_TV 0x01
|
||||
#define PCI_SUBCLASS_AUDIO 0x02
|
||||
#define PCI_SUBCLASS_VOICE 0x03
|
||||
#define PCI_SUBCLASS_DATA 0x04
|
||||
|
||||
#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
|
||||
#define PCI_SUBCLASS_NET_COMPUT 0x00
|
||||
#define PCI_SUBCLASS_ENTERTAINMENT 0x10
|
||||
|
||||
#define PCI_CLASS_DPIO 0x11
|
||||
|
||||
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
|
||||
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
|
||||
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
|
||||
|
||||
#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
|
||||
#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
|
||||
#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
|
||||
#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
|
||||
#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
|
||||
#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
|
||||
#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
|
||||
#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
|
||||
#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
|
||||
#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
|
||||
#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
|
||||
#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
|
||||
#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
|
||||
#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
|
||||
#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
|
||||
|
||||
#define HEADER_TYPE_DEVICE 0x00
|
||||
#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
|
||||
#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
|
||||
|
||||
#define HEADER_TYPE_MULTI_FUNCTION 0x80
|
||||
#define HEADER_LAYOUT_CODE 0x7f
|
||||
|
||||
#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
|
||||
#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
|
||||
#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
|
||||
|
||||
#define PCI_DEVICE_ROMBAR 0x30
|
||||
#define PCI_BRIDGE_ROMBAR 0x38
|
||||
|
||||
#define PCI_MAX_BAR 0x0006
|
||||
#define PCI_MAX_CONFIG_OFFSET 0x0100
|
||||
|
||||
#define PCI_VENDOR_ID_OFFSET 0x00
|
||||
#define PCI_DEVICE_ID_OFFSET 0x02
|
||||
#define PCI_COMMAND_OFFSET 0x04
|
||||
#define PCI_PRIMARY_STATUS_OFFSET 0x06
|
||||
#define PCI_REVISION_ID_OFFSET 0x08
|
||||
#define PCI_CLASSCODE_OFFSET 0x09
|
||||
#define PCI_SUBCLASSCODE_OFFSET 0x0A
|
||||
#define PCI_CACHELINE_SIZE_OFFSET 0x0C
|
||||
#define PCI_LATENCY_TIMER_OFFSET 0x0D
|
||||
#define PCI_HEADER_TYPE_OFFSET 0x0E
|
||||
#define PCI_BIST_OFFSET 0x0F
|
||||
#define PCI_BASE_ADDRESSREG_OFFSET 0x10
|
||||
#define PCI_CARDBUS_CIS_OFFSET 0x28
|
||||
#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
|
||||
#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
|
||||
#define PCI_SID_OFFSET 0x2E // SubSystem ID
|
||||
#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
|
||||
#define PCI_EXPANSION_ROM_BASE 0x30
|
||||
#define PCI_CAPBILITY_POINTER_OFFSET 0x34
|
||||
#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
|
||||
#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
|
||||
#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
|
||||
#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
|
||||
|
||||
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
|
||||
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
|
||||
|
||||
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
|
||||
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
|
||||
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
|
||||
|
||||
//
|
||||
// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
|
||||
//
|
||||
#define PCI_INT_LINE_UNKNOWN 0xFF
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT32 Reg : 8;
|
||||
UINT32 Func : 3;
|
||||
UINT32 Dev : 5;
|
||||
UINT32 Bus : 8;
|
||||
UINT32 Reserved : 7;
|
||||
UINT32 Enable : 1;
|
||||
} PCI_CONFIG_ACCESS_CF8;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
|
||||
#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
|
||||
#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
|
||||
#define PCI_CODE_TYPE_EFI_IMAGE 0x03
|
||||
#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
|
||||
|
||||
#define EFI_PCI_COMMAND_IO_SPACE 0x0001
|
||||
#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
|
||||
#define EFI_PCI_COMMAND_BUS_MASTER 0x0004
|
||||
#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
|
||||
#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
|
||||
#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
|
||||
#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
|
||||
#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
|
||||
#define EFI_PCI_COMMAND_SERR 0x0100
|
||||
#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
|
||||
|
||||
#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
|
||||
#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
|
||||
#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
|
||||
#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
|
||||
#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
|
||||
#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
|
||||
#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
|
||||
#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
|
||||
#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
|
||||
#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
|
||||
#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
|
||||
#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
|
||||
|
||||
//
|
||||
// Following are the PCI-CARDBUS bridge control bit
|
||||
//
|
||||
#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
|
||||
#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
|
||||
#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
|
||||
#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
|
||||
|
||||
//
|
||||
// Following are the PCI status control bit
|
||||
//
|
||||
#define EFI_PCI_STATUS_CAPABILITY 0x0010
|
||||
#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
|
||||
#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
|
||||
#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
|
||||
|
||||
#define EFI_PCI_CAPABILITY_PTR 0x34
|
||||
#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
|
||||
|
||||
#pragma pack(1)
|
||||
typedef struct {
|
||||
UINT16 Signature; // 0xaa55
|
||||
UINT8 Reserved[0x16];
|
||||
UINT16 PcirOffset;
|
||||
} PCI_EXPANSION_ROM_HEADER;
|
||||
|
||||
typedef struct {
|
||||
UINT16 Signature; // 0xaa55
|
||||
UINT8 Size512;
|
||||
UINT8 InitEntryPoint[3];
|
||||
UINT8 Reserved[0x12];
|
||||
UINT16 PcirOffset;
|
||||
} EFI_LEGACY_EXPANSION_ROM_HEADER;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Signature; // "PCIR"
|
||||
UINT16 VendorId;
|
||||
UINT16 DeviceId;
|
||||
UINT16 Reserved0;
|
||||
UINT16 Length;
|
||||
UINT8 Revision;
|
||||
UINT8 ClassCode[3];
|
||||
UINT16 ImageLength;
|
||||
UINT16 CodeRevision;
|
||||
UINT8 CodeType;
|
||||
UINT8 Indicator;
|
||||
UINT16 Reserved1;
|
||||
} PCI_DATA_STRUCTURE;
|
||||
|
||||
//
|
||||
// PCI Capability List IDs and records
|
||||
//
|
||||
#define EFI_PCI_CAPABILITY_ID_PMI 0x01
|
||||
#define EFI_PCI_CAPABILITY_ID_AGP 0x02
|
||||
#define EFI_PCI_CAPABILITY_ID_VPD 0x03
|
||||
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
|
||||
#define EFI_PCI_CAPABILITY_ID_MSI 0x05
|
||||
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
|
||||
#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
|
||||
|
||||
typedef struct {
|
||||
UINT8 CapabilityID;
|
||||
UINT8 NextItemPtr;
|
||||
} EFI_PCI_CAPABILITY_HDR;
|
||||
|
||||
//
|
||||
// Capability EFI_PCI_CAPABILITY_ID_PMI
|
||||
//
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
UINT16 PMC;
|
||||
UINT16 PMCSR;
|
||||
UINT8 BridgeExtention;
|
||||
UINT8 Data;
|
||||
} EFI_PCI_CAPABILITY_PMI;
|
||||
|
||||
//
|
||||
// Capability EFI_PCI_CAPABILITY_ID_AGP
|
||||
//
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
UINT8 Rev;
|
||||
UINT8 Reserved;
|
||||
UINT32 Status;
|
||||
UINT32 Command;
|
||||
} EFI_PCI_CAPABILITY_AGP;
|
||||
|
||||
//
|
||||
// Capability EFI_PCI_CAPABILITY_ID_VPD
|
||||
//
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
UINT16 AddrReg;
|
||||
UINT32 DataReg;
|
||||
} EFI_PCI_CAPABILITY_VPD;
|
||||
|
||||
//
|
||||
// Capability EFI_PCI_CAPABILITY_ID_SLOTID
|
||||
//
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
UINT8 ExpnsSlotReg;
|
||||
UINT8 ChassisNo;
|
||||
} EFI_PCI_CAPABILITY_SLOTID;
|
||||
|
||||
//
|
||||
// Capability EFI_PCI_CAPABILITY_ID_MSI
|
||||
//
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
UINT16 MsgCtrlReg;
|
||||
UINT32 MsgAddrReg;
|
||||
UINT16 MsgDataReg;
|
||||
} EFI_PCI_CAPABILITY_MSI32;
|
||||
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
UINT16 MsgCtrlReg;
|
||||
UINT32 MsgAddrRegLsdw;
|
||||
UINT32 MsgAddrRegMsdw;
|
||||
UINT16 MsgDataReg;
|
||||
} EFI_PCI_CAPABILITY_MSI64;
|
||||
|
||||
//
|
||||
// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
|
||||
//
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
//
|
||||
// not finished - fields need to go here
|
||||
//
|
||||
} EFI_PCI_CAPABILITY_HOTPLUG;
|
||||
|
||||
//
|
||||
// Capability EFI_PCI_CAPABILITY_ID_PCIX
|
||||
//
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
UINT16 CommandReg;
|
||||
UINT32 StatusReg;
|
||||
} EFI_PCI_CAPABILITY_PCIX;
|
||||
|
||||
typedef struct {
|
||||
EFI_PCI_CAPABILITY_HDR Hdr;
|
||||
UINT16 SecStatusReg;
|
||||
UINT32 StatusReg;
|
||||
UINT32 SplitTransCtrlRegUp;
|
||||
UINT32 SplitTransCtrlRegDn;
|
||||
} EFI_PCI_CAPABILITY_PCIX_BRDG;
|
||||
|
||||
#define DEVICE_ID_NOCARE 0xFFFF
|
||||
|
||||
#define PCI_ACPI_UNUSED 0
|
||||
#define PCI_BAR_NOCHANGE 0
|
||||
#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFF
|
||||
#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFE
|
||||
#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFD
|
||||
#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFC
|
||||
|
||||
#define PCI_BAR_IDX0 0x00
|
||||
#define PCI_BAR_IDX1 0x01
|
||||
#define PCI_BAR_IDX2 0x02
|
||||
#define PCI_BAR_IDX3 0x03
|
||||
#define PCI_BAR_IDX4 0x04
|
||||
#define PCI_BAR_IDX5 0x05
|
||||
#define PCI_BAR_ALL 0xFF
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
//
|
||||
// NOTE: The following header files are included here for
|
||||
// compatibility consideration.
|
||||
//
|
||||
#include "EfiPci.h"
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,31 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2006 - 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
pci23.h
|
||||
|
||||
Abstract:
|
||||
Support for PCI 2.3 standard.
|
||||
|
||||
Revision History
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PCI23_H
|
||||
#define _PCI23_H
|
||||
|
||||
#include "pci22.h"
|
||||
|
||||
#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
|
||||
#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2006 - 2007, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
pci30.h
|
||||
|
||||
Abstract:
|
||||
Support for PCI 3.0 standard.
|
||||
|
||||
Revision History
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PCI30_H
|
||||
#define _PCI30_H
|
||||
|
||||
#include "pci23.h"
|
||||
|
||||
#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
|
||||
#define PCI_CLASS_MASS_STORAGE_AHCI PCI_CLASS_MASS_STORAGE_SATADPA
|
||||
|
||||
#pragma pack(push, 1)
|
||||
|
||||
typedef struct {
|
||||
UINT32 Signature; // "PCIR"
|
||||
UINT16 VendorId;
|
||||
UINT16 DeviceId;
|
||||
UINT16 DeviceListOffset;
|
||||
UINT16 Length;
|
||||
UINT8 Revision;
|
||||
UINT8 ClassCode[3];
|
||||
UINT16 ImageLength;
|
||||
UINT16 CodeRevision;
|
||||
UINT8 CodeType;
|
||||
UINT8 Indicator;
|
||||
UINT16 MaxRuntimeImageLength;
|
||||
UINT16 ConfigUtilityCodeHeaderOffset;
|
||||
UINT16 DMTFCLPEntryPointOffset;
|
||||
} PCI_3_0_DATA_STRUCTURE;
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
#endif
|
||||
292
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h
Normal file
292
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h
Normal file
@@ -0,0 +1,292 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2004 - 2006, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
scsi.h
|
||||
|
||||
Abstract:
|
||||
support for SCSI standard
|
||||
|
||||
Revision History
|
||||
--*/
|
||||
|
||||
#ifndef _SCSI_H
|
||||
#define _SCSI_H
|
||||
|
||||
//
|
||||
// SCSI command OP Code
|
||||
//
|
||||
//
|
||||
// Commands for all device types
|
||||
//
|
||||
#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
|
||||
#define EFI_SCSI_OP_COMPARE 0x39
|
||||
#define EFI_SCSI_OP_COPY 0x18
|
||||
#define EFI_SCSI_OP_COPY_VERIFY 0x3a
|
||||
#define EFI_SCSI_OP_INQUIRY 0x12
|
||||
#define EFI_SCSI_OP_LOG_SELECT 0x4c
|
||||
#define EFI_SCSI_OP_LOG_SENSE 0x4d
|
||||
#define EFI_SCSI_OP_MODE_SEL6 0x15
|
||||
#define EFI_SCSI_OP_MODE_SEL10 0x55
|
||||
#define EFI_SCSI_OP_MODE_SEN6 0x1a
|
||||
#define EFI_SCSI_OP_MODE_SEN10 0x5a
|
||||
#define EFI_SCSI_OP_READ_BUFFER 0x3c
|
||||
#define EFI_SCSI_OP_REQUEST_SENSE 0x03
|
||||
#define EFI_SCSI_OP_SEND_DIAG 0x1d
|
||||
#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
|
||||
#define EFI_SCSI_OP_WRITE_BUFF 0x3b
|
||||
|
||||
//
|
||||
// Commands unique to Direct Access Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_COMPARE 0x39
|
||||
#define EFI_SCSI_OP_FORMAT 0x04
|
||||
#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
|
||||
#define EFI_SCSI_OP_PREFETCH 0x34
|
||||
#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e
|
||||
#define EFI_SCSI_OP_READ6 0x08
|
||||
#define EFI_SCSI_OP_READ10 0x28
|
||||
#define EFI_SCSI_OP_READ_CAPACITY 0x25
|
||||
#define EFI_SCSI_OP_READ_DEFECT 0x37
|
||||
#define EFI_SCSI_OP_READ_LONG 0x3e
|
||||
#define EFI_SCSI_OP_REASSIGN_BLK 0x07
|
||||
#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
|
||||
#define EFI_SCSI_OP_RELEASE 0x17
|
||||
#define EFI_SCSI_OP_REZERO 0x01
|
||||
#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
|
||||
#define EFI_SCSI_OP_SEARCH_DATA_H 0x30
|
||||
#define EFI_SCSI_OP_SEARCH_DATA_L 0x32
|
||||
#define EFI_SCSI_OP_SEEK6 0x0b
|
||||
#define EFI_SCSI_OP_SEEK10 0x2b
|
||||
#define EFI_SCSI_OP_SEND_DIAG 0x1d
|
||||
#define EFI_SCSI_OP_SET_LIMIT 0x33
|
||||
#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
|
||||
#define EFI_SCSI_OP_SYNC_CACHE 0x35
|
||||
#define EFI_SCSI_OP_VERIFY 0x2f
|
||||
#define EFI_SCSI_OP_WRITE6 0x0a
|
||||
#define EFI_SCSI_OP_WRITE10 0x2a
|
||||
#define EFI_SCSI_OP_WRITE_VERIFY 0x2e
|
||||
#define EFI_SCSI_OP_WRITE_LONG 0x3f
|
||||
#define EFI_SCSI_OP_WRITE_SAME 0x41
|
||||
|
||||
//
|
||||
// Commands unique to Sequential Access Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_ERASE 0x19
|
||||
#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b
|
||||
#define EFI_SCSI_OP_LOCATE 0x2b
|
||||
#define EFI_SCSI_OP_READ_BLOCK_LIMIT 0x05
|
||||
#define EFI_SCSI_OP_READ_POS 0x34
|
||||
#define EFI_SCSI_OP_READ_REVERSE 0x0f
|
||||
#define EFI_SCSI_OP_RECOVER_BUF_DATA 0x14
|
||||
#define EFI_SCSI_OP_RESERVE_UNIT 0x16
|
||||
#define EFI_SCSI_OP_REWIND 0x01
|
||||
#define EFI_SCSI_OP_SPACE 0x11
|
||||
#define EFI_SCSI_OP_VERIFY_TAPE 0x13
|
||||
#define EFI_SCSI_OP_WRITE_FILEMARK 0x10
|
||||
|
||||
//
|
||||
// Commands unique to Printer Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_PRINT 0x0a
|
||||
#define EFI_SCSI_OP_SLEW_PRINT 0x0b
|
||||
#define EFI_SCSI_OP_STOP_PRINT 0x1b
|
||||
#define EFI_SCSI_OP_SYNC_BUFF 0x10
|
||||
|
||||
//
|
||||
// Commands unique to Processor Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_RECEIVE 0x08
|
||||
#define EFI_SCSI_OP_SEND 0x0a
|
||||
|
||||
//
|
||||
// Commands unique to Write-Once Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_MEDIUM_SCAN 0x38
|
||||
#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31
|
||||
#define EFI_SCSI_OP_SEARCH_DAT_E12 0xb1
|
||||
#define EFI_SCSI_OP_SEARCH_DAT_H10 0x30
|
||||
#define EFI_SCSI_OP_SEARCH_DAT_H12 0xb0
|
||||
#define EFI_SCSI_OP_SEARCH_DAT_L10 0x32
|
||||
#define EFI_SCSI_OP_SEARCH_DAT_L12 0xb2
|
||||
#define EFI_SCSI_OP_SET_LIMIT10 0x33
|
||||
#define EFI_SCSI_OP_SET_LIMIT12 0xb3
|
||||
#define EFI_SCSI_OP_VERIFY10 0x2f
|
||||
#define EFI_SCSI_OP_VERIFY12 0xaf
|
||||
#define EFI_SCSI_OP_WRITE12 0xaa
|
||||
#define EFI_SCSI_OP_WRITE_VERIFY10 0x2e
|
||||
#define EFI_SCSI_OP_WRITE_VERIFY12 0xae
|
||||
|
||||
//
|
||||
// Commands unique to CD-ROM Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_PLAY_AUD_10 0x45
|
||||
#define EFI_SCSI_OP_PLAY_AUD_12 0xa5
|
||||
#define EFI_SCSI_OP_PLAY_AUD_MSF 0x47
|
||||
#define EFI_SCSI_OP_PLAY_AUD_TKIN 0x48
|
||||
#define EFI_SCSI_OP_PLAY_TK_REL10 0x49
|
||||
#define EFI_SCSI_OP_PLAY_TK_REL12 0xa9
|
||||
#define EFI_SCSI_OP_READ_CD_CAPACITY 0x25
|
||||
#define EFI_SCSI_OP_READ_HEADER 0x44
|
||||
#define EFI_SCSI_OP_READ_SUB_CHANNEL 0x42
|
||||
#define EFI_SCSI_OP_READ_TOC 0x43
|
||||
|
||||
//
|
||||
// Commands unique to Scanner Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
|
||||
#define EFI_SCSI_OP_GET_WINDOW 0x25
|
||||
#define EFI_SCSI_OP_OBJECT_POS 0x31
|
||||
#define EFI_SCSI_OP_SCAN 0x1b
|
||||
#define EFI_SCSI_OP_SET_WINDOW 0x24
|
||||
|
||||
//
|
||||
// Commands unique to Optical Memory Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d
|
||||
|
||||
//
|
||||
// Commands unique to Medium Changer Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
|
||||
#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
|
||||
#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b
|
||||
#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5
|
||||
#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
|
||||
|
||||
//
|
||||
// Commands unique to Communition Devices
|
||||
//
|
||||
#define EFI_SCSI_OP_GET_MESSAGE6 0x08
|
||||
#define EFI_SCSI_OP_GET_MESSAGE10 0x28
|
||||
#define EFI_SCSI_OP_GET_MESSAGE12 0xa8
|
||||
#define EFI_SCSI_OP_SEND_MESSAGE6 0x0a
|
||||
#define EFI_SCSI_OP_SEND_MESSAGE10 0x2a
|
||||
#define EFI_SCSI_OP_SEND_MESSAGE12 0xaa
|
||||
|
||||
//
|
||||
// SCSI Data Transfer Direction
|
||||
//
|
||||
#define EFI_SCSI_DATA_IN 0
|
||||
#define EFI_SCSI_DATA_OUT 1
|
||||
|
||||
//
|
||||
// Peripheral Device Type Definitions
|
||||
//
|
||||
#define EFI_SCSI_TYPE_DISK 0x00 // Disk device
|
||||
#define EFI_SCSI_TYPE_TAPE 0x01 // Tape device
|
||||
#define EFI_SCSI_TYPE_PRINTER 0x02 // Printer
|
||||
#define EFI_SCSI_TYPE_PROCESSOR 0x03 // Processor
|
||||
#define EFI_SCSI_TYPE_WORM 0x04 // Write-once read-multiple
|
||||
#define EFI_SCSI_TYPE_CDROM 0x05 // CD-ROM device
|
||||
#define EFI_SCSI_TYPE_SCANNER 0x06 // Scanner device
|
||||
#define EFI_SCSI_TYPE_OPTICAL 0x07 // Optical memory device
|
||||
#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 // Medium Changer device
|
||||
#define EFI_SCSI_TYPE_COMMUNICATION 0x09 // Communications device
|
||||
#define EFI_SCSI_TYPE_RESERVED_LOW 0x0A // Reserved (low)
|
||||
#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1E // Reserved (high)
|
||||
#define EFI_SCSI_TYPE_UNKNOWN 0x1F // Unknown or no device type
|
||||
#pragma pack(1)
|
||||
//
|
||||
// Data structures for scsi command use
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Peripheral_Type : 5;
|
||||
UINT8 Peripheral_Qualifier : 3;
|
||||
UINT8 DeviceType_Modifier : 7;
|
||||
UINT8 RMB : 1;
|
||||
UINT8 Version;
|
||||
UINT8 Response_Data_Format;
|
||||
UINT8 Addnl_Length;
|
||||
UINT8 Reserved_5_95[95 - 5 + 1];
|
||||
} EFI_SCSI_INQUIRY_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Error_Code : 7;
|
||||
UINT8 Valid : 1;
|
||||
UINT8 Segment_Number;
|
||||
UINT8 Sense_Key : 4;
|
||||
UINT8 Reserved_21 : 1;
|
||||
UINT8 ILI : 1;
|
||||
UINT8 Reserved_22 : 2;
|
||||
UINT8 Information_3_6[4];
|
||||
UINT8 Addnl_Sense_Length; // n - 7
|
||||
UINT8 Vendor_Specific_8_11[4];
|
||||
UINT8 Addnl_Sense_Code; // mandatory
|
||||
UINT8 Addnl_Sense_Code_Qualifier; // mandatory
|
||||
UINT8 Field_Replaceable_Unit_Code; // optional
|
||||
UINT8 Reserved_15_17[3];
|
||||
} EFI_SCSI_SENSE_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 LastLba3;
|
||||
UINT8 LastLba2;
|
||||
UINT8 LastLba1;
|
||||
UINT8 LastLba0;
|
||||
UINT8 BlockSize3;
|
||||
UINT8 BlockSize2;
|
||||
UINT8 BlockSize1;
|
||||
UINT8 BlockSize0;
|
||||
} EFI_SCSI_DISK_CAPACITY_DATA;
|
||||
|
||||
#pragma pack()
|
||||
//
|
||||
// Sense Key
|
||||
//
|
||||
#define EFI_SCSI_REQUEST_SENSE_ERROR (0x70)
|
||||
#define EFI_SCSI_SK_NO_SENSE (0x0)
|
||||
#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
|
||||
#define EFI_SCSI_SK_NOT_READY (0x2)
|
||||
#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)
|
||||
#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)
|
||||
#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)
|
||||
#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)
|
||||
#define EFI_SCSI_SK_DATA_PROTECT (0x7)
|
||||
#define EFI_SCSI_SK_BLANK_CHECK (0x8)
|
||||
#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)
|
||||
#define EFI_SCSI_SK_RESERVED_A (0xA)
|
||||
#define EFI_SCSI_SK_ABORT (0xB)
|
||||
#define EFI_SCSI_SK_RESERVED_C (0xC)
|
||||
#define EFI_SCSI_SK_OVERFLOW (0xD)
|
||||
#define EFI_SCSI_SK_MISCOMPARE (0xE)
|
||||
#define EFI_SCSI_SK_RESERVED_F (0xF)
|
||||
|
||||
//
|
||||
// Additional Sense Codes
|
||||
//
|
||||
#define EFI_SCSI_ASC_NOT_READY (0x04)
|
||||
#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)
|
||||
#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)
|
||||
#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14)
|
||||
#define EFI_SCSI_ASC_MEDIA_ERR4 (0x30)
|
||||
#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN (0x06)
|
||||
#define EFI_SCSI_ASC_INVALID_CMD (0x20)
|
||||
#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE (0x21)
|
||||
#define EFI_SCSI_ASC_INVALID_FIELD (0x24)
|
||||
#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27)
|
||||
#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28)
|
||||
#define EFI_SCSI_ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
|
||||
#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26)
|
||||
#define EFI_SCSI_ASC_NO_MEDIA (0x3A)
|
||||
#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
|
||||
|
||||
//
|
||||
// Additional Sense Code Qualifier
|
||||
//
|
||||
#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
|
||||
|
||||
//
|
||||
// Max bytes needed to represent ID of a SCSI device
|
||||
//
|
||||
#define EFI_SCSI_TARGET_MAX_BYTES (0x10)
|
||||
|
||||
#endif
|
||||
293
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h
Normal file
293
EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h
Normal file
@@ -0,0 +1,293 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2004 - 2006, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
usb.h
|
||||
|
||||
Abstract:
|
||||
Support for USB 1.1 standard.
|
||||
|
||||
|
||||
|
||||
|
||||
Revision History
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _USB_H
|
||||
#define _USB_H
|
||||
//
|
||||
// USB Descriptor types
|
||||
//
|
||||
#define USB_DT_DEVICE 0x01
|
||||
#define USB_DT_CONFIG 0x02
|
||||
#define USB_DT_STRING 0x03
|
||||
#define USB_DT_INTERFACE 0x04
|
||||
#define USB_DT_ENDPOINT 0x05
|
||||
#define USB_DT_HUB 0x29
|
||||
#define USB_DT_HID 0x21
|
||||
|
||||
//
|
||||
// USB request type
|
||||
//
|
||||
#define USB_TYPE_STANDARD (0x00 << 5)
|
||||
#define USB_TYPE_CLASS (0x01 << 5)
|
||||
#define USB_TYPE_VENDOR (0x02 << 5)
|
||||
#define USB_TYPE_RESERVED (0x03 << 5)
|
||||
|
||||
//
|
||||
// USB request targer device
|
||||
//
|
||||
#define USB_RECIP_DEVICE 0x00
|
||||
#define USB_RECIP_INTERFACE 0x01
|
||||
#define USB_RECIP_ENDPOINT 0x02
|
||||
#define USB_RECIP_OTHER 0x03
|
||||
|
||||
//
|
||||
// Request target types.
|
||||
//
|
||||
#define USB_RT_DEVICE 0x00
|
||||
#define USB_RT_INTERFACE 0x01
|
||||
#define USB_RT_ENDPOINT 0x02
|
||||
#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
|
||||
#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
|
||||
|
||||
//
|
||||
// USB Transfer Results
|
||||
//
|
||||
#define EFI_USB_NOERROR 0x00
|
||||
#define EFI_USB_ERR_NOTEXECUTE 0x01
|
||||
#define EFI_USB_ERR_STALL 0x02
|
||||
#define EFI_USB_ERR_BUFFER 0x04
|
||||
#define EFI_USB_ERR_BABBLE 0x08
|
||||
#define EFI_USB_ERR_NAK 0x10
|
||||
#define EFI_USB_ERR_CRC 0x20
|
||||
#define EFI_USB_ERR_TIMEOUT 0x40
|
||||
#define EFI_USB_ERR_BITSTUFF 0x80
|
||||
#define EFI_USB_ERR_SYSTEM 0x100
|
||||
|
||||
//
|
||||
//Use 200 ms to increase the error handling response time
|
||||
//
|
||||
#define EFI_USB_INTERRUPT_DELAY 2000000
|
||||
|
||||
//
|
||||
// USB transation direction
|
||||
//
|
||||
typedef enum {
|
||||
EfiUsbDataIn,
|
||||
EfiUsbDataOut,
|
||||
EfiUsbNoData
|
||||
} EFI_USB_DATA_DIRECTION;
|
||||
|
||||
//
|
||||
// Usb Data recipient type
|
||||
//
|
||||
typedef enum {
|
||||
EfiUsbDevice,
|
||||
EfiUsbInterface,
|
||||
EfiUsbEndpoint
|
||||
} EFI_USB_RECIPIENT;
|
||||
|
||||
typedef enum {
|
||||
EfiUsbEndpointHalt,
|
||||
EfiUsbDeviceRemoteWakeup
|
||||
} EFI_USB_STANDARD_FEATURE_SELECTOR;
|
||||
|
||||
#pragma pack(1)
|
||||
//
|
||||
// Usb device request structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 RequestType;
|
||||
UINT8 Request;
|
||||
UINT16 Value;
|
||||
UINT16 Index;
|
||||
UINT16 Length;
|
||||
} EFI_USB_DEVICE_REQUEST;
|
||||
|
||||
//
|
||||
// Standard USB request
|
||||
//
|
||||
#define USB_DEV_GET_STATUS 0x00
|
||||
|
||||
#define USB_DEV_CLEAR_FEATURE 0x01
|
||||
|
||||
#define USB_DEV_SET_FEATURE 0x03
|
||||
|
||||
#define USB_DEV_SET_ADDRESS 0x05
|
||||
#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00
|
||||
|
||||
#define USB_DEV_GET_DESCRIPTOR 0x06
|
||||
#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80
|
||||
|
||||
#define USB_DEV_SET_DESCRIPTOR 0x07
|
||||
#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00
|
||||
|
||||
#define USB_DEV_GET_CONFIGURATION 0x08
|
||||
#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80
|
||||
|
||||
#define USB_DEV_SET_CONFIGURATION 0x09
|
||||
#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00
|
||||
|
||||
#define USB_DEV_GET_INTERFACE 0x0A
|
||||
#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81
|
||||
|
||||
#define USB_DEV_SET_INTERFACE 0x0B
|
||||
#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01
|
||||
|
||||
#define USB_DEV_SYNCH_FRAME 0x0C
|
||||
#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82
|
||||
|
||||
//
|
||||
// Device descriptor. refer USB1.1
|
||||
//
|
||||
typedef struct usb_device_descriptor {
|
||||
UINT8 Length;
|
||||
UINT8 DescriptorType;
|
||||
UINT16 BcdUSB;
|
||||
UINT8 DeviceClass;
|
||||
UINT8 DeviceSubClass;
|
||||
UINT8 DeviceProtocol;
|
||||
UINT8 MaxPacketSize0;
|
||||
UINT16 IdVendor;
|
||||
UINT16 IdProduct;
|
||||
UINT16 BcdDevice;
|
||||
UINT8 StrManufacturer;
|
||||
UINT8 StrProduct;
|
||||
UINT8 StrSerialNumber;
|
||||
UINT8 NumConfigurations;
|
||||
} EFI_USB_DEVICE_DESCRIPTOR;
|
||||
|
||||
//
|
||||
// Endpoint descriptor
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Length;
|
||||
UINT8 DescriptorType;
|
||||
UINT8 EndpointAddress;
|
||||
UINT8 Attributes;
|
||||
UINT16 MaxPacketSize;
|
||||
UINT8 Interval;
|
||||
} EFI_USB_ENDPOINT_DESCRIPTOR;
|
||||
|
||||
//
|
||||
// Interface descriptor
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Length;
|
||||
UINT8 DescriptorType;
|
||||
UINT8 InterfaceNumber;
|
||||
UINT8 AlternateSetting;
|
||||
UINT8 NumEndpoints;
|
||||
UINT8 InterfaceClass;
|
||||
UINT8 InterfaceSubClass;
|
||||
UINT8 InterfaceProtocol;
|
||||
UINT8 Interface;
|
||||
} EFI_USB_INTERFACE_DESCRIPTOR;
|
||||
|
||||
//
|
||||
// USB alternate setting
|
||||
//
|
||||
typedef struct {
|
||||
EFI_USB_INTERFACE_DESCRIPTOR *Interface;
|
||||
} USB_ALT_SETTING;
|
||||
|
||||
//
|
||||
// Configuration descriptor
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Length;
|
||||
UINT8 DescriptorType;
|
||||
UINT16 TotalLength;
|
||||
UINT8 NumInterfaces;
|
||||
UINT8 ConfigurationValue;
|
||||
UINT8 Configuration;
|
||||
UINT8 Attributes;
|
||||
UINT8 MaxPower;
|
||||
} EFI_USB_CONFIG_DESCRIPTOR;
|
||||
|
||||
//
|
||||
// Supported String Languages
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Length;
|
||||
UINT8 DescriptorType;
|
||||
UINT16 SupportedLanID[1];
|
||||
} EFI_USB_SUPPORTED_LANGUAGES;
|
||||
|
||||
//
|
||||
// String descriptor
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Length;
|
||||
UINT8 DescriptorType;
|
||||
CHAR16 String[1];
|
||||
} EFI_USB_STRING_DESCRIPTOR;
|
||||
|
||||
//
|
||||
// Hub descriptor
|
||||
//
|
||||
#define MAXBYTES 8
|
||||
typedef struct {
|
||||
UINT8 Length;
|
||||
UINT8 DescriptorType;
|
||||
UINT8 NbrPorts;
|
||||
UINT8 HubCharacteristics[2];
|
||||
UINT8 PwrOn2PwrGood;
|
||||
UINT8 HubContrCurrent;
|
||||
UINT8 Filler[MAXBYTES];
|
||||
} EFI_USB_HUB_DESCRIPTOR;
|
||||
|
||||
typedef struct {
|
||||
UINT16 PortStatus;
|
||||
UINT16 PortChangeStatus;
|
||||
} EFI_USB_PORT_STATUS;
|
||||
|
||||
//
|
||||
// Constant value for Port Status & Port Change Status
|
||||
//
|
||||
#define USB_PORT_STAT_CONNECTION 0x0001
|
||||
#define USB_PORT_STAT_ENABLE 0x0002
|
||||
#define USB_PORT_STAT_SUSPEND 0x0004
|
||||
#define USB_PORT_STAT_OVERCURRENT 0x0008
|
||||
#define USB_PORT_STAT_RESET 0x0010
|
||||
#define USB_PORT_STAT_POWER 0x0100
|
||||
#define USB_PORT_STAT_LOW_SPEED 0x0200
|
||||
#define USB_PORT_STAT_HIGH_SPEED 0x0400
|
||||
#define USB_PORT_STAT_OWNER 0x0800
|
||||
|
||||
#define USB_PORT_STAT_C_CONNECTION 0x0001
|
||||
#define USB_PORT_STAT_C_ENABLE 0x0002
|
||||
#define USB_PORT_STAT_C_SUSPEND 0x0004
|
||||
#define USB_PORT_STAT_C_OVERCURRENT 0x0008
|
||||
#define USB_PORT_STAT_C_RESET 0x0010
|
||||
|
||||
//
|
||||
// Used for set/clear port feature request
|
||||
//
|
||||
typedef enum {
|
||||
EfiUsbPortEnable = 1,
|
||||
EfiUsbPortSuspend = 2,
|
||||
EfiUsbPortReset = 4,
|
||||
EfiUsbPortPower = 8,
|
||||
EfiUsbPortOwner = 13,
|
||||
EfiUsbPortConnectChange = 16,
|
||||
EfiUsbPortEnableChange = 17,
|
||||
EfiUsbPortSuspendChange = 18,
|
||||
EfiUsbPortOverCurrentChange = 19,
|
||||
EfiUsbPortResetChange = 20
|
||||
} EFI_USB_PORT_FEATURE;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user