DynamicTablesPkg: Add ETE device to CPU node in AML
The Coresight Embedded Trace Extension (ETE) feature can be detected by the platform firmware by examining the debug feature register ID_AA64DFR0_EL1.TraceVer field. The platform configuration manager can then describe the ETE by creating CM_ARM_ET_INFO object(s) and referencing these in CM_ARM_GICC_INFO.EtToken. The 'Table 3: Compatible IDs for architected CoreSight components' in the 'ACPI for CoreSight 1.2 Platform Design Document' specifies the HID value for Coresight ETE and CoreSight Embedded Trace Macrocell (ETM) v4.x as ARMH C500. Therefore, update the SsdtCpuTopologyGenerator to add an ETE device to the CPU node in the AML CPU hierarchy so that an OS can utilise this information. Note: Although ETE and ETM share the same HID, ETE has a system register interfaces, unlike ETM which requires memory mapped registers. Since this patch aims to support ETE, the AML description does not describe any memory mapped registers. However, support for ETM can be added in the future. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
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/** @file
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SSDT Cpu Topology Table Generator.
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Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
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Copyright (c) 2021 - 2023, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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- ACPI 6.3 Specification - January 2019 - s8.4 Declaring Processors
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- ACPI for CoreSight version 1.2 Platform Design Document
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(https://developer.arm.com/documentation/den0067/a/?lang=en)
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@par Glossary:
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- ETE - Embedded Trace Extension.
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- ETM - Embedded Trace Macrocell.
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**/
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#ifndef SSDT_CPU_TOPOLOGY_GENERATOR_H_
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/// HID for a processor device.
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#define ACPI_HID_PROCESSOR_DEVICE "ACPI0007"
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/// HID for a ETM/ETE device.
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#define ACPI_HID_ET_DEVICE "ARMHC500"
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/// HID for a processor container device.
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#define ACPI_HID_PROCESSOR_CONTAINER_DEVICE "ACPI0010"
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