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UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address

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When trying to get page table base, if mInternalCr3 is zero, it will use
 the page table from CR3, and reflect the page table depth by CR4 LA57 bit.
If mInternalCr3 is non zero, it will use the page table from mInternalCr3
 and reflect the page table depth of mInternalCr3 at same time.
In the case of X64, we use m5LevelPagingNeeded to reflect the depth of
 the page table. And in the case of IA32, it will not the page table depth
 information.

This patch is a bug fix when enable CET feature with 5 level paging.
The SMM page tables are allocated / initialized in PiCpuSmmEntry().
When CET is enabled, PiCpuSmmEntry() must further modify the attribute of
 shadow stack pages. This page table is not set to CR3 in PiCpuSmmEntry().
 So the page table base address is set to mInternalCr3 for modifty the
 page table attribute. It could not use CR4 LA57 bit to reflect the
 page table depth for mInternalCr3.
So we create a architecture-specific implementation GetPageTable() with
 2 output parameters. One parameter is used to output the page table
 address. Another parameter is used to reflect if it is 5 level paging
 or not.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Sheng Wei
2020-11-09 13:16:57 +08:00
committed by mergify[bot]
parent 1a110fcd4e
commit 404250c8f7
4 changed files with 74 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
View File

@@ -49,22 +49,6 @@ SetPageTableBase (
mInternalCr3 = Cr3;
}
/**
Return page table base.
@return page table base.
**/
UINTN
GetPageTableBase (
VOID
)
{
if (mInternalCr3 != 0) {
return mInternalCr3;
}
return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
}
/**
Return length according to page attributes.
@@ -131,21 +115,20 @@ GetPageTableEntry (
UINT64 *L3PageTable;
UINT64 *L4PageTable;
UINT64 *L5PageTable;
IA32_CR4 Cr4;
UINTN PageTableBase;
BOOLEAN Enable5LevelPaging;
GetPageTable (&PageTableBase, &Enable5LevelPaging);
Index5 = ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK;
Index4 = ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK;
Index3 = ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK;
Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;
Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;
Cr4.UintN = AsmReadCr4 ();
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
if (sizeof(UINTN) == sizeof(UINT64)) {
if (Enable5LevelPaging) {
L5PageTable = (UINT64 *)GetPageTableBase ();
L5PageTable = (UINT64 *)PageTableBase;
if (L5PageTable[Index5] == 0) {
*PageAttribute = PageNone;
return NULL;
@@ -153,7 +136,7 @@ GetPageTableEntry (
L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
} else {
L4PageTable = (UINT64 *)GetPageTableBase ();
L4PageTable = (UINT64 *)PageTableBase;
}
if (L4PageTable[Index4] == 0) {
*PageAttribute = PageNone;
@@ -162,7 +145,7 @@ GetPageTableEntry (
L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
} else {
L3PageTable = (UINT64 *)GetPageTableBase ();
L3PageTable = (UINT64 *)PageTableBase;
}
if (L3PageTable[Index3] == 0) {
*PageAttribute = PageNone;