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ArmPlatformPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:53:52 -08:00
committed by mergify[bot]
parent 429309e0c6
commit 40b0b23ed3
47 changed files with 2846 additions and 2662 deletions
Download Patch File Download Diff File Expand all files Collapse all files

145
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c
View File

@@ -7,7 +7,6 @@
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
@@ -24,29 +23,31 @@
#include "PL061Gpio.h"
PLATFORM_GPIO_CONTROLLER *mPL061PlatformGpio;
PLATFORM_GPIO_CONTROLLER *mPL061PlatformGpio;
EFI_STATUS
EFIAPI
PL061Locate (
IN EMBEDDED_GPIO_PIN Gpio,
OUT UINTN *ControllerIndex,
OUT UINTN *ControllerOffset,
OUT UINTN *RegisterBase
IN EMBEDDED_GPIO_PIN Gpio,
OUT UINTN *ControllerIndex,
OUT UINTN *ControllerOffset,
OUT UINTN *RegisterBase
)
{
UINT32 Index;
UINT32 Index;
for (Index = 0; Index < mPL061PlatformGpio->GpioControllerCount; Index++) {
if ( (Gpio >= mPL061PlatformGpio->GpioController[Index].GpioIndex)
&& (Gpio < mPL061PlatformGpio->GpioController[Index].GpioIndex
+ mPL061PlatformGpio->GpioController[Index].InternalGpioCount)) {
*ControllerIndex = Index;
if ( (Gpio >= mPL061PlatformGpio->GpioController[Index].GpioIndex)
&& (Gpio < mPL061PlatformGpio->GpioController[Index].GpioIndex
+ mPL061PlatformGpio->GpioController[Index].InternalGpioCount))
{
*ControllerIndex = Index;
*ControllerOffset = Gpio % mPL061PlatformGpio->GpioController[Index].InternalGpioCount;
*RegisterBase = mPL061PlatformGpio->GpioController[Index].RegisterBase;
*RegisterBase = mPL061PlatformGpio->GpioController[Index].RegisterBase;
return EFI_SUCCESS;
}
}
DEBUG ((DEBUG_ERROR, "%a, failed to locate gpio %d\n", __func__, Gpio));
return EFI_INVALID_PARAMETER;
}
@@ -72,8 +73,8 @@ STATIC
UINTN
EFIAPI
PL061EffectiveAddress (
IN UINTN Address,
IN UINTN Mask
IN UINTN Address,
IN UINTN Mask
)
{
return ((Address + PL061_GPIO_DATA_REG_OFFSET) + (Mask << 2));
@@ -83,8 +84,8 @@ STATIC
UINTN
EFIAPI
PL061GetPins (
IN UINTN Address,
IN UINTN Mask
IN UINTN Address,
IN UINTN Mask
)
{
return MmioRead8 (PL061EffectiveAddress (Address, Mask));
@@ -94,9 +95,9 @@ STATIC
VOID
EFIAPI
PL061SetPins (
IN UINTN Address,
IN UINTN Mask,
IN UINTN Value
IN UINTN Address,
IN UINTN Mask,
IN UINTN Value
)
{
MmioWrite8 (PL061EffectiveAddress (Address, Mask), Value);
@@ -105,18 +106,18 @@ PL061SetPins (
/**
Function implementations
**/
EFI_STATUS
PL061Identify (
VOID
)
{
UINTN Index;
UINTN RegisterBase;
UINTN Index;
UINTN RegisterBase;
if ( (mPL061PlatformGpio->GpioCount == 0)
|| (mPL061PlatformGpio->GpioControllerCount == 0)) {
return EFI_NOT_FOUND;
if ( (mPL061PlatformGpio->GpioCount == 0)
|| (mPL061PlatformGpio->GpioControllerCount == 0))
{
return EFI_NOT_FOUND;
}
for (Index = 0; Index < mPL061PlatformGpio->GpioControllerCount; Index++) {
@@ -127,18 +128,20 @@ PL061Identify (
RegisterBase = mPL061PlatformGpio->GpioController[Index].RegisterBase;
// Check if this is a PrimeCell Peripheral
if ( (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID0) != 0x0D)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID1) != 0xF0)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID2) != 0x05)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID3) != 0xB1)) {
if ( (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID0) != 0x0D)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID1) != 0xF0)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID2) != 0x05)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID3) != 0xB1))
{
return EFI_NOT_FOUND;
}
// Check if this PrimeCell Peripheral is the PL061 GPIO
if ( (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID0) != 0x61)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID1) != 0x10)
|| ((MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID2) & 0xF) != 0x04)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID3) != 0x00)) {
if ( (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID0) != 0x61)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID1) != 0x10)
|| ((MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID2) & 0xF) != 0x04)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID3) != 0x00))
{
return EFI_NOT_FOUND;
}
}
@@ -166,13 +169,13 @@ Returns:
EFI_STATUS
EFIAPI
Get (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
OUT UINTN *Value
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
OUT UINTN *Value
)
{
EFI_STATUS Status;
UINTN Index, Offset, RegisterBase;
EFI_STATUS Status;
UINTN Index, Offset, RegisterBase;
Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
ASSERT_EFI_ERROR (Status);
@@ -181,7 +184,7 @@ Get (
return EFI_INVALID_PARAMETER;
}
if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset)) != 0) {
if (PL061GetPins (RegisterBase, GPIO_PIN_MASK (Offset)) != 0) {
*Value = 1;
} else {
*Value = 0;
@@ -216,32 +219,33 @@ Set (
IN EMBEDDED_GPIO_MODE Mode
)
{
EFI_STATUS Status;
UINTN Index, Offset, RegisterBase;
EFI_STATUS Status;
UINTN Index, Offset, RegisterBase;
Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
ASSERT_EFI_ERROR (Status);
switch (Mode)
{
switch (Mode) {
case GPIO_MODE_INPUT:
// Set the corresponding direction bit to LOW for input
MmioAnd8 (RegisterBase + PL061_GPIO_DIR_REG,
~GPIO_PIN_MASK(Offset) & 0xFF);
MmioAnd8 (
RegisterBase + PL061_GPIO_DIR_REG,
~GPIO_PIN_MASK(Offset) & 0xFF
);
break;
case GPIO_MODE_OUTPUT_0:
// Set the corresponding direction bit to HIGH for output
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset));
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK (Offset));
// Set the corresponding data bit to LOW for 0
PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0);
PL061SetPins (RegisterBase, GPIO_PIN_MASK (Offset), 0);
break;
case GPIO_MODE_OUTPUT_1:
// Set the corresponding direction bit to HIGH for output
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset));
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK (Offset));
// Set the corresponding data bit to HIGH for 1
PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff);
PL061SetPins (RegisterBase, GPIO_PIN_MASK (Offset), 0xff);
break;
default:
@@ -278,8 +282,8 @@ GetMode (
OUT EMBEDDED_GPIO_MODE *Mode
)
{
EFI_STATUS Status;
UINTN Index, Offset, RegisterBase;
EFI_STATUS Status;
UINTN Index, Offset, RegisterBase;
Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
ASSERT_EFI_ERROR (Status);
@@ -290,9 +294,9 @@ GetMode (
}
// Check if it is input or output
if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) {
if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK (Offset)) {
// Pin set to output
if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset)) != 0) {
if (PL061GetPins (RegisterBase, GPIO_PIN_MASK (Offset)) != 0) {
*Mode = GPIO_MODE_OUTPUT_1;
} else {
*Mode = GPIO_MODE_OUTPUT_0;
@@ -336,7 +340,7 @@ SetPull (
/**
Protocol variable definition
**/
EMBEDDED_GPIO gGpio = {
EMBEDDED_GPIO gGpio = {
Get,
Set,
GetMode,
@@ -357,13 +361,13 @@ EMBEDDED_GPIO gGpio = {
EFI_STATUS
EFIAPI
PL061InstallProtocol (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
GPIO_CONTROLLER *GpioController;
EFI_STATUS Status;
EFI_HANDLE Handle;
GPIO_CONTROLLER *GpioController;
//
// Make sure the Gpio protocol has not been installed in the system yet.
@@ -379,29 +383,30 @@ PL061InstallProtocol (
return EFI_BAD_BUFFER_SIZE;
}
mPL061PlatformGpio->GpioCount = PL061_GPIO_PINS;
mPL061PlatformGpio->GpioCount = PL061_GPIO_PINS;
mPL061PlatformGpio->GpioControllerCount = 1;
mPL061PlatformGpio->GpioController = (GPIO_CONTROLLER *)((UINTN) mPL061PlatformGpio + sizeof (PLATFORM_GPIO_CONTROLLER));
mPL061PlatformGpio->GpioController = (GPIO_CONTROLLER *)((UINTN)mPL061PlatformGpio + sizeof (PLATFORM_GPIO_CONTROLLER));
GpioController = mPL061PlatformGpio->GpioController;
GpioController->RegisterBase = (UINTN) PcdGet32 (PcdPL061GpioBase);
GpioController->GpioIndex = 0;
GpioController = mPL061PlatformGpio->GpioController;
GpioController->RegisterBase = (UINTN)PcdGet32 (PcdPL061GpioBase);
GpioController->GpioIndex = 0;
GpioController->InternalGpioCount = PL061_GPIO_PINS;
}
Status = PL061Identify();
if (EFI_ERROR(Status)) {
Status = PL061Identify ();
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
// Install the Embedded GPIO Protocol onto a new handle
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces(
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gEmbeddedGpioProtocolGuid, &gGpio,
&gEmbeddedGpioProtocolGuid,
&gGpio,
NULL
);
if (EFI_ERROR(Status)) {
);
if (EFI_ERROR (Status)) {
Status = EFI_OUT_OF_RESOURCES;
}

45
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h
View File

@@ -6,38 +6,37 @@
**/
#ifndef __PL061_GPIO_H__
#define __PL061_GPIO_H__
#include <Protocol/EmbeddedGpio.h>
// PL061 GPIO Registers
#define PL061_GPIO_DATA_REG_OFFSET ((UINTN) 0x000)
#define PL061_GPIO_DATA_REG 0x000
#define PL061_GPIO_DIR_REG 0x400
#define PL061_GPIO_IS_REG 0x404
#define PL061_GPIO_IBE_REG 0x408
#define PL061_GPIO_IEV_REG 0x40C
#define PL061_GPIO_IE_REG 0x410
#define PL061_GPIO_RIS_REG 0x414
#define PL061_GPIO_MIS_REG 0x410
#define PL061_GPIO_IC_REG 0x41C
#define PL061_GPIO_AFSEL_REG 0x420
#define PL061_GPIO_DATA_REG_OFFSET ((UINTN) 0x000)
#define PL061_GPIO_DATA_REG 0x000
#define PL061_GPIO_DIR_REG 0x400
#define PL061_GPIO_IS_REG 0x404
#define PL061_GPIO_IBE_REG 0x408
#define PL061_GPIO_IEV_REG 0x40C
#define PL061_GPIO_IE_REG 0x410
#define PL061_GPIO_RIS_REG 0x414
#define PL061_GPIO_MIS_REG 0x410
#define PL061_GPIO_IC_REG 0x41C
#define PL061_GPIO_AFSEL_REG 0x420
#define PL061_GPIO_PERIPH_ID0 0xFE0
#define PL061_GPIO_PERIPH_ID1 0xFE4
#define PL061_GPIO_PERIPH_ID2 0xFE8
#define PL061_GPIO_PERIPH_ID3 0xFEC
#define PL061_GPIO_PERIPH_ID0 0xFE0
#define PL061_GPIO_PERIPH_ID1 0xFE4
#define PL061_GPIO_PERIPH_ID2 0xFE8
#define PL061_GPIO_PERIPH_ID3 0xFEC
#define PL061_GPIO_PCELL_ID0 0xFF0
#define PL061_GPIO_PCELL_ID1 0xFF4
#define PL061_GPIO_PCELL_ID2 0xFF8
#define PL061_GPIO_PCELL_ID3 0xFFC
#define PL061_GPIO_PCELL_ID0 0xFF0
#define PL061_GPIO_PCELL_ID1 0xFF4
#define PL061_GPIO_PCELL_ID2 0xFF8
#define PL061_GPIO_PCELL_ID3 0xFFC
#define PL061_GPIO_PINS 8
#define PL061_GPIO_PINS 8
// All bits low except one bit high, native bit length
#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
#endif // __PL061_GPIO_H__
#endif // __PL061_GPIO_H__