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ArmPlatformPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:53:52 -08:00
committed by mergify[bot]
parent 429309e0c6
commit 40b0b23ed3
47 changed files with 2846 additions and 2662 deletions
Download Patch File Download Diff File Expand all files Collapse all files

86
ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c
View File

@@ -17,7 +17,7 @@
#include "ArmMaliDp.h"
// CORE_ID of the MALI DP
STATIC UINT32 mDpDeviceId;
STATIC UINT32 mDpDeviceId;
/** Disable the graphics layer
@@ -25,7 +25,9 @@ STATIC UINT32 mDpDeviceId;
**/
STATIC
VOID
LayerGraphicsDisable (VOID)
LayerGraphicsDisable (
VOID
)
{
MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE);
}
@@ -36,7 +38,9 @@ LayerGraphicsDisable (VOID)
**/
STATIC
VOID
LayerGraphicsEnable (VOID)
LayerGraphicsEnable (
VOID
)
{
MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE);
}
@@ -49,7 +53,7 @@ LayerGraphicsEnable (VOID)
STATIC
VOID
LayerGraphicsSetFrame (
IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
)
{
// Disable the graphics layer.
@@ -84,12 +88,12 @@ LayerGraphicsSetFrame (
STATIC
VOID
LayerGraphicsConfig (
IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat,
IN CONST UINT32 HRes,
IN CONST UINT32 VRes
IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat,
IN CONST UINT32 HRes,
IN CONST UINT32 VRes
)
{
UINT32 PixelFormat;
UINT32 PixelFormat;
// Disable the graphics layer before configuring any settings.
LayerGraphicsDisable ();
@@ -134,26 +138,26 @@ LayerGraphicsConfig (
STATIC
VOID
SetDisplayEngineTiming (
IN CONST SCAN_TIMINGS * CONST Horizontal,
IN CONST SCAN_TIMINGS * CONST Vertical
IN CONST SCAN_TIMINGS *CONST Horizontal,
IN CONST SCAN_TIMINGS *CONST Vertical
)
{
UINTN RegHIntervals;
UINTN RegVIntervals;
UINTN RegSyncControl;
UINTN RegHVActiveSize;
UINTN RegHIntervals;
UINTN RegVIntervals;
UINTN RegSyncControl;
UINTN RegHVActiveSize;
if (mDpDeviceId == MALIDP_500) {
// MALI DP500 timing registers.
RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS;
RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS;
RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL;
RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS;
RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS;
RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL;
RegHVActiveSize = DP_BASE + DP_DE_DP500_HV_ACTIVESIZE;
} else {
// MALI DP550/DP650 timing registers.
RegHIntervals = DP_BASE + DP_DE_H_INTERVALS;
RegVIntervals = DP_BASE + DP_DE_V_INTERVALS;
RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL;
RegHIntervals = DP_BASE + DP_DE_H_INTERVALS;
RegVIntervals = DP_BASE + DP_DE_V_INTERVALS;
RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL;
RegHVActiveSize = DP_BASE + DP_DE_HV_ACTIVESIZE;
}
@@ -194,11 +198,11 @@ UINT32
ArmMaliDpGetCoreId (
)
{
UINT32 DpCoreId;
UINT32 DpCoreId;
// First check for DP500 as register offset for DP550/DP650 CORE_ID
// is beyond 3K/4K register space of the DP500.
DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID);
DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID);
DpCoreId >>= DP_DE_DP500_CORE_ID_SHIFT;
if (DpCoreId == MALIDP_500) {
@@ -206,7 +210,7 @@ ArmMaliDpGetCoreId (
}
// Check for DP550 or DP650.
DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID);
DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID);
DpCoreId >>= DP_DC_CORE_ID_SHIFT;
if ((DpCoreId == MALIDP_550) || (DpCoreId == MALIDP_650)) {
@@ -227,9 +231,12 @@ ArmMaliDpGetCoreId (
on the platform.
**/
EFI_STATUS
LcdIdentify (VOID)
LcdIdentify (
VOID
)
{
DEBUG ((DEBUG_WARN,
DEBUG ((
DEBUG_WARN,
"Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n",
DP_BASE
));
@@ -239,8 +246,8 @@ LcdIdentify (VOID)
}
if (mDpDeviceId == MALIDP_NOT_PRESENT) {
DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n"));
return EFI_NOT_FOUND;
DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n"));
return EFI_NOT_FOUND;
}
DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId));
@@ -256,7 +263,7 @@ LcdIdentify (VOID)
**/
EFI_STATUS
LcdInitialize (
IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
)
{
DEBUG ((DEBUG_WARN, "Framebuffer base address = %p\n", FrameBaseAddress));
@@ -266,8 +273,11 @@ LcdInitialize (
}
if (mDpDeviceId == MALIDP_NOT_PRESENT) {
DEBUG ((DEBUG_ERROR, "ARM Mali DP initialization failed,"
"no ARM Mali DP present\n"));
DEBUG ((
DEBUG_ERROR,
"ARM Mali DP initialization failed,"
"no ARM Mali DP present\n"
));
return EFI_NOT_FOUND;
}
@@ -285,7 +295,9 @@ LcdInitialize (
**/
STATIC
VOID
SetConfigurationMode (VOID)
SetConfigurationMode (
VOID
)
{
// Request configuration Mode.
if (mDpDeviceId == MALIDP_500) {
@@ -303,7 +315,9 @@ SetConfigurationMode (VOID)
**/
STATIC
VOID
SetNormalMode (VOID)
SetNormalMode (
VOID
)
{
// Disable configuration Mode.
if (mDpDeviceId == MALIDP_500) {
@@ -321,7 +335,9 @@ SetNormalMode (VOID)
**/
STATIC
VOID
SetConfigValid (VOID)
SetConfigValid (
VOID
)
{
if (mDpDeviceId == MALIDP_500) {
MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID);
@@ -396,7 +412,9 @@ LcdSetMode (
**/
VOID
LcdShutdown (VOID)
LcdShutdown (
VOID
)
{
// Disable graphics layer.
LayerGraphicsDisable ();

307
ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h
View File

@@ -6,232 +6,233 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef ARMMALIDP_H_
#define ARMMALIDP_H_
#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))
#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))
// MALI DP Ids
#define MALIDP_NOT_PRESENT 0xFFF
#define MALIDP_500 0x500
#define MALIDP_550 0x550
#define MALIDP_650 0x650
#define MALIDP_NOT_PRESENT 0xFFF
#define MALIDP_500 0x500
#define MALIDP_550 0x550
#define MALIDP_650 0x650
// DP500 Peripheral Ids
#define DP500_ID_PART_0 0x00
#define DP500_ID_DES_0 0xB
#define DP500_ID_PART_1 0x5
#define DP500_ID_PART_0 0x00
#define DP500_ID_DES_0 0xB
#define DP500_ID_PART_1 0x5
#define DP500_ID_REVISION 0x1
#define DP500_ID_JEDEC 0x1
#define DP500_ID_DES_1 0x3
#define DP500_ID_REVISION 0x1
#define DP500_ID_JEDEC 0x1
#define DP500_ID_DES_1 0x3
#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)
#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \
#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)
#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \
| DP500_ID_PART_1)
#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \
#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \
| (DP500_ID_JEDEC << 3) \
| (DP500_ID_DES_1))
// DP550 Peripheral Ids
#define DP550_ID_PART_0 0x50
#define DP550_ID_DES_0 0xB
#define DP550_ID_PART_1 0x5
#define DP550_ID_PART_0 0x50
#define DP550_ID_DES_0 0xB
#define DP550_ID_PART_1 0x5
#define DP550_ID_REVISION 0x0
#define DP550_ID_JEDEC 0x1
#define DP550_ID_DES_1 0x3
#define DP550_ID_REVISION 0x0
#define DP550_ID_JEDEC 0x1
#define DP550_ID_DES_1 0x3
#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)
#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \
#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)
#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \
| DP550_ID_PART_1)
#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \
#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \
| (DP550_ID_JEDEC << 3) \
| (DP550_ID_DES_1))
// DP650 Peripheral Ids
#define DP650_ID_PART_0 0x50
#define DP650_ID_DES_0 0xB
#define DP650_ID_PART_1 0x6
#define DP650_ID_PART_0 0x50
#define DP650_ID_DES_0 0xB
#define DP650_ID_PART_1 0x6
#define DP650_ID_REVISION 0x0
#define DP650_ID_JEDEC 0x1
#define DP650_ID_DES_1 0x3
#define DP650_ID_REVISION 0x0
#define DP650_ID_JEDEC 0x1
#define DP650_ID_DES_1 0x3
#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)
#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \
#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)
#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \
| DP650_ID_PART_1)
#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \
#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \
| (DP650_ID_JEDEC << 3) \
| (DP650_ID_DES_1))
// Display Engine (DE) control register offsets for DP550/DP650
#define DP_DE_STATUS 0x00000
#define DP_DE_IRQ_SET 0x00004
#define DP_DE_IRQ_MASK 0x00008
#define DP_DE_IRQ_CLEAR 0x0000C
#define DP_DE_CONTROL 0x00010
#define DP_DE_PROG_LINE 0x00014
#define DP_DE_AXI_CONTROL 0x00018
#define DP_DE_AXI_QOS 0x0001C
#define DP_DE_DISPLAY_FUNCTION 0x00020
#define DP_DE_STATUS 0x00000
#define DP_DE_IRQ_SET 0x00004
#define DP_DE_IRQ_MASK 0x00008
#define DP_DE_IRQ_CLEAR 0x0000C
#define DP_DE_CONTROL 0x00010
#define DP_DE_PROG_LINE 0x00014
#define DP_DE_AXI_CONTROL 0x00018
#define DP_DE_AXI_QOS 0x0001C
#define DP_DE_DISPLAY_FUNCTION 0x00020
#define DP_DE_H_INTERVALS 0x00030
#define DP_DE_V_INTERVALS 0x00034
#define DP_DE_SYNC_CONTROL 0x00038
#define DP_DE_HV_ACTIVESIZE 0x0003C
#define DP_DE_DISPLAY_SIDEBAND 0x00040
#define DP_DE_BACKGROUND_COLOR 0x00044
#define DP_DE_DISPLAY_SPLIT 0x00048
#define DP_DE_OUTPUT_DEPTH 0x0004C
#define DP_DE_H_INTERVALS 0x00030
#define DP_DE_V_INTERVALS 0x00034
#define DP_DE_SYNC_CONTROL 0x00038
#define DP_DE_HV_ACTIVESIZE 0x0003C
#define DP_DE_DISPLAY_SIDEBAND 0x00040
#define DP_DE_BACKGROUND_COLOR 0x00044
#define DP_DE_DISPLAY_SPLIT 0x00048
#define DP_DE_OUTPUT_DEPTH 0x0004C
// Display Engine (DE) control register offsets for DP500
#define DP_DE_DP500_CORE_ID 0x00018
#define DP_DE_DP500_CONTROL 0x0000C
#define DP_DE_DP500_PROG_LINE 0x00010
#define DP_DE_DP500_H_INTERVALS 0x00028
#define DP_DE_DP500_V_INTERVALS 0x0002C
#define DP_DE_DP500_SYNC_CONTROL 0x00030
#define DP_DE_DP500_HV_ACTIVESIZE 0x00034
#define DP_DE_DP500_BG_COLOR_RG 0x0003C
#define DP_DE_DP500_BG_COLOR_B 0x00040
#define DP_DE_DP500_CORE_ID 0x00018
#define DP_DE_DP500_CONTROL 0x0000C
#define DP_DE_DP500_PROG_LINE 0x00010
#define DP_DE_DP500_H_INTERVALS 0x00028
#define DP_DE_DP500_V_INTERVALS 0x0002C
#define DP_DE_DP500_SYNC_CONTROL 0x00030
#define DP_DE_DP500_HV_ACTIVESIZE 0x00034
#define DP_DE_DP500_BG_COLOR_RG 0x0003C
#define DP_DE_DP500_BG_COLOR_B 0x00040
/* Display Engine (DE) graphics layer (LG) register offsets
* NOTE: For DP500 it will be LG2.
*/
#define DE_LG_OFFSET 0x00300
#define DP_DE_LG_FORMAT (DE_LG_OFFSET)
#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)
#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)
#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)
#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)
#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)
#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)
#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)
#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)
#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)
#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)
#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)
#define DE_LG_OFFSET 0x00300
#define DP_DE_LG_FORMAT (DE_LG_OFFSET)
#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)
#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)
#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)
#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)
#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)
#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)
#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)
#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)
#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)
#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)
#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)
// Display core (DC) control register offsets.
#define DP_DC_OFFSET 0x0C000
#define DP_DC_STATUS (DP_DC_OFFSET + 0x00)
#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)
#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)
#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)
#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)
#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)
#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)
#define DP_DC_OFFSET 0x0C000
#define DP_DC_STATUS (DP_DC_OFFSET + 0x00)
#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)
#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)
#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)
#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)
#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)
#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)
// DP500 has a global configuration register.
#define DP_DP500_CONFIG_VALID (0xF00)
#define DP_DP500_CONFIG_VALID (0xF00)
// Display core ID register offsets.
#define DP_DC_ID_OFFSET 0x0FF00
#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)
#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)
#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)
#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)
#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)
#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)
#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)
#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)
#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)
#define DP_DC_ID_OFFSET 0x0FF00
#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)
#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)
#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)
#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)
#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)
#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)
#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)
#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)
#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)
#define DP_DP500_ID_OFFSET 0x0F00
#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)
#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)
#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)
#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)
#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)
#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)
#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)
#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)
#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)
#define DP_DP500_ID_OFFSET 0x0F00
#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)
#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)
#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)
#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)
#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)
#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)
#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)
#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)
#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)
// Display status configuration mode activation flag
#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)
#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)
// Display core control configuration mode
#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)
#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)
#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)
#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)
#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)
#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)
#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16)
#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17)
// Display core configuration valid register
#define DP_DC_CONFIG_VALID_CVAL (0x1U)
#define DP_DC_CONFIG_VALID_CVAL (0x1U)
// DC_CORE_ID
// Display core version register PRODUCT_ID
#define DP_DC_CORE_ID_SHIFT 16
#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT
#define DP_DC_CORE_ID_SHIFT 16
#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT
// Timing settings
#define DP_DE_HBACKPORCH_SHIFT 16
#define DP_DE_VBACKPORCH_SHIFT 16
#define DP_DE_VSP_SHIFT 28
#define DP_DE_VSYNCWIDTH_SHIFT 16
#define DP_DE_HSP_SHIFT 13
#define DP_DE_V_ACTIVE_SHIFT 16
#define DP_DE_HBACKPORCH_SHIFT 16
#define DP_DE_VBACKPORCH_SHIFT 16
#define DP_DE_VSP_SHIFT 28
#define DP_DE_VSYNCWIDTH_SHIFT 16
#define DP_DE_HSP_SHIFT 13
#define DP_DE_V_ACTIVE_SHIFT 16
// BACKGROUND_COLOR
#define DP_DE_BG_R_PIXEL_SHIFT 16
#define DP_DE_BG_G_PIXEL_SHIFT 8
#define DP_DE_BG_R_PIXEL_SHIFT 16
#define DP_DE_BG_G_PIXEL_SHIFT 8
//Graphics layer LG_FORMAT Pixel Format
#define DP_PIXEL_FORMAT_ARGB_8888 0x8
#define DP_PIXEL_FORMAT_ABGR_8888 0x9
#define DP_PIXEL_FORMAT_RGBA_8888 0xA
#define DP_PIXEL_FORMAT_BGRA_8888 0xB
#define DP_PIXEL_FORMAT_XRGB_8888 0x10
#define DP_PIXEL_FORMAT_XBGR_8888 0x11
#define DP_PIXEL_FORMAT_RGBX_8888 0x12
#define DP_PIXEL_FORMAT_BGRX_8888 0x13
#define DP_PIXEL_FORMAT_RGB_888 0x18
#define DP_PIXEL_FORMAT_BGR_888 0x19
// Graphics layer LG_FORMAT Pixel Format
#define DP_PIXEL_FORMAT_ARGB_8888 0x8
#define DP_PIXEL_FORMAT_ABGR_8888 0x9
#define DP_PIXEL_FORMAT_RGBA_8888 0xA
#define DP_PIXEL_FORMAT_BGRA_8888 0xB
#define DP_PIXEL_FORMAT_XRGB_8888 0x10
#define DP_PIXEL_FORMAT_XBGR_8888 0x11
#define DP_PIXEL_FORMAT_RGBX_8888 0x12
#define DP_PIXEL_FORMAT_BGRX_8888 0x13
#define DP_PIXEL_FORMAT_RGB_888 0x18
#define DP_PIXEL_FORMAT_BGR_888 0x19
// DP500 format code are different than DP550/DP650
#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2
#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3
#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4
#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5
#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2
#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3
#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4
#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5
// Graphics layer LG_PTR_LOW and LG_PTR_HIGH
#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU
#define DP_DE_LG_PTR_HIGH_SHIFT 32
#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU
#define DP_DE_LG_PTR_HIGH_SHIFT 32
// Graphics layer LG_CONTROL register characteristics
#define DP_DE_LG_L_ALPHA_SHIFT 16
#define DP_DE_LG_CHK_SHIFT 15
#define DP_DE_LG_PMUL_SHIFT 14
#define DP_DE_LG_COM_SHIFT 12
#define DP_DE_LG_VFP_SHIFT 11
#define DP_DE_LG_HFP_SHIFT 10
#define DP_DE_LG_ROTATION_SHIFT 8
#define DP_DE_LG_L_ALPHA_SHIFT 16
#define DP_DE_LG_CHK_SHIFT 15
#define DP_DE_LG_PMUL_SHIFT 14
#define DP_DE_LG_COM_SHIFT 12
#define DP_DE_LG_VFP_SHIFT 11
#define DP_DE_LG_HFP_SHIFT 10
#define DP_DE_LG_ROTATION_SHIFT 8
#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U
#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U
#define DP_DE_LG_LAYER_BLEND_BG 0x2U
#define DP_DE_LG_PIXEL_BLEND_BG 0x3U
#define DP_DE_LG_ENABLE 0x1U
#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U
#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U
#define DP_DE_LG_LAYER_BLEND_BG 0x2U
#define DP_DE_LG_PIXEL_BLEND_BG 0x3U
#define DP_DE_LG_ENABLE 0x1U
// Graphics layer LG_IN_SIZE register characteristics
#define DP_DE_LG_V_IN_SIZE_SHIFT 16
#define DP_DE_LG_V_IN_SIZE_SHIFT 16
// Graphics layer LG_CMP_SIZE register characteristics
#define DP_DE_LG_V_CMP_SIZE_SHIFT 16
#define DP_DE_LG_V_OFFSET_SHIFT 16
#define DP_DE_LG_V_CMP_SIZE_SHIFT 16
#define DP_DE_LG_V_OFFSET_SHIFT 16
// Helper display timing macro functions.
#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)
#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)
#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)
#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)
#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)
#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)
#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)
#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)
// Helper layer graphics macros.
#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)
#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)
#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)
#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)
#endif /* ARMMALIDP_H_ */