ArmPlatformPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
429309e0c6
commit
40b0b23ed3
@@ -16,7 +16,7 @@
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#include "HdLcd.h"
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#define BYTES_PER_PIXEL 4
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#define BYTES_PER_PIXEL 4
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/** Initialize display.
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@@ -26,7 +26,7 @@
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**/
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EFI_STATUS
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LcdInitialize (
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IN EFI_PHYSICAL_ADDRESS VramBaseAddress
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IN EFI_PHYSICAL_ADDRESS VramBaseAddress
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)
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{
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// Disable the controller
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@@ -39,7 +39,7 @@ LcdInitialize (
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MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress);
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// Setup various registers that never change
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MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
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MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
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MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES);
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@@ -63,9 +63,9 @@ LcdSetMode (
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IN UINT32 ModeNumber
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)
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{
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EFI_STATUS Status;
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SCAN_TIMINGS *Horizontal;
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SCAN_TIMINGS *Vertical;
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EFI_STATUS Status;
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SCAN_TIMINGS *Horizontal;
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SCAN_TIMINGS *Vertical;
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EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
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@@ -100,11 +100,11 @@ LcdSetMode (
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: PixelBlueGreenRedReserved8BitPerColor;
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if (ModeInfo.PixelFormat == PixelFormat) {
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MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16);
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MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16);
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MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 0);
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} else {
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MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 16);
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MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0);
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MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0);
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}
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MmioWrite32 (HDLCD_REG_GREEN_SELECT, (8 << 8) | 8);
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@@ -126,15 +126,15 @@ LcdSetMode (
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MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1);
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// Set the vertical timing information
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MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync);
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MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch);
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MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1);
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MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync);
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MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch);
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MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1);
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MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, Vertical->FrontPorch);
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// Set the horizontal timing information
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MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync);
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MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch);
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MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1);
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MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync);
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MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch);
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MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1);
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MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, Horizontal->FrontPorch);
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// Enable the controller
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@@ -10,75 +10,75 @@
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#define HDLCD_H_
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// HDLCD Controller Register Offsets
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#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
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#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
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#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
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#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
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#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
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#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
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#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
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#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
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#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
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#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
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#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
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#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
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#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
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#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
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#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
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#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
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#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
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#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
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#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
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#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
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#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
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#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
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#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
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#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
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#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
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#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
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#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
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#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
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#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
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#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
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#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
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#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
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#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
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#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
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#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
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#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
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#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
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#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
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#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
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#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
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#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
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#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
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#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
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#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
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#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
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#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
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#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
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#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
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// HDLCD Values of registers
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// HDLCD Interrupt mask, clear and status register
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#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
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#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
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#define HDLCD_SYNC BIT2 /* Vertical sync */
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#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
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#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
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#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
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#define HDLCD_SYNC BIT2 /* Vertical sync */
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#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
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// CLCD_CONTROL Control register
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#define HDLCD_DISABLE 0
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#define HDLCD_ENABLE BIT0
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#define HDLCD_DISABLE 0
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#define HDLCD_ENABLE BIT0
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// Bus Options
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#define HDLCD_BURST_1 BIT0
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#define HDLCD_BURST_2 BIT1
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#define HDLCD_BURST_4 BIT2
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#define HDLCD_BURST_8 BIT3
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#define HDLCD_BURST_16 BIT4
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#define HDLCD_BURST_1 BIT0
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#define HDLCD_BURST_2 BIT1
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#define HDLCD_BURST_4 BIT2
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#define HDLCD_BURST_8 BIT3
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#define HDLCD_BURST_16 BIT4
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// Polarities - HIGH
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#define HDLCD_VSYNC_HIGH BIT0
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#define HDLCD_HSYNC_HIGH BIT1
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#define HDLCD_DATEN_HIGH BIT2
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#define HDLCD_DATA_HIGH BIT3
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#define HDLCD_PXCLK_HIGH BIT4
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#define HDLCD_VSYNC_HIGH BIT0
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#define HDLCD_HSYNC_HIGH BIT1
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#define HDLCD_DATEN_HIGH BIT2
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#define HDLCD_DATA_HIGH BIT3
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#define HDLCD_PXCLK_HIGH BIT4
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// Polarities - LOW (for completion and for ease of understanding the hardware settings)
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#define HDLCD_VSYNC_LOW 0
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#define HDLCD_HSYNC_LOW 0
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#define HDLCD_DATEN_LOW 0
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#define HDLCD_DATA_LOW 0
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#define HDLCD_PXCLK_LOW 0
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#define HDLCD_VSYNC_LOW 0
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#define HDLCD_HSYNC_LOW 0
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#define HDLCD_DATEN_LOW 0
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#define HDLCD_DATA_LOW 0
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#define HDLCD_PXCLK_LOW 0
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// Default polarities
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#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
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#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
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HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \
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HDLCD_VSYNC_HIGH)
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// Pixel Format
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#define HDLCD_LITTLE_ENDIAN (0 << 31)
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#define HDLCD_BIG_ENDIAN (1 << 31)
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#define HDLCD_LITTLE_ENDIAN (0 << 31)
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#define HDLCD_BIG_ENDIAN (1 << 31)
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// Number of bytes per pixel
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#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
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#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
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#define HDLCD_PRODUCT_ID 0x1CDC
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#define HDLCD_PRODUCT_ID 0x1CDC
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#endif /* HDLCD_H_ */
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