ArmPlatformPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
429309e0c6
commit
40b0b23ed3
@@ -9,106 +9,106 @@
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#ifndef __PL011_UART_H__
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#define __PL011_UART_H__
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#define PL011_VARIANT_ZTE 1
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#define PL011_VARIANT_ZTE 1
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// PL011 Registers
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#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
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#define UARTDR 0x004
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#define UARTRSR 0x010
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#define UARTECR 0x010
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#define UARTFR 0x014
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x030
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#define UARTCR 0x034
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#define UARTIFLS 0x038
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#define UARTIMSC 0x040
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#define UARTRIS 0x044
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#define UARTMIS 0x048
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#define UARTICR 0x04c
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#define UARTDMACR 0x050
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#define UARTDR 0x004
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#define UARTRSR 0x010
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#define UARTECR 0x010
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#define UARTFR 0x014
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x030
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#define UARTCR 0x034
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#define UARTIFLS 0x038
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#define UARTIMSC 0x040
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#define UARTRIS 0x044
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#define UARTMIS 0x048
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#define UARTICR 0x04c
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#define UARTDMACR 0x050
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#else
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#define UARTDR 0x000
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#define UARTRSR 0x004
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#define UARTECR 0x004
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#define UARTFR 0x018
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#define UARTILPR 0x020
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x02C
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#define UARTCR 0x030
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#define UARTIFLS 0x034
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#define UARTIMSC 0x038
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#define UARTRIS 0x03C
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#define UARTMIS 0x040
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#define UARTICR 0x044
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#define UARTDMACR 0x048
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#define UARTDR 0x000
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#define UARTRSR 0x004
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#define UARTECR 0x004
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#define UARTFR 0x018
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#define UARTILPR 0x020
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x02C
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#define UARTCR 0x030
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#define UARTIFLS 0x034
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#define UARTIMSC 0x038
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#define UARTRIS 0x03C
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#define UARTMIS 0x040
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#define UARTICR 0x044
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#define UARTDMACR 0x048
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#endif
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#define UARTPID0 0xFE0
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#define UARTPID1 0xFE4
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#define UARTPID2 0xFE8
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#define UARTPID3 0xFEC
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#define UARTPID0 0xFE0
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#define UARTPID1 0xFE4
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#define UARTPID2 0xFE8
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#define UARTPID3 0xFEC
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// Data status bits
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#define UART_DATA_ERROR_MASK 0x0F00
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#define UART_DATA_ERROR_MASK 0x0F00
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// Status reg bits
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#define UART_STATUS_ERROR_MASK 0x0F
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#define UART_STATUS_ERROR_MASK 0x0F
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// Flag reg bits
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#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
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#define PL011_UARTFR_RI (1 << 0) // Ring indicator
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#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY (1 << 8) // UART busy
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#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
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#define PL011_UARTFR_DSR (1 << 3) // Data set ready
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#define PL011_UARTFR_CTS (1 << 1) // Clear to send
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#define PL011_UARTFR_RI (1 << 0) // Ring indicator
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#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY (1 << 8) // UART busy
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#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
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#define PL011_UARTFR_DSR (1 << 3) // Data set ready
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#define PL011_UARTFR_CTS (1 << 1) // Clear to send
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#else
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#define PL011_UARTFR_RI (1 << 8) // Ring indicator
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#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY (1 << 3) // UART busy
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#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
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#define PL011_UARTFR_DSR (1 << 1) // Data set ready
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#define PL011_UARTFR_CTS (1 << 0) // Clear to send
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#define PL011_UARTFR_RI (1 << 8) // Ring indicator
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#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY (1 << 3) // UART busy
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#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
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#define PL011_UARTFR_DSR (1 << 1) // Data set ready
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#define PL011_UARTFR_CTS (1 << 0) // Clear to send
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#endif
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// Flag reg bits - alternative names
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#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
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#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
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#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
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#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
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#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
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#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
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#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
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#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
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#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
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#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
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// Control reg bits
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#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
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#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
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#define PL011_UARTCR_RTS (1 << 11) // Request to send
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#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
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#define PL011_UARTCR_RXE (1 << 9) // Receive enable
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#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
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#define PL011_UARTCR_LBE (1 << 7) // Loopback enable
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#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
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#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
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#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
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#define PL011_UARTCR_RTS (1 << 11) // Request to send
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#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
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#define PL011_UARTCR_RXE (1 << 9) // Receive enable
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#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
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#define PL011_UARTCR_LBE (1 << 7) // Loopback enable
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#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
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// Line Control Register Bits
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#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
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#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
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#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
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#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
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#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
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#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
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#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
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#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
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#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
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#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
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#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
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#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
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#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
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#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
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#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
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#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
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#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
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#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
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#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
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#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
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#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)
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#define PL011_VER_R1P4 0x2
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#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)
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#define PL011_VER_R1P4 0x2
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#endif
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@@ -25,7 +25,7 @@
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// EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only
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// control bit that is not supported.
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//
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STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
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STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
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/**
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@@ -73,16 +73,16 @@ PL011UartInitializePort (
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IN OUT EFI_STOP_BITS_TYPE *StopBits
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)
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{
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UINT32 LineControl;
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UINT32 Divisor;
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UINT32 Integer;
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UINT32 Fractional;
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UINT32 HardwareFifoDepth;
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UINT32 UartPid2;
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UINT32 LineControl;
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UINT32 Divisor;
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UINT32 Integer;
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UINT32 Fractional;
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UINT32 HardwareFifoDepth;
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UINT32 UartPid2;
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HardwareFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
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if (HardwareFifoDepth == 0) {
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UartPid2 = MmioRead32 (UartBase + UARTPID2);
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UartPid2 = MmioRead32 (UartBase + UARTPID2);
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HardwareFifoDepth = (PL011_UARTPID2_VER (UartPid2) > PL011_VER_R1P4) ? 32 : 16;
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}
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@@ -91,7 +91,7 @@ PL011UartInitializePort (
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// down, there is no maximum FIFO size.
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if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {
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// Enable FIFO
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LineControl = PL011_UARTLCR_H_FEN;
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LineControl = PL011_UARTLCR_H_FEN;
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*ReceiveFifoDepth = HardwareFifoDepth;
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} else {
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// Disable FIFO
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@@ -104,67 +104,67 @@ PL011UartInitializePort (
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// Parity
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//
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switch (*Parity) {
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case DefaultParity:
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*Parity = NoParity;
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case NoParity:
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// Nothing to do. Parity is disabled by default.
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break;
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case EvenParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
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break;
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case OddParity:
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LineControl |= PL011_UARTLCR_H_PEN;
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break;
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case MarkParity:
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LineControl |= ( PL011_UARTLCR_H_PEN \
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| PL011_UARTLCR_H_SPS \
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| PL011_UARTLCR_H_EPS);
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break;
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case SpaceParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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case DefaultParity:
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*Parity = NoParity;
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case NoParity:
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// Nothing to do. Parity is disabled by default.
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break;
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case EvenParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
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break;
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case OddParity:
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LineControl |= PL011_UARTLCR_H_PEN;
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break;
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case MarkParity:
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LineControl |= (PL011_UARTLCR_H_PEN \
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| PL011_UARTLCR_H_SPS \
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| PL011_UARTLCR_H_EPS);
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break;
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case SpaceParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Data Bits
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//
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switch (*DataBits) {
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case 0:
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*DataBits = 8;
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case 8:
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LineControl |= PL011_UARTLCR_H_WLEN_8;
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break;
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case 7:
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LineControl |= PL011_UARTLCR_H_WLEN_7;
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break;
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case 6:
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LineControl |= PL011_UARTLCR_H_WLEN_6;
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break;
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case 5:
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LineControl |= PL011_UARTLCR_H_WLEN_5;
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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case 0:
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*DataBits = 8;
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case 8:
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LineControl |= PL011_UARTLCR_H_WLEN_8;
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break;
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case 7:
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LineControl |= PL011_UARTLCR_H_WLEN_7;
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break;
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case 6:
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LineControl |= PL011_UARTLCR_H_WLEN_6;
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break;
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case 5:
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LineControl |= PL011_UARTLCR_H_WLEN_5;
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Stop Bits
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//
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switch (*StopBits) {
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case DefaultStopBits:
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*StopBits = OneStopBit;
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case OneStopBit:
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// Nothing to do. One stop bit is enabled by default.
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break;
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case TwoStopBits:
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LineControl |= PL011_UARTLCR_H_STP2;
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break;
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case OneFiveStopBits:
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case DefaultStopBits:
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*StopBits = OneStopBit;
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case OneStopBit:
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// Nothing to do. One stop bit is enabled by default.
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break;
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case TwoStopBits:
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LineControl |= PL011_UARTLCR_H_STP2;
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break;
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case OneFiveStopBits:
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// Only 1 or 2 stop bits are supported
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default:
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return RETURN_INVALID_PARAMETER;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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// Don't send the LineControl value to the PL011 yet,
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@@ -178,7 +178,7 @@ PL011UartInitializePort (
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// If PL011 Integer value has been defined then always ignore the BAUD rate
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if (FixedPcdGet32 (PL011UartInteger) != 0) {
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Integer = FixedPcdGet32 (PL011UartInteger);
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Integer = FixedPcdGet32 (PL011UartInteger);
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Fractional = FixedPcdGet32 (PL011UartFractional);
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} else {
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// If BAUD rate is zero then replace it with the system default value
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@@ -188,12 +188,13 @@ PL011UartInitializePort (
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return RETURN_INVALID_PARAMETER;
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}
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}
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if (0 == UartClkInHz) {
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return RETURN_INVALID_PARAMETER;
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}
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Divisor = (UartClkInHz * 4) / *BaudRate;
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Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
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Divisor = (UartClkInHz * 4) / *BaudRate;
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Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
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Fractional = Divisor & FRACTION_PART_MASK;
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}
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@@ -202,15 +203,17 @@ PL011UartInitializePort (
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// and re-initialize only if the settings are different.
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//
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if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&
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(MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
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(MmioRead32 (UartBase + UARTIBRD) == Integer) &&
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(MmioRead32 (UartBase + UARTFBRD) == Fractional)) {
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(MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
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(MmioRead32 (UartBase + UARTIBRD) == Integer) &&
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(MmioRead32 (UartBase + UARTFBRD) == Fractional))
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{
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// Nothing to do - already initialized with correct attributes
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return RETURN_SUCCESS;
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}
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// Wait for the end of transmission
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while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);
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while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0) {
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}
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// Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed
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// when the UART is enabled"
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@@ -227,8 +230,10 @@ PL011UartInitializePort (
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MmioWrite32 (UartBase + UARTECR, 0);
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// Enable Tx, Rx, and UART overall
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MmioWrite32 (UartBase + UARTCR,
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PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);
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MmioWrite32 (
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UartBase + UARTCR,
|
||||
PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN
|
||||
);
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
@@ -263,8 +268,8 @@ PL011UartInitializePort (
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
PL011UartSetControl (
|
||||
IN UINTN UartBase,
|
||||
IN UINT32 Control
|
||||
IN UINTN UartBase,
|
||||
IN UINT32 Control
|
||||
)
|
||||
{
|
||||
UINT32 Bits;
|
||||
@@ -340,15 +345,14 @@ PL011UartSetControl (
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
PL011UartGetControl (
|
||||
IN UINTN UartBase,
|
||||
OUT UINT32 *Control
|
||||
IN UINTN UartBase,
|
||||
OUT UINT32 *Control
|
||||
)
|
||||
{
|
||||
UINT32 FlagRegister;
|
||||
UINT32 ControlRegister;
|
||||
UINT32 FlagRegister;
|
||||
UINT32 ControlRegister;
|
||||
|
||||
|
||||
FlagRegister = MmioRead32 (UartBase + UARTFR);
|
||||
FlagRegister = MmioRead32 (UartBase + UARTFR);
|
||||
ControlRegister = MmioRead32 (UartBase + UARTCR);
|
||||
|
||||
*Control = 0;
|
||||
@@ -386,7 +390,8 @@ PL011UartGetControl (
|
||||
}
|
||||
|
||||
if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
|
||||
== (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {
|
||||
== (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
|
||||
{
|
||||
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
|
||||
}
|
||||
|
||||
@@ -410,16 +415,17 @@ PL011UartGetControl (
|
||||
UINTN
|
||||
EFIAPI
|
||||
PL011UartWrite (
|
||||
IN UINTN UartBase,
|
||||
IN UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
IN UINTN UartBase,
|
||||
IN UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
)
|
||||
{
|
||||
UINT8* CONST Final = &Buffer[NumberOfBytes];
|
||||
UINT8 *CONST Final = &Buffer[NumberOfBytes];
|
||||
|
||||
while (Buffer < Final) {
|
||||
// Wait until UART able to accept another char
|
||||
while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));
|
||||
while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK)) {
|
||||
}
|
||||
|
||||
MmioWrite8 (UartBase + UARTDR, *Buffer++);
|
||||
}
|
||||
@@ -440,15 +446,17 @@ PL011UartWrite (
|
||||
UINTN
|
||||
EFIAPI
|
||||
PL011UartRead (
|
||||
IN UINTN UartBase,
|
||||
OUT UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
IN UINTN UartBase,
|
||||
OUT UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
)
|
||||
{
|
||||
UINTN Count;
|
||||
UINTN Count;
|
||||
|
||||
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
|
||||
while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
|
||||
while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0) {
|
||||
}
|
||||
|
||||
*Buffer = MmioRead8 (UartBase + UARTDR);
|
||||
}
|
||||
|
||||
@@ -465,7 +473,7 @@ PL011UartRead (
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
PL011UartPoll (
|
||||
IN UINTN UartBase
|
||||
IN UINTN UartBase
|
||||
)
|
||||
{
|
||||
return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
|
||||
|
||||
Reference in New Issue
Block a user