ArmPlatformPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
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mergify[bot]
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429309e0c6
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40b0b23ed3
@@ -25,7 +25,7 @@
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// EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only
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// control bit that is not supported.
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//
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STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
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STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
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/**
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@@ -73,16 +73,16 @@ PL011UartInitializePort (
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IN OUT EFI_STOP_BITS_TYPE *StopBits
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)
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{
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UINT32 LineControl;
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UINT32 Divisor;
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UINT32 Integer;
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UINT32 Fractional;
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UINT32 HardwareFifoDepth;
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UINT32 UartPid2;
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UINT32 LineControl;
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UINT32 Divisor;
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UINT32 Integer;
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UINT32 Fractional;
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UINT32 HardwareFifoDepth;
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UINT32 UartPid2;
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HardwareFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
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if (HardwareFifoDepth == 0) {
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UartPid2 = MmioRead32 (UartBase + UARTPID2);
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UartPid2 = MmioRead32 (UartBase + UARTPID2);
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HardwareFifoDepth = (PL011_UARTPID2_VER (UartPid2) > PL011_VER_R1P4) ? 32 : 16;
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}
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@@ -91,7 +91,7 @@ PL011UartInitializePort (
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// down, there is no maximum FIFO size.
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if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {
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// Enable FIFO
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LineControl = PL011_UARTLCR_H_FEN;
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LineControl = PL011_UARTLCR_H_FEN;
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*ReceiveFifoDepth = HardwareFifoDepth;
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} else {
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// Disable FIFO
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@@ -104,67 +104,67 @@ PL011UartInitializePort (
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// Parity
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//
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switch (*Parity) {
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case DefaultParity:
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*Parity = NoParity;
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case NoParity:
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// Nothing to do. Parity is disabled by default.
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break;
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case EvenParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
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break;
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case OddParity:
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LineControl |= PL011_UARTLCR_H_PEN;
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break;
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case MarkParity:
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LineControl |= ( PL011_UARTLCR_H_PEN \
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| PL011_UARTLCR_H_SPS \
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| PL011_UARTLCR_H_EPS);
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break;
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case SpaceParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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case DefaultParity:
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*Parity = NoParity;
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case NoParity:
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// Nothing to do. Parity is disabled by default.
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break;
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case EvenParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
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break;
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case OddParity:
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LineControl |= PL011_UARTLCR_H_PEN;
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break;
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case MarkParity:
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LineControl |= (PL011_UARTLCR_H_PEN \
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| PL011_UARTLCR_H_SPS \
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| PL011_UARTLCR_H_EPS);
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break;
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case SpaceParity:
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LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Data Bits
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//
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switch (*DataBits) {
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case 0:
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*DataBits = 8;
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case 8:
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LineControl |= PL011_UARTLCR_H_WLEN_8;
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break;
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case 7:
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LineControl |= PL011_UARTLCR_H_WLEN_7;
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break;
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case 6:
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LineControl |= PL011_UARTLCR_H_WLEN_6;
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break;
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case 5:
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LineControl |= PL011_UARTLCR_H_WLEN_5;
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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case 0:
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*DataBits = 8;
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case 8:
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LineControl |= PL011_UARTLCR_H_WLEN_8;
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break;
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case 7:
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LineControl |= PL011_UARTLCR_H_WLEN_7;
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break;
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case 6:
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LineControl |= PL011_UARTLCR_H_WLEN_6;
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break;
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case 5:
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LineControl |= PL011_UARTLCR_H_WLEN_5;
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break;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Stop Bits
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//
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switch (*StopBits) {
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case DefaultStopBits:
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*StopBits = OneStopBit;
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case OneStopBit:
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// Nothing to do. One stop bit is enabled by default.
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break;
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case TwoStopBits:
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LineControl |= PL011_UARTLCR_H_STP2;
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break;
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case OneFiveStopBits:
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case DefaultStopBits:
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*StopBits = OneStopBit;
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case OneStopBit:
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// Nothing to do. One stop bit is enabled by default.
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break;
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case TwoStopBits:
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LineControl |= PL011_UARTLCR_H_STP2;
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break;
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case OneFiveStopBits:
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// Only 1 or 2 stop bits are supported
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default:
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return RETURN_INVALID_PARAMETER;
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default:
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return RETURN_INVALID_PARAMETER;
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}
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// Don't send the LineControl value to the PL011 yet,
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@@ -178,7 +178,7 @@ PL011UartInitializePort (
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// If PL011 Integer value has been defined then always ignore the BAUD rate
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if (FixedPcdGet32 (PL011UartInteger) != 0) {
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Integer = FixedPcdGet32 (PL011UartInteger);
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Integer = FixedPcdGet32 (PL011UartInteger);
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Fractional = FixedPcdGet32 (PL011UartFractional);
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} else {
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// If BAUD rate is zero then replace it with the system default value
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@@ -188,12 +188,13 @@ PL011UartInitializePort (
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return RETURN_INVALID_PARAMETER;
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}
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}
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if (0 == UartClkInHz) {
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return RETURN_INVALID_PARAMETER;
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}
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Divisor = (UartClkInHz * 4) / *BaudRate;
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Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
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Divisor = (UartClkInHz * 4) / *BaudRate;
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Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
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Fractional = Divisor & FRACTION_PART_MASK;
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}
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@@ -202,15 +203,17 @@ PL011UartInitializePort (
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// and re-initialize only if the settings are different.
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//
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if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&
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(MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
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(MmioRead32 (UartBase + UARTIBRD) == Integer) &&
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(MmioRead32 (UartBase + UARTFBRD) == Fractional)) {
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(MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
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(MmioRead32 (UartBase + UARTIBRD) == Integer) &&
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(MmioRead32 (UartBase + UARTFBRD) == Fractional))
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{
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// Nothing to do - already initialized with correct attributes
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return RETURN_SUCCESS;
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}
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// Wait for the end of transmission
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while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);
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while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0) {
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}
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// Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed
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// when the UART is enabled"
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@@ -227,8 +230,10 @@ PL011UartInitializePort (
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MmioWrite32 (UartBase + UARTECR, 0);
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// Enable Tx, Rx, and UART overall
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MmioWrite32 (UartBase + UARTCR,
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PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);
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MmioWrite32 (
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UartBase + UARTCR,
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PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN
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);
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return RETURN_SUCCESS;
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}
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@@ -263,8 +268,8 @@ PL011UartInitializePort (
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RETURN_STATUS
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EFIAPI
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PL011UartSetControl (
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IN UINTN UartBase,
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IN UINT32 Control
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IN UINTN UartBase,
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IN UINT32 Control
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)
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{
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UINT32 Bits;
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@@ -340,15 +345,14 @@ PL011UartSetControl (
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RETURN_STATUS
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EFIAPI
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PL011UartGetControl (
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IN UINTN UartBase,
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OUT UINT32 *Control
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IN UINTN UartBase,
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OUT UINT32 *Control
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)
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{
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UINT32 FlagRegister;
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UINT32 ControlRegister;
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UINT32 FlagRegister;
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UINT32 ControlRegister;
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FlagRegister = MmioRead32 (UartBase + UARTFR);
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FlagRegister = MmioRead32 (UartBase + UARTFR);
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ControlRegister = MmioRead32 (UartBase + UARTCR);
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*Control = 0;
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@@ -386,7 +390,8 @@ PL011UartGetControl (
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}
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if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
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== (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {
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== (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
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{
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*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
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}
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@@ -410,16 +415,17 @@ PL011UartGetControl (
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UINTN
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EFIAPI
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PL011UartWrite (
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IN UINTN UartBase,
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IN UINT8 *Buffer,
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IN UINTN NumberOfBytes
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IN UINTN UartBase,
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IN UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINT8* CONST Final = &Buffer[NumberOfBytes];
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UINT8 *CONST Final = &Buffer[NumberOfBytes];
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while (Buffer < Final) {
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// Wait until UART able to accept another char
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while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));
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while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK)) {
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}
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MmioWrite8 (UartBase + UARTDR, *Buffer++);
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}
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@@ -440,15 +446,17 @@ PL011UartWrite (
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UINTN
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EFIAPI
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PL011UartRead (
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IN UINTN UartBase,
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OUT UINT8 *Buffer,
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IN UINTN NumberOfBytes
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IN UINTN UartBase,
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OUT UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINTN Count;
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UINTN Count;
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for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
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while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
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while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0) {
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}
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*Buffer = MmioRead8 (UartBase + UARTDR);
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}
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@@ -465,7 +473,7 @@ PL011UartRead (
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BOOLEAN
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EFIAPI
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PL011UartPoll (
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IN UINTN UartBase
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IN UINTN UartBase
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)
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{
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return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
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