ArmPlatformPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
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40b0b23ed3
@@ -24,7 +24,7 @@
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN MpId
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IN UINTN MpId
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)
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{
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EFI_STATUS Status;
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@@ -37,18 +37,21 @@ SecondaryMain (
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ARM_CORE_INFO *ArmCoreInfoTable;
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UINT32 ClusterId;
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UINT32 CoreId;
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VOID (*SecondaryStart)(VOID);
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UINTN SecondaryEntryAddr;
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UINTN AcknowledgeInterrupt;
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UINTN InterruptId;
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ClusterId = GET_CLUSTER_ID(MpId);
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CoreId = GET_CORE_ID(MpId);
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VOID (*SecondaryStart)(
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VOID
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);
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UINTN SecondaryEntryAddr;
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UINTN AcknowledgeInterrupt;
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UINTN InterruptId;
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ClusterId = GET_CLUSTER_ID (MpId);
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CoreId = GET_CORE_ID (MpId);
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// Get the gArmMpCoreInfoPpiGuid
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PpiListSize = 0;
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ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
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PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
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PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
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for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
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if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
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break;
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@@ -59,8 +62,8 @@ SecondaryMain (
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ASSERT (Index != PpiListCount);
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ArmMpCoreInfoPpi = PpiList->Ppi;
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ArmCoreCount = 0;
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Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
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ArmCoreCount = 0;
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Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
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ASSERT_EFI_ERROR (Status);
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// Find the core in the ArmCoreTable
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@@ -92,11 +95,11 @@ SecondaryMain (
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} while (SecondaryEntryAddr == 0);
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// Jump to secondary core entry point.
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SecondaryStart = (VOID (*)())SecondaryEntryAddr;
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SecondaryStart();
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SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
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SecondaryStart ();
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// The secondaries shouldn't reach here
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ASSERT(FALSE);
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ASSERT (FALSE);
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}
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VOID
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@@ -105,26 +108,26 @@ PrimaryMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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UINTN PpiListSize;
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EFI_PEI_PPI_DESCRIPTOR *PpiList;
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UINTN TemporaryRamBase;
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UINTN TemporaryRamSize;
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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UINTN PpiListSize;
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EFI_PEI_PPI_DESCRIPTOR *PpiList;
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UINTN TemporaryRamBase;
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UINTN TemporaryRamSize;
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CreatePpiList (&PpiListSize, &PpiList);
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// Enable the GIC Distributor
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ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));
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ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
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// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
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if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
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// Sending SGI to all the Secondary CPU interfaces
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ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
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ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
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}
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// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
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// the base of the primary core stack
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PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);
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PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
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TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
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TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
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@@ -133,7 +136,7 @@ PrimaryMain (
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
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