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ArmPlatformPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:53:52 -08:00
committed by mergify[bot]
parent 429309e0c6
commit 40b0b23ed3
47 changed files with 2846 additions and 2662 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
ArmPlatformPkg/PrePi/Arm/ArchPrePi.c
View File

@@ -20,4 +20,3 @@ ArchInitialize (
ArmEnableVFP ();
}
}

55
ArmPlatformPkg/PrePi/MainMPCore.c
View File

@@ -14,52 +14,55 @@
VOID
PrimaryMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
)
{
// Enable the GIC Distributor
ArmGicEnableDistributor(PcdGet64(PcdGicDistributorBase));
ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {
if (!FixedPcdGet32 (PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces
ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
}
PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
// We must never return
ASSERT(FALSE);
ASSERT (FALSE);
}
VOID
SecondaryMain (
IN UINTN MpId
IN UINTN MpId
)
{
EFI_STATUS Status;
ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN Index;
UINTN ArmCoreCount;
ARM_CORE_INFO *ArmCoreInfoTable;
UINT32 ClusterId;
UINT32 CoreId;
VOID (*SecondaryStart)(VOID);
UINTN SecondaryEntryAddr;
UINTN AcknowledgeInterrupt;
UINTN InterruptId;
EFI_STATUS Status;
ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN Index;
UINTN ArmCoreCount;
ARM_CORE_INFO *ArmCoreInfoTable;
UINT32 ClusterId;
UINT32 CoreId;
ClusterId = GET_CLUSTER_ID(MpId);
CoreId = GET_CORE_ID(MpId);
VOID (*SecondaryStart)(
VOID
);
UINTN SecondaryEntryAddr;
UINTN AcknowledgeInterrupt;
UINTN InterruptId;
ClusterId = GET_CLUSTER_ID (MpId);
CoreId = GET_CORE_ID (MpId);
// On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
ASSERT_EFI_ERROR (Status);
ArmCoreCount = 0;
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
ASSERT_EFI_ERROR (Status);
// Find the core in the ArmCoreTable
@@ -91,9 +94,9 @@ SecondaryMain (
} while (SecondaryEntryAddr == 0);
// Jump to secondary core entry point.
SecondaryStart = (VOID (*)())SecondaryEntryAddr;
SecondaryStart();
SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
SecondaryStart ();
// The secondaries shouldn't reach here
ASSERT(FALSE);
ASSERT (FALSE);
}

13
ArmPlatformPkg/PrePi/MainUniCore.c
View File

@@ -10,23 +10,22 @@
VOID
PrimaryMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
)
{
PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
// We must never return
ASSERT(FALSE);
ASSERT (FALSE);
}
VOID
SecondaryMain (
IN UINTN MpId
IN UINTN MpId
)
{
// We must never get into this function on UniCore system
ASSERT(FALSE);
ASSERT (FALSE);
}

90
ArmPlatformPkg/PrePi/PrePi.c
View File

@@ -22,11 +22,11 @@
#include "PrePi.h"
#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \
#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) ||\
((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))
UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +
FixedPcdGet64(PcdSystemMemorySize) - 1;
UINT64 mSystemMemoryEnd = FixedPcdGet64 (PcdSystemMemoryBase) +
FixedPcdGet64 (PcdSystemMemorySize) - 1;
EFI_STATUS
GetPlatformPpi (
@@ -41,7 +41,7 @@ GetPlatformPpi (
PpiListSize = 0;
ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
*Ppi = PpiList->Ppi;
@@ -54,34 +54,42 @@ GetPlatformPpi (
VOID
PrePiMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
)
{
EFI_HOB_HANDOFF_INFO_TABLE* HobList;
ARM_MP_CORE_INFO_PPI* ArmMpCoreInfoPpi;
UINTN ArmCoreCount;
ARM_CORE_INFO* ArmCoreInfoTable;
EFI_STATUS Status;
CHAR8 Buffer[100];
UINTN CharCount;
UINTN StacksSize;
FIRMWARE_SEC_PERFORMANCE Performance;
EFI_HOB_HANDOFF_INFO_TABLE *HobList;
ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN ArmCoreCount;
ARM_CORE_INFO *ArmCoreInfoTable;
EFI_STATUS Status;
CHAR8 Buffer[100];
UINTN CharCount;
UINTN StacksSize;
FIRMWARE_SEC_PERFORMANCE Performance;
// If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
ASSERT (IS_XIP() ||
((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));
ASSERT (
IS_XIP () ||
((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd))
);
// Initialize the architecture specific bits
ArchInitialize ();
// Initialize the Serial Port
SerialPortInitialize ();
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",
(CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
CharCount = AsciiSPrint (
Buffer,
sizeof (Buffer),
"UEFI firmware (version %s built at %a on %a)\n\r",
(CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
__TIME__,
__DATE__
);
SerialPortWrite ((UINT8 *)Buffer, CharCount);
// Initialize the Debug Agent for Source Level Debugging
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
@@ -89,11 +97,11 @@ PrePiMain (
// Declare the PI/UEFI memory region
HobList = HobConstructor (
(VOID*)UefiMemoryBase,
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
(VOID*)UefiMemoryBase,
(VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks
);
(VOID *)UefiMemoryBase,
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
(VOID *)UefiMemoryBase,
(VOID *)StacksBase // The top of the UEFI Memory is reserved for the stacks
);
PrePeiSetHobList (HobList);
// Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
@@ -107,22 +115,23 @@ PrePiMain (
} else {
StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
}
BuildStackHob (StacksBase, StacksSize);
//TODO: Call CpuPei as a library
// TODO: Call CpuPei as a library
BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
if (ArmIsMpCore ()) {
// Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
// On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
ASSERT_EFI_ERROR (Status);
// Build the MP Core Info Table
ArmCoreCount = 0;
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {
// Build MPCore Info HOB
BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
}
@@ -158,12 +167,12 @@ PrePiMain (
VOID
CEntryPoint (
IN UINTN MpId,
IN UINTN UefiMemoryBase,
IN UINTN StacksBase
IN UINTN MpId,
IN UINTN UefiMemoryBase,
IN UINTN StacksBase
)
{
UINT64 StartTimeStamp;
UINT64 StartTimeStamp;
// Initialize the platform specific controllers
ArmPlatformInitialize (MpId);
@@ -185,9 +194,9 @@ CEntryPoint (
ArmEnableInstructionCache ();
// Define the Global Variable region when we are not running in XIP
if (!IS_XIP()) {
if (!IS_XIP ()) {
if (ArmPlatformIsPrimaryCore (MpId)) {
if (ArmIsMpCore()) {
if (ArmIsMpCore ()) {
// Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
ArmCallSEV ();
}
@@ -199,9 +208,10 @@ CEntryPoint (
// If not primary Jump to Secondary Main
if (ArmPlatformIsPrimaryCore (MpId)) {
InvalidateDataCacheRange ((VOID *)UefiMemoryBase,
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
InvalidateDataCacheRange (
(VOID *)UefiMemoryBase,
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
);
// Goto primary Main.
PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);

20
ArmPlatformPkg/PrePi/PrePi.h
View File

@@ -21,7 +21,7 @@
#include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h>
extern UINT64 mSystemMemoryEnd;
extern UINT64 mSystemMemoryEnd;
RETURN_STATUS
EFIAPI
@@ -31,16 +31,16 @@ TimerConstructor (
VOID
PrePiMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
);
EFI_STATUS
EFIAPI
MemoryPeim (
IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
IN UINT64 UefiMemorySize
IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
IN UINT64 UefiMemorySize
);
EFI_STATUS
@@ -51,14 +51,14 @@ PlatformPeim (
VOID
PrimaryMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
);
VOID
SecondaryMain (
IN UINTN MpId
IN UINTN MpId
);
// Either implemented by PrePiLib or by MemoryInitPei