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ArmPlatformPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:53:52 -08:00
committed by mergify[bot]
parent 429309e0c6
commit 40b0b23ed3
47 changed files with 2846 additions and 2662 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1187
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c
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File diff suppressed because it is too large Load Diff

142
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c
View File

@ -21,37 +21,37 @@
// Global variables // Global variables
// //
BOOLEAN mDisplayInitialized = FALSE; BOOLEAN mDisplayInitialized = FALSE;
LCD_INSTANCE mLcdTemplate = { LCD_INSTANCE mLcdTemplate = {
LCD_INSTANCE_SIGNATURE, LCD_INSTANCE_SIGNATURE,
NULL, // Handle NULL, // Handle
{ // ModeInfo { // ModeInfo
0, // Version 0, // Version
0, // HorizontalResolution 0, // HorizontalResolution
0, // VerticalResolution 0, // VerticalResolution
PixelBltOnly, // PixelFormat PixelBltOnly, // PixelFormat
{ 0 }, // PixelInformation { 0 }, // PixelInformation
0, // PixelsPerScanLine 0, // PixelsPerScanLine
}, },
{ {
0, // MaxMode; 0, // MaxMode;
0, // Mode; 0, // Mode;
NULL, // Info; NULL, // Info;
0, // SizeOfInfo; 0, // SizeOfInfo;
0, // FrameBufferBase; 0, // FrameBufferBase;
0 // FrameBufferSize; 0 // FrameBufferSize;
}, },
{ // Gop { // Gop
LcdGraphicsQueryMode, // QueryMode LcdGraphicsQueryMode, // QueryMode
LcdGraphicsSetMode, // SetMode LcdGraphicsSetMode, // SetMode
LcdGraphicsBlt, // Blt LcdGraphicsBlt, // Blt
NULL // *Mode NULL // *Mode
}, },
{ // DevicePath { // DevicePath
{ {
{ {
HARDWARE_DEVICE_PATH, HW_VENDOR_DP, HARDWARE_DEVICE_PATH, HW_VENDOR_DP,
{ {
(UINT8)(sizeof (VENDOR_DEVICE_PATH)), (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
(UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
@ -75,10 +75,10 @@ LCD_INSTANCE mLcdTemplate = {
EFI_STATUS EFI_STATUS
LcdInstanceContructor ( LcdInstanceContructor (
OUT LCD_INSTANCE** NewInstance OUT LCD_INSTANCE **NewInstance
) )
{ {
LCD_INSTANCE* Instance; LCD_INSTANCE *Instance;
Instance = AllocateCopyPool (sizeof (LCD_INSTANCE), &mLcdTemplate); Instance = AllocateCopyPool (sizeof (LCD_INSTANCE), &mLcdTemplate);
if (Instance == NULL) { if (Instance == NULL) {
@ -99,12 +99,12 @@ LcdInstanceContructor (
EFI_STATUS EFI_STATUS
InitializeDisplay ( InitializeDisplay (
IN LCD_INSTANCE* Instance IN LCD_INSTANCE *Instance
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS VramBaseAddress; EFI_PHYSICAL_ADDRESS VramBaseAddress;
UINTN VramSize; UINTN VramSize;
Status = LcdPlatformGetVram (&VramBaseAddress, &VramSize); Status = LcdPlatformGetVram (&VramBaseAddress, &VramSize);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -144,12 +144,12 @@ EXIT:
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LcdGraphicsOutputDxeInitialize ( LcdGraphicsOutputDxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
LCD_INSTANCE* Instance; LCD_INSTANCE *Instance;
Status = LcdIdentify (); Status = LcdIdentify ();
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -240,14 +240,14 @@ LcdGraphicsExitBootServicesEvent (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LcdGraphicsQueryMode ( LcdGraphicsQueryMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber, IN UINT32 ModeNumber,
OUT UINTN *SizeOfInfo, OUT UINTN *SizeOfInfo,
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
LCD_INSTANCE *Instance; LCD_INSTANCE *Instance;
Instance = LCD_INSTANCE_FROM_GOP_THIS (This); Instance = LCD_INSTANCE_FROM_GOP_THIS (This);
@ -263,7 +263,8 @@ LcdGraphicsQueryMode (
if ((This == NULL) || if ((This == NULL) ||
(Info == NULL) || (Info == NULL) ||
(SizeOfInfo == NULL) || (SizeOfInfo == NULL) ||
(ModeNumber >= This->Mode->MaxMode)) { (ModeNumber >= This->Mode->MaxMode))
{
DEBUG ((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d : Invalid Parameter.\n", ModeNumber)); DEBUG ((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d : Invalid Parameter.\n", ModeNumber));
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
goto EXIT; goto EXIT;
@ -292,14 +293,14 @@ EXIT:
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LcdGraphicsSetMode ( LcdGraphicsSetMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber IN UINT32 ModeNumber
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL FillColour; EFI_GRAPHICS_OUTPUT_BLT_PIXEL FillColour;
LCD_INSTANCE* Instance; LCD_INSTANCE *Instance;
LCD_BPP Bpp; LCD_BPP Bpp;
Instance = LCD_INSTANCE_FROM_GOP_THIS (This); Instance = LCD_INSTANCE_FROM_GOP_THIS (This);
@ -333,9 +334,10 @@ LcdGraphicsSetMode (
DEBUG ((DEBUG_ERROR, "LcdGraphicsSetMode: ERROR - Couldn't get bytes per pixel, status: %r\n", Status)); DEBUG ((DEBUG_ERROR, "LcdGraphicsSetMode: ERROR - Couldn't get bytes per pixel, status: %r\n", Status));
goto EXIT; goto EXIT;
} }
This->Mode->FrameBufferSize = Instance->ModeInfo.VerticalResolution This->Mode->FrameBufferSize = Instance->ModeInfo.VerticalResolution
* Instance->ModeInfo.PixelsPerScanLine * Instance->ModeInfo.PixelsPerScanLine
* GetBytesPerPixel (Bpp); * GetBytesPerPixel (Bpp);
// Set the hardware to the new mode // Set the hardware to the new mode
Status = LcdSetMode (ModeNumber); Status = LcdSetMode (ModeNumber);
@ -352,17 +354,17 @@ LcdGraphicsSetMode (
// Fill the entire visible area with the same colour. // Fill the entire visible area with the same colour.
Status = This->Blt ( Status = This->Blt (
This, This,
&FillColour, &FillColour,
EfiBltVideoFill, EfiBltVideoFill,
0, 0,
0, 0,
0, 0,
0, 0,
This->Mode->Info->HorizontalResolution, This->Mode->Info->HorizontalResolution,
This->Mode->Info->VerticalResolution, This->Mode->Info->VerticalResolution,
0 0
); );
EXIT: EXIT:
return Status; return Status;
@ -370,25 +372,25 @@ EXIT:
UINTN UINTN
GetBytesPerPixel ( GetBytesPerPixel (
IN LCD_BPP Bpp IN LCD_BPP Bpp
) )
{ {
switch (Bpp) { switch (Bpp) {
case LcdBitsPerPixel_24: case LcdBitsPerPixel_24:
return 4; return 4;
case LcdBitsPerPixel_16_565: case LcdBitsPerPixel_16_565:
case LcdBitsPerPixel_16_555: case LcdBitsPerPixel_16_555:
case LcdBitsPerPixel_12_444: case LcdBitsPerPixel_12_444:
return 2; return 2;
case LcdBitsPerPixel_8: case LcdBitsPerPixel_8:
case LcdBitsPerPixel_4: case LcdBitsPerPixel_4:
case LcdBitsPerPixel_2: case LcdBitsPerPixel_2:
case LcdBitsPerPixel_1: case LcdBitsPerPixel_1:
return 1; return 1;
default: default:
return 0; return 0;
} }
} }

44
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h
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@ -22,23 +22,23 @@
// Device structures // Device structures
// //
typedef struct { typedef struct {
VENDOR_DEVICE_PATH Guid; VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End; EFI_DEVICE_PATH_PROTOCOL End;
} LCD_GRAPHICS_DEVICE_PATH; } LCD_GRAPHICS_DEVICE_PATH;
typedef struct { typedef struct {
UINT32 Signature; UINT32 Signature;
EFI_HANDLE Handle; EFI_HANDLE Handle;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;
EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE Mode; EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE Mode;
EFI_GRAPHICS_OUTPUT_PROTOCOL Gop; EFI_GRAPHICS_OUTPUT_PROTOCOL Gop;
LCD_GRAPHICS_DEVICE_PATH DevicePath; LCD_GRAPHICS_DEVICE_PATH DevicePath;
EFI_EVENT ExitBootServicesEvent; EFI_EVENT ExitBootServicesEvent;
} LCD_INSTANCE; } LCD_INSTANCE;
#define LCD_INSTANCE_SIGNATURE SIGNATURE_32('l', 'c', 'd', '0') #define LCD_INSTANCE_SIGNATURE SIGNATURE_32('l', 'c', 'd', '0')
#define LCD_INSTANCE_FROM_GOP_THIS(a) CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE) #define LCD_INSTANCE_FROM_GOP_THIS(a) CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE)
// //
// Function Prototypes // Function Prototypes
@ -46,9 +46,9 @@ typedef struct {
VOID VOID
LcdGraphicsExitBootServicesEvent ( LcdGraphicsExitBootServicesEvent (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
@ -57,14 +57,14 @@ LcdGraphicsQueryMode (
IN UINT32 ModeNumber, IN UINT32 ModeNumber,
OUT UINTN *SizeOfInfo, OUT UINTN *SizeOfInfo,
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LcdGraphicsSetMode ( LcdGraphicsSetMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber IN UINT32 ModeNumber
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
@ -79,23 +79,23 @@ LcdGraphicsBlt (
IN UINTN Width, IN UINTN Width,
IN UINTN Height, IN UINTN Height,
IN UINTN Delta OPTIONAL IN UINTN Delta OPTIONAL
); );
UINTN UINTN
GetBytesPerPixel ( GetBytesPerPixel (
IN LCD_BPP Bpp IN LCD_BPP Bpp
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GraphicsOutputDxeInitialize ( GraphicsOutputDxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
); );
EFI_STATUS EFI_STATUS
InitializeDisplay ( InitializeDisplay (
IN LCD_INSTANCE* Instance IN LCD_INSTANCE *Instance
); );
#endif /* LCD_GRAPHICS_OUTPUT_DXE_H_ */ #endif /* LCD_GRAPHICS_OUTPUT_DXE_H_ */

392
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlash.c
View File

@ -14,13 +14,13 @@
// //
// Global variable declarations // Global variable declarations
// //
extern NOR_FLASH_INSTANCE **mNorFlashInstances; extern NOR_FLASH_INSTANCE **mNorFlashInstances;
extern UINT32 mNorFlashDeviceCount; extern UINT32 mNorFlashDeviceCount;
UINT32 UINT32
NorFlashReadStatusRegister ( NorFlashReadStatusRegister (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN SR_Address IN UINTN SR_Address
) )
{ {
// Prepare to read the status register // Prepare to read the status register
@ -31,23 +31,23 @@ NorFlashReadStatusRegister (
STATIC STATIC
BOOLEAN BOOLEAN
NorFlashBlockIsLocked ( NorFlashBlockIsLocked (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
) )
{ {
UINT32 LockStatus; UINT32 LockStatus;
// Send command for reading device id // Send command for reading device id
SEND_NOR_COMMAND (BlockAddress, 2, P30_CMD_READ_DEVICE_ID); SEND_NOR_COMMAND (BlockAddress, 2, P30_CMD_READ_DEVICE_ID);
// Read block lock status // Read block lock status
LockStatus = MmioRead32 (CREATE_NOR_ADDRESS(BlockAddress, 2)); LockStatus = MmioRead32 (CREATE_NOR_ADDRESS (BlockAddress, 2));
// Decode block lock status // Decode block lock status
LockStatus = FOLD_32BIT_INTO_16BIT(LockStatus); LockStatus = FOLD_32BIT_INTO_16BIT (LockStatus);
if ((LockStatus & 0x2) != 0) { if ((LockStatus & 0x2) != 0) {
DEBUG((DEBUG_ERROR, "NorFlashBlockIsLocked: WARNING: Block LOCKED DOWN\n")); DEBUG ((DEBUG_ERROR, "NorFlashBlockIsLocked: WARNING: Block LOCKED DOWN\n"));
} }
return ((LockStatus & 0x1) != 0); return ((LockStatus & 0x1) != 0);
@ -56,11 +56,11 @@ NorFlashBlockIsLocked (
STATIC STATIC
EFI_STATUS EFI_STATUS
NorFlashUnlockSingleBlock ( NorFlashUnlockSingleBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
) )
{ {
UINT32 LockStatus; UINT32 LockStatus;
// Raise the Task Priority Level to TPL_NOTIFY to serialise all its operations // Raise the Task Priority Level to TPL_NOTIFY to serialise all its operations
// and to protect shared data structures. // and to protect shared data structures.
@ -77,10 +77,10 @@ NorFlashUnlockSingleBlock (
SEND_NOR_COMMAND (BlockAddress, 2, P30_CMD_READ_DEVICE_ID); SEND_NOR_COMMAND (BlockAddress, 2, P30_CMD_READ_DEVICE_ID);
// Read block lock status // Read block lock status
LockStatus = MmioRead32 (CREATE_NOR_ADDRESS(BlockAddress, 2)); LockStatus = MmioRead32 (CREATE_NOR_ADDRESS (BlockAddress, 2));
// Decode block lock status // Decode block lock status
LockStatus = FOLD_32BIT_INTO_16BIT(LockStatus); LockStatus = FOLD_32BIT_INTO_16BIT (LockStatus);
} while ((LockStatus & 0x1) == 1); } while ((LockStatus & 0x1) == 1);
} else { } else {
// Request a lock setup // Request a lock setup
@ -98,18 +98,18 @@ NorFlashUnlockSingleBlock (
// Put device back into Read Array mode // Put device back into Read Array mode
SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_READ_ARRAY); SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_READ_ARRAY);
DEBUG((DEBUG_BLKIO, "UnlockSingleBlock: BlockAddress=0x%08x\n", BlockAddress)); DEBUG ((DEBUG_BLKIO, "UnlockSingleBlock: BlockAddress=0x%08x\n", BlockAddress));
return EFI_SUCCESS; return EFI_SUCCESS;
} }
EFI_STATUS EFI_STATUS
NorFlashUnlockSingleBlockIfNecessary ( NorFlashUnlockSingleBlockIfNecessary (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@ -120,24 +120,23 @@ NorFlashUnlockSingleBlockIfNecessary (
return Status; return Status;
} }
/** /**
* The following function presumes that the block has already been unlocked. * The following function presumes that the block has already been unlocked.
**/ **/
EFI_STATUS EFI_STATUS
NorFlashEraseSingleBlock ( NorFlashEraseSingleBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 StatusRegister; UINT32 StatusRegister;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
// Request a block erase and then confirm it // Request a block erase and then confirm it
SEND_NOR_COMMAND(BlockAddress, 0, P30_CMD_BLOCK_ERASE_SETUP); SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_BLOCK_ERASE_SETUP);
SEND_NOR_COMMAND(BlockAddress, 0, P30_CMD_BLOCK_ERASE_CONFIRM); SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_BLOCK_ERASE_CONFIRM);
// Wait until the status register gives us the all clear // Wait until the status register gives us the all clear
do { do {
@ -145,27 +144,27 @@ NorFlashEraseSingleBlock (
} while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE); } while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE);
if (StatusRegister & P30_SR_BIT_VPP) { if (StatusRegister & P30_SR_BIT_VPP) {
DEBUG((DEBUG_ERROR,"EraseSingleBlock(BlockAddress=0x%08x: VPP Range Error\n", BlockAddress)); DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: VPP Range Error\n", BlockAddress));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if ((StatusRegister & (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM)) == (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM)) { if ((StatusRegister & (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM)) == (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM)) {
DEBUG((DEBUG_ERROR,"EraseSingleBlock(BlockAddress=0x%08x: Command Sequence Error\n", BlockAddress)); DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Command Sequence Error\n", BlockAddress));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if (StatusRegister & P30_SR_BIT_ERASE) { if (StatusRegister & P30_SR_BIT_ERASE) {
DEBUG((DEBUG_ERROR,"EraseSingleBlock(BlockAddress=0x%08x: Block Erase Error StatusRegister:0x%X\n", BlockAddress, StatusRegister)); DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block Erase Error StatusRegister:0x%X\n", BlockAddress, StatusRegister));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) { if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) {
// The debug level message has been reduced because a device lock might happen. In this case we just retry it ... // The debug level message has been reduced because a device lock might happen. In this case we just retry it ...
DEBUG((DEBUG_INFO,"EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error\n", BlockAddress)); DEBUG ((DEBUG_INFO, "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error\n", BlockAddress));
Status = EFI_WRITE_PROTECTED; Status = EFI_WRITE_PROTECTED;
} }
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
// Clear the Status Register // Clear the Status Register
SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS_REGISTER); SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS_REGISTER);
} }
@ -178,18 +177,18 @@ NorFlashEraseSingleBlock (
EFI_STATUS EFI_STATUS
NorFlashWriteSingleWord ( NorFlashWriteSingleWord (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN WordAddress, IN UINTN WordAddress,
IN UINT32 WriteData IN UINT32 WriteData
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 StatusRegister; UINT32 StatusRegister;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
// Request a write single word command // Request a write single word command
SEND_NOR_COMMAND(WordAddress, 0, P30_CMD_WORD_PROGRAM_SETUP); SEND_NOR_COMMAND (WordAddress, 0, P30_CMD_WORD_PROGRAM_SETUP);
// Store the word into NOR Flash; // Store the word into NOR Flash;
MmioWrite32 (WordAddress, WriteData); MmioWrite32 (WordAddress, WriteData);
@ -201,27 +200,26 @@ NorFlashWriteSingleWord (
// The chip is busy while the WRITE bit is not asserted // The chip is busy while the WRITE bit is not asserted
} while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE); } while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE);
// Perform a full status check: // Perform a full status check:
// Mask the relevant bits of Status Register. // Mask the relevant bits of Status Register.
// Everything should be zero, if not, we have a problem // Everything should be zero, if not, we have a problem
if (StatusRegister & P30_SR_BIT_VPP) { if (StatusRegister & P30_SR_BIT_VPP) {
DEBUG((DEBUG_ERROR,"NorFlashWriteSingleWord(WordAddress:0x%X): VPP Range Error\n",WordAddress)); DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X): VPP Range Error\n", WordAddress));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if (StatusRegister & P30_SR_BIT_PROGRAM) { if (StatusRegister & P30_SR_BIT_PROGRAM) {
DEBUG((DEBUG_ERROR,"NorFlashWriteSingleWord(WordAddress:0x%X): Program Error\n",WordAddress)); DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X): Program Error\n", WordAddress));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) { if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) {
DEBUG((DEBUG_ERROR,"NorFlashWriteSingleWord(WordAddress:0x%X): Device Protect Error\n",WordAddress)); DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X): Device Protect Error\n", WordAddress));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
// Clear the Status Register // Clear the Status Register
SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS_REGISTER); SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS_REGISTER);
} }
@ -249,19 +247,19 @@ NorFlashWriteSingleWord (
*/ */
EFI_STATUS EFI_STATUS
NorFlashWriteBuffer ( NorFlashWriteBuffer (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN TargetAddress, IN UINTN TargetAddress,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
IN UINT32 *Buffer IN UINT32 *Buffer
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN BufferSizeInWords; UINTN BufferSizeInWords;
UINTN Count; UINTN Count;
volatile UINT32 *Data; volatile UINT32 *Data;
UINTN WaitForBuffer; UINTN WaitForBuffer;
BOOLEAN BufferAvailable; BOOLEAN BufferAvailable;
UINT32 StatusRegister; UINT32 StatusRegister;
WaitForBuffer = MAX_BUFFERED_PROG_ITERATIONS; WaitForBuffer = MAX_BUFFERED_PROG_ITERATIONS;
BufferAvailable = FALSE; BufferAvailable = FALSE;
@ -294,7 +292,7 @@ NorFlashWriteBuffer (
// Check the availability of the buffer // Check the availability of the buffer
do { do {
// Issue the Buffered Program Setup command // Issue the Buffered Program Setup command
SEND_NOR_COMMAND(TargetAddress, 0, P30_CMD_BUFFERED_PROGRAM_SETUP); SEND_NOR_COMMAND (TargetAddress, 0, P30_CMD_BUFFERED_PROGRAM_SETUP);
// Read back the status register bit#7 from the same address // Read back the status register bit#7 from the same address
if (((*Data) & P30_SR_BIT_WRITE) == P30_SR_BIT_WRITE) { if (((*Data) & P30_SR_BIT_WRITE) == P30_SR_BIT_WRITE) {
@ -303,7 +301,6 @@ NorFlashWriteBuffer (
// Update the loop counter // Update the loop counter
WaitForBuffer--; WaitForBuffer--;
} while ((WaitForBuffer > 0) && (BufferAvailable == FALSE)); } while ((WaitForBuffer > 0) && (BufferAvailable == FALSE));
// The buffer was not available for writing // The buffer was not available for writing
@ -317,10 +314,10 @@ NorFlashWriteBuffer (
// Write the word count, which is (buffer_size_in_words - 1), // Write the word count, which is (buffer_size_in_words - 1),
// because word count 0 means one word. // because word count 0 means one word.
SEND_NOR_COMMAND(TargetAddress, 0, (BufferSizeInWords - 1)); SEND_NOR_COMMAND (TargetAddress, 0, (BufferSizeInWords - 1));
// Write the data to the NOR Flash, advancing each address by 4 bytes // Write the data to the NOR Flash, advancing each address by 4 bytes
for(Count=0; Count < BufferSizeInWords; Count++, Data++, Buffer++) { for (Count = 0; Count < BufferSizeInWords; Count++, Data++, Buffer++) {
MmioWrite32 ((UINTN)Data, *Buffer); MmioWrite32 ((UINTN)Data, *Buffer);
} }
@ -333,29 +330,28 @@ NorFlashWriteBuffer (
// The chip is busy while the WRITE bit is not asserted // The chip is busy while the WRITE bit is not asserted
} while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE); } while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE);
// Perform a full status check: // Perform a full status check:
// Mask the relevant bits of Status Register. // Mask the relevant bits of Status Register.
// Everything should be zero, if not, we have a problem // Everything should be zero, if not, we have a problem
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
if (StatusRegister & P30_SR_BIT_VPP) { if (StatusRegister & P30_SR_BIT_VPP) {
DEBUG((DEBUG_ERROR,"NorFlashWriteBuffer(TargetAddress:0x%X): VPP Range Error\n", TargetAddress)); DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X): VPP Range Error\n", TargetAddress));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if (StatusRegister & P30_SR_BIT_PROGRAM) { if (StatusRegister & P30_SR_BIT_PROGRAM) {
DEBUG((DEBUG_ERROR,"NorFlashWriteBuffer(TargetAddress:0x%X): Program Error\n", TargetAddress)); DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X): Program Error\n", TargetAddress));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) { if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) {
DEBUG((DEBUG_ERROR,"NorFlashWriteBuffer(TargetAddress:0x%X): Device Protect Error\n",TargetAddress)); DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X): Device Protect Error\n", TargetAddress));
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
// Clear the Status Register // Clear the Status Register
SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS_REGISTER); SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_CLEAR_STATUS_REGISTER);
} }
@ -369,18 +365,18 @@ EXIT:
EFI_STATUS EFI_STATUS
NorFlashWriteBlocks ( NorFlashWriteBlocks (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
IN VOID *Buffer IN VOID *Buffer
) )
{ {
UINT32 *pWriteBuffer; UINT32 *pWriteBuffer;
EFI_STATUS Status; EFI_STATUS Status;
EFI_LBA CurrentBlock; EFI_LBA CurrentBlock;
UINT32 BlockSizeInWords; UINT32 BlockSizeInWords;
UINT32 NumBlocks; UINT32 NumBlocks;
UINT32 BlockCount; UINT32 BlockCount;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@ -389,29 +385,29 @@ NorFlashWriteBlocks (
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if(Instance->Media.ReadOnly == TRUE) { if (Instance->Media.ReadOnly == TRUE) {
return EFI_WRITE_PROTECTED; return EFI_WRITE_PROTECTED;
} }
// We must have some bytes to read // We must have some bytes to read
DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n", BufferSizeInBytes)); DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n", BufferSizeInBytes));
if(BufferSizeInBytes == 0) { if (BufferSizeInBytes == 0) {
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
// The size of the buffer must be a multiple of the block size // The size of the buffer must be a multiple of the block size
DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n", Instance->Media.BlockSize)); DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n", Instance->Media.BlockSize));
if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) { if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) {
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
// All blocks must be within the device // All blocks must be within the device
NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ; NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize;
DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld.\n", NumBlocks, Instance->Media.LastBlock, Lba)); DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld.\n", NumBlocks, Instance->Media.LastBlock, Lba));
if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) { if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) {
DEBUG((DEBUG_ERROR, "NorFlashWriteBlocks: ERROR - Write will exceed last block.\n")); DEBUG ((DEBUG_ERROR, "NorFlashWriteBlocks: ERROR - Write will exceed last block.\n"));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -422,22 +418,21 @@ NorFlashWriteBlocks (
pWriteBuffer = (UINT32 *)Buffer; pWriteBuffer = (UINT32 *)Buffer;
CurrentBlock = Lba; CurrentBlock = Lba;
for (BlockCount=0; BlockCount < NumBlocks; BlockCount++, CurrentBlock++, pWriteBuffer = pWriteBuffer + BlockSizeInWords) { for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++, CurrentBlock++, pWriteBuffer = pWriteBuffer + BlockSizeInWords) {
DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Writing block #%d\n", (UINTN)CurrentBlock));
DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: Writing block #%d\n", (UINTN)CurrentBlock));
Status = NorFlashWriteFullBlock (Instance, CurrentBlock, pWriteBuffer, BlockSizeInWords); Status = NorFlashWriteFullBlock (Instance, CurrentBlock, pWriteBuffer, BlockSizeInWords);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
break; break;
} }
} }
DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: Exit Status = \"%r\".\n", Status)); DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Exit Status = \"%r\".\n", Status));
return Status; return Status;
} }
#define BOTH_ALIGNED(a, b, align) ((((UINTN)(a) | (UINTN)(b)) & ((align) - 1)) == 0) #define BOTH_ALIGNED(a, b, align) ((((UINTN)(a) | (UINTN)(b)) & ((align) - 1)) == 0)
/** /**
Copy Length bytes from Source to Destination, using aligned accesses only. Copy Length bytes from Source to Destination, using aligned accesses only.
@ -454,61 +449,69 @@ NorFlashWriteBlocks (
STATIC STATIC
VOID * VOID *
AlignedCopyMem ( AlignedCopyMem (
OUT VOID *DestinationBuffer, OUT VOID *DestinationBuffer,
IN CONST VOID *SourceBuffer, IN CONST VOID *SourceBuffer,
IN UINTN Length IN UINTN Length
) )
{ {
UINT8 *Destination8; UINT8 *Destination8;
CONST UINT8 *Source8; CONST UINT8 *Source8;
UINT32 *Destination32; UINT32 *Destination32;
CONST UINT32 *Source32; CONST UINT32 *Source32;
UINT64 *Destination64; UINT64 *Destination64;
CONST UINT64 *Source64; CONST UINT64 *Source64;
if (BOTH_ALIGNED(DestinationBuffer, SourceBuffer, 8) && Length >= 8) { if (BOTH_ALIGNED (DestinationBuffer, SourceBuffer, 8) && (Length >= 8)) {
Destination64 = DestinationBuffer; Destination64 = DestinationBuffer;
Source64 = SourceBuffer; Source64 = SourceBuffer;
while (Length >= 8) { while (Length >= 8) {
*Destination64++ = *Source64++; *Destination64++ = *Source64++;
Length -= 8; Length -= 8;
} }
Destination8 = (UINT8 *)Destination64; Destination8 = (UINT8 *)Destination64;
Source8 = (CONST UINT8 *)Source64; Source8 = (CONST UINT8 *)Source64;
} else if (BOTH_ALIGNED(DestinationBuffer, SourceBuffer, 4) && Length >= 4) { } else if (BOTH_ALIGNED (DestinationBuffer, SourceBuffer, 4) && (Length >= 4)) {
Destination32 = DestinationBuffer; Destination32 = DestinationBuffer;
Source32 = SourceBuffer; Source32 = SourceBuffer;
while (Length >= 4) { while (Length >= 4) {
*Destination32++ = *Source32++; *Destination32++ = *Source32++;
Length -= 4; Length -= 4;
} }
Destination8 = (UINT8 *)Destination32; Destination8 = (UINT8 *)Destination32;
Source8 = (CONST UINT8 *)Source32; Source8 = (CONST UINT8 *)Source32;
} else { } else {
Destination8 = DestinationBuffer; Destination8 = DestinationBuffer;
Source8 = SourceBuffer; Source8 = SourceBuffer;
} }
while (Length-- != 0) { while (Length-- != 0) {
*Destination8++ = *Source8++; *Destination8++ = *Source8++;
} }
return DestinationBuffer; return DestinationBuffer;
} }
EFI_STATUS EFI_STATUS
NorFlashReadBlocks ( NorFlashReadBlocks (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
OUT VOID *Buffer OUT VOID *Buffer
) )
{ {
UINT32 NumBlocks; UINT32 NumBlocks;
UINTN StartAddress; UINTN StartAddress;
DEBUG((DEBUG_BLKIO, "NorFlashReadBlocks: BufferSize=0x%xB BlockSize=0x%xB LastBlock=%ld, Lba=%ld.\n", DEBUG ((
BufferSizeInBytes, Instance->Media.BlockSize, Instance->Media.LastBlock, Lba)); DEBUG_BLKIO,
"NorFlashReadBlocks: BufferSize=0x%xB BlockSize=0x%xB LastBlock=%ld, Lba=%ld.\n",
BufferSizeInBytes,
Instance->Media.BlockSize,
Instance->Media.LastBlock,
Lba
));
// The buffer must be valid // The buffer must be valid
if (Buffer == NULL) { if (Buffer == NULL) {
@ -526,18 +529,19 @@ NorFlashReadBlocks (
} }
// All blocks must be within the device // All blocks must be within the device
NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ; NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize;
if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) { if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) {
DEBUG((DEBUG_ERROR, "NorFlashReadBlocks: ERROR - Read will exceed last block\n")); DEBUG ((DEBUG_ERROR, "NorFlashReadBlocks: ERROR - Read will exceed last block\n"));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
// Get the address to start reading from // Get the address to start reading from
StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, StartAddress = GET_NOR_BLOCK_ADDRESS (
Lba, Instance->RegionBaseAddress,
Instance->Media.BlockSize Lba,
); Instance->Media.BlockSize
);
// Put the device into Read Array mode // Put the device into Read Array mode
SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY);
@ -550,11 +554,11 @@ NorFlashReadBlocks (
EFI_STATUS EFI_STATUS
NorFlashRead ( NorFlashRead (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
OUT VOID *Buffer OUT VOID *Buffer
) )
{ {
UINTN StartAddress; UINTN StartAddress;
@ -575,10 +579,11 @@ NorFlashRead (
} }
// Get the address to start reading from // Get the address to start reading from
StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, StartAddress = GET_NOR_BLOCK_ADDRESS (
Lba, Instance->RegionBaseAddress,
Instance->Media.BlockSize Lba,
); Instance->Media.BlockSize
);
// Put the device into Read Array mode // Put the device into Read Array mode
SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY);
@ -595,11 +600,11 @@ NorFlashRead (
*/ */
EFI_STATUS EFI_STATUS
NorFlashWriteSingleBlock ( NorFlashWriteSingleBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN OUT UINTN *NumBytes, IN OUT UINTN *NumBytes,
IN UINT8 *Buffer IN UINT8 *Buffer
) )
{ {
EFI_STATUS TempStatus; EFI_STATUS TempStatus;
@ -631,16 +636,17 @@ NorFlashWriteSingleBlock (
// The write must not span block boundaries. // The write must not span block boundaries.
// We need to check each variable individually because adding two large values together overflows. // We need to check each variable individually because adding two large values together overflows.
if ( ( Offset >= BlockSize ) || if ((Offset >= BlockSize) ||
( *NumBytes > BlockSize ) || (*NumBytes > BlockSize) ||
( (Offset + *NumBytes) > BlockSize ) ) { ((Offset + *NumBytes) > BlockSize))
DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize )); {
DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize));
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
// We must have some bytes to write // We must have some bytes to write
if (*NumBytes == 0) { if (*NumBytes == 0) {
DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize )); DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize));
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
@ -659,16 +665,19 @@ NorFlashWriteSingleBlock (
while (BytesToWrite > 0) { while (BytesToWrite > 0) {
// Read full word from NOR, splice as required. A word is the smallest // Read full word from NOR, splice as required. A word is the smallest
// unit we can write. // unit we can write.
TempStatus = NorFlashRead (Instance, Lba, CurOffset & ~(0x3), sizeof(Tmp), &Tmp); TempStatus = NorFlashRead (Instance, Lba, CurOffset & ~(0x3), sizeof (Tmp), &Tmp);
if (EFI_ERROR (TempStatus)) { if (EFI_ERROR (TempStatus)) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
// Physical address of word in NOR to write. // Physical address of word in NOR to write.
WordAddr = (CurOffset & ~(0x3)) + GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, WordAddr = (CurOffset & ~(0x3)) + GET_NOR_BLOCK_ADDRESS (
Lba, BlockSize); Instance->RegionBaseAddress,
Lba,
BlockSize
);
// The word of data that is to be written. // The word of data that is to be written.
TmpBuf = *((UINT32*)(Buffer + (*NumBytes - BytesToWrite))); TmpBuf = *((UINT32 *)(Buffer + (*NumBytes - BytesToWrite)));
// First do word aligned chunks. // First do word aligned chunks.
if ((CurOffset & 0x3) == 0) { if ((CurOffset & 0x3) == 0) {
@ -681,10 +690,11 @@ NorFlashWriteSingleBlock (
break; break;
} }
} }
// Write this word to NOR // Write this word to NOR
WordToWrite = TmpBuf; WordToWrite = TmpBuf;
CurOffset += sizeof(TmpBuf); CurOffset += sizeof (TmpBuf);
BytesToWrite -= sizeof(TmpBuf); BytesToWrite -= sizeof (TmpBuf);
} else { } else {
// BytesToWrite < 4. Do small writes and left-overs // BytesToWrite < 4. Do small writes and left-overs
Mask = ~((~0) << (BytesToWrite * 8)); Mask = ~((~0) << (BytesToWrite * 8));
@ -698,9 +708,10 @@ NorFlashWriteSingleBlock (
break; break;
} }
} }
// Merge old and new data. Write merged word to NOR // Merge old and new data. Write merged word to NOR
WordToWrite = (Tmp & ~Mask) | TmpBuf; WordToWrite = (Tmp & ~Mask) | TmpBuf;
CurOffset += BytesToWrite; CurOffset += BytesToWrite;
BytesToWrite = 0; BytesToWrite = 0;
} }
} else { } else {
@ -717,10 +728,11 @@ NorFlashWriteSingleBlock (
break; break;
} }
} }
// Merge old and new data. Write merged word to NOR // Merge old and new data. Write merged word to NOR
WordToWrite = (Tmp & ~Mask) | TmpBuf; WordToWrite = (Tmp & ~Mask) | TmpBuf;
BytesToWrite -= (4 - (CurOffset & 0x3)); BytesToWrite -= (4 - (CurOffset & 0x3));
CurOffset += (4 - (CurOffset & 0x3)); CurOffset += (4 - (CurOffset & 0x3));
} else { } else {
// Unaligned and fits in one word. // Unaligned and fits in one word.
Mask = (~((~0) << (BytesToWrite * 8))) << ((CurOffset & 0x3) * 8); Mask = (~((~0) << (BytesToWrite * 8))) << ((CurOffset & 0x3) * 8);
@ -734,9 +746,10 @@ NorFlashWriteSingleBlock (
break; break;
} }
} }
// Merge old and new data. Write merged word to NOR // Merge old and new data. Write merged word to NOR
WordToWrite = (Tmp & ~Mask) | TmpBuf; WordToWrite = (Tmp & ~Mask) | TmpBuf;
CurOffset += BytesToWrite; CurOffset += BytesToWrite;
BytesToWrite = 0; BytesToWrite = 0;
} }
} }
@ -751,13 +764,16 @@ NorFlashWriteSingleBlock (
if (EFI_ERROR (TempStatus)) { if (EFI_ERROR (TempStatus)) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
PrevBlockAddress = BlockAddress; PrevBlockAddress = BlockAddress;
} }
TempStatus = NorFlashWriteSingleWord (Instance, WordAddr, WordToWrite); TempStatus = NorFlashWriteSingleWord (Instance, WordAddr, WordToWrite);
if (EFI_ERROR (TempStatus)) { if (EFI_ERROR (TempStatus)) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
} }
// Exit if we got here and could write all the data. Otherwise do the // Exit if we got here and could write all the data. Otherwise do the
// Erase-Write cycle. // Erase-Write cycle.
if (!DoErase) { if (!DoErase) {
@ -779,7 +795,7 @@ NorFlashWriteSingleBlock (
} }
// Put the data at the appropriate location inside the buffer area // Put the data at the appropriate location inside the buffer area
CopyMem ((VOID*)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes); CopyMem ((VOID *)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes);
// Write the modified buffer back to the NorFlash // Write the modified buffer back to the NorFlash
TempStatus = NorFlashWriteBlocks (Instance, Lba, BlockSize, Instance->ShadowBuffer); TempStatus = NorFlashWriteBlocks (Instance, Lba, BlockSize, Instance->ShadowBuffer);
@ -819,26 +835,26 @@ NorFlashWriteSingleBlock (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashDiskIoReadDisk ( NorFlashDiskIoReadDisk (
IN EFI_DISK_IO_PROTOCOL *This, IN EFI_DISK_IO_PROTOCOL *This,
IN UINT32 MediaId, IN UINT32 MediaId,
IN UINT64 DiskOffset, IN UINT64 DiskOffset,
IN UINTN BufferSize, IN UINTN BufferSize,
OUT VOID *Buffer OUT VOID *Buffer
) )
{ {
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
UINT32 BlockSize; UINT32 BlockSize;
UINT32 BlockOffset; UINT32 BlockOffset;
EFI_LBA Lba; EFI_LBA Lba;
Instance = INSTANCE_FROM_DISKIO_THIS(This); Instance = INSTANCE_FROM_DISKIO_THIS (This);
if (MediaId != Instance->Media.MediaId) { if (MediaId != Instance->Media.MediaId) {
return EFI_MEDIA_CHANGED; return EFI_MEDIA_CHANGED;
} }
BlockSize = Instance->Media.BlockSize; BlockSize = Instance->Media.BlockSize;
Lba = (EFI_LBA) DivU64x32Remainder (DiskOffset, BlockSize, &BlockOffset); Lba = (EFI_LBA)DivU64x32Remainder (DiskOffset, BlockSize, &BlockOffset);
return NorFlashRead (Instance, Lba, BlockOffset, BufferSize, Buffer); return NorFlashRead (Instance, Lba, BlockOffset, BufferSize, Buffer);
} }
@ -864,14 +880,14 @@ NorFlashDiskIoReadDisk (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashDiskIoWriteDisk ( NorFlashDiskIoWriteDisk (
IN EFI_DISK_IO_PROTOCOL *This, IN EFI_DISK_IO_PROTOCOL *This,
IN UINT32 MediaId, IN UINT32 MediaId,
IN UINT64 DiskOffset, IN UINT64 DiskOffset,
IN UINTN BufferSize, IN UINTN BufferSize,
IN VOID *Buffer IN VOID *Buffer
) )
{ {
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
UINT32 BlockSize; UINT32 BlockSize;
UINT32 BlockOffset; UINT32 BlockOffset;
EFI_LBA Lba; EFI_LBA Lba;
@ -879,14 +895,14 @@ NorFlashDiskIoWriteDisk (
UINTN WriteSize; UINTN WriteSize;
EFI_STATUS Status; EFI_STATUS Status;
Instance = INSTANCE_FROM_DISKIO_THIS(This); Instance = INSTANCE_FROM_DISKIO_THIS (This);
if (MediaId != Instance->Media.MediaId) { if (MediaId != Instance->Media.MediaId) {
return EFI_MEDIA_CHANGED; return EFI_MEDIA_CHANGED;
} }
BlockSize = Instance->Media.BlockSize; BlockSize = Instance->Media.BlockSize;
Lba = (EFI_LBA) DivU64x32Remainder (DiskOffset, BlockSize, &BlockOffset); Lba = (EFI_LBA)DivU64x32Remainder (DiskOffset, BlockSize, &BlockOffset);
RemainingBytes = BufferSize; RemainingBytes = BufferSize;
@ -904,15 +920,17 @@ NorFlashDiskIoWriteDisk (
// Write a partial block // Write a partial block
Status = NorFlashWriteSingleBlock (Instance, Lba, BlockOffset, &WriteSize, Buffer); Status = NorFlashWriteSingleBlock (Instance, Lba, BlockOffset, &WriteSize, Buffer);
} }
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// Now continue writing either all the remaining bytes or single blocks. // Now continue writing either all the remaining bytes or single blocks.
RemainingBytes -= WriteSize; RemainingBytes -= WriteSize;
Buffer = (UINT8 *) Buffer + WriteSize; Buffer = (UINT8 *)Buffer + WriteSize;
Lba++; Lba++;
BlockOffset = 0; BlockOffset = 0;
WriteSize = MIN (RemainingBytes, BlockSize); WriteSize = MIN (RemainingBytes, BlockSize);
} while (RemainingBytes); } while (RemainingBytes);
return Status; return Status;
@ -920,7 +938,7 @@ NorFlashDiskIoWriteDisk (
EFI_STATUS EFI_STATUS
NorFlashReset ( NorFlashReset (
IN NOR_FLASH_INSTANCE *Instance IN NOR_FLASH_INSTANCE *Instance
) )
{ {
// As there is no specific RESET to perform, ensure that the devices is in the default Read Array mode // As there is no specific RESET to perform, ensure that the devices is in the default Read Array mode
@ -939,33 +957,33 @@ NorFlashReset (
VOID VOID
EFIAPI EFIAPI
NorFlashVirtualNotifyEvent ( NorFlashVirtualNotifyEvent (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
UINTN Index; UINTN Index;
for (Index = 0; Index < mNorFlashDeviceCount; Index++) { for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->DeviceBaseAddress);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->RegionBaseAddress);
// Convert BlockIo protocol // Convert BlockIo protocol
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.FlushBlocks); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->BlockIoProtocol.FlushBlocks);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.ReadBlocks); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->BlockIoProtocol.ReadBlocks);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.Reset); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->BlockIoProtocol.Reset);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.WriteBlocks); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->BlockIoProtocol.WriteBlocks);
// Convert Fvb // Convert Fvb
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtocol.Read);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes);
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->FvbProtocol.Write);
if (mNorFlashInstances[Index]->ShadowBuffer != NULL) { if (mNorFlashInstances[Index]->ShadowBuffer != NULL) {
EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->ShadowBuffer); EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->ShadowBuffer);
} }
} }

364
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlash.h
View File

@ -9,7 +9,6 @@
#ifndef __NOR_FLASH_H__ #ifndef __NOR_FLASH_H__
#define __NOR_FLASH_H__ #define __NOR_FLASH_H__
#include <Base.h> #include <Base.h>
#include <PiDxe.h> #include <PiDxe.h>
@ -25,138 +24,138 @@
#include <Library/UefiLib.h> #include <Library/UefiLib.h>
#include <Library/UefiRuntimeLib.h> #include <Library/UefiRuntimeLib.h>
#define NOR_FLASH_ERASE_RETRY 10 #define NOR_FLASH_ERASE_RETRY 10
// Device access macros // Device access macros
// These are necessary because we use 2 x 16bit parts to make up 32bit data // These are necessary because we use 2 x 16bit parts to make up 32bit data
#define HIGH_16_BITS 0xFFFF0000 #define HIGH_16_BITS 0xFFFF0000
#define LOW_16_BITS 0x0000FFFF #define LOW_16_BITS 0x0000FFFF
#define LOW_8_BITS 0x000000FF #define LOW_8_BITS 0x000000FF
#define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16_BITS ) ) #define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16_BITS ) )
#define GET_LOW_BYTE(value) ( value & LOW_8_BITS ) #define GET_LOW_BYTE(value) ( value & LOW_8_BITS )
#define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) ) #define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) )
// Each command must be sent simultaneously to both chips, // Each command must be sent simultaneously to both chips,
// i.e. at the lower 16 bits AND at the higher 16 bits // i.e. at the lower 16 bits AND at the higher 16 bits
#define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ((BaseAddr) + ((OffsetAddr) << 2)) #define CREATE_NOR_ADDRESS(BaseAddr, OffsetAddr) ((BaseAddr) + ((OffsetAddr) << 2))
#define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd & LOW_16_BITS) ) #define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd & LOW_16_BITS) )
#define SEND_NOR_COMMAND(BaseAddr,Offset,Cmd) MmioWrite32 (CREATE_NOR_ADDRESS(BaseAddr,Offset), CREATE_DUAL_CMD(Cmd)) #define SEND_NOR_COMMAND(BaseAddr, Offset, Cmd) MmioWrite32 (CREATE_NOR_ADDRESS(BaseAddr,Offset), CREATE_DUAL_CMD(Cmd))
#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) ) #define GET_NOR_BLOCK_ADDRESS(BaseAddr, Lba, LbaSize) ( BaseAddr + (UINTN)((Lba) * LbaSize) )
// Status Register Bits // Status Register Bits
#define P30_SR_BIT_WRITE (BIT7 << 16 | BIT7) #define P30_SR_BIT_WRITE (BIT7 << 16 | BIT7)
#define P30_SR_BIT_ERASE_SUSPEND (BIT6 << 16 | BIT6) #define P30_SR_BIT_ERASE_SUSPEND (BIT6 << 16 | BIT6)
#define P30_SR_BIT_ERASE (BIT5 << 16 | BIT5) #define P30_SR_BIT_ERASE (BIT5 << 16 | BIT5)
#define P30_SR_BIT_PROGRAM (BIT4 << 16 | BIT4) #define P30_SR_BIT_PROGRAM (BIT4 << 16 | BIT4)
#define P30_SR_BIT_VPP (BIT3 << 16 | BIT3) #define P30_SR_BIT_VPP (BIT3 << 16 | BIT3)
#define P30_SR_BIT_PROGRAM_SUSPEND (BIT2 << 16 | BIT2) #define P30_SR_BIT_PROGRAM_SUSPEND (BIT2 << 16 | BIT2)
#define P30_SR_BIT_BLOCK_LOCKED (BIT1 << 16 | BIT1) #define P30_SR_BIT_BLOCK_LOCKED (BIT1 << 16 | BIT1)
#define P30_SR_BIT_BEFP (BIT0 << 16 | BIT0) #define P30_SR_BIT_BEFP (BIT0 << 16 | BIT0)
// Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family // Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family
// On chip buffer size for buffered programming operations // On chip buffer size for buffered programming operations
// There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word is 2 bytes. // There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word is 2 bytes.
// Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes // Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes
#define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128) #define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128)
#define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4)) #define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4))
#define MAX_BUFFERED_PROG_ITERATIONS 10000000 #define MAX_BUFFERED_PROG_ITERATIONS 10000000
#define BOUNDARY_OF_32_WORDS 0x7F #define BOUNDARY_OF_32_WORDS 0x7F
// CFI Addresses // CFI Addresses
#define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10 #define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10
#define P30_CFI_ADDR_VENDOR_ID 0x13 #define P30_CFI_ADDR_VENDOR_ID 0x13
// CFI Data // CFI Data
#define CFI_QRY 0x00595251 #define CFI_QRY 0x00595251
// READ Commands // READ Commands
#define P30_CMD_READ_DEVICE_ID 0x0090 #define P30_CMD_READ_DEVICE_ID 0x0090
#define P30_CMD_READ_STATUS_REGISTER 0x0070 #define P30_CMD_READ_STATUS_REGISTER 0x0070
#define P30_CMD_CLEAR_STATUS_REGISTER 0x0050 #define P30_CMD_CLEAR_STATUS_REGISTER 0x0050
#define P30_CMD_READ_ARRAY 0x00FF #define P30_CMD_READ_ARRAY 0x00FF
#define P30_CMD_READ_CFI_QUERY 0x0098 #define P30_CMD_READ_CFI_QUERY 0x0098
// WRITE Commands // WRITE Commands
#define P30_CMD_WORD_PROGRAM_SETUP 0x0040 #define P30_CMD_WORD_PROGRAM_SETUP 0x0040
#define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010 #define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010
#define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8 #define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8
#define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0 #define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0
#define P30_CMD_BEFP_SETUP 0x0080 #define P30_CMD_BEFP_SETUP 0x0080
#define P30_CMD_BEFP_CONFIRM 0x00D0 #define P30_CMD_BEFP_CONFIRM 0x00D0
// ERASE Commands // ERASE Commands
#define P30_CMD_BLOCK_ERASE_SETUP 0x0020 #define P30_CMD_BLOCK_ERASE_SETUP 0x0020
#define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0 #define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0
// SUSPEND Commands // SUSPEND Commands
#define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0 #define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0
#define P30_CMD_SUSPEND_RESUME 0x00D0 #define P30_CMD_SUSPEND_RESUME 0x00D0
// BLOCK LOCKING / UNLOCKING Commands // BLOCK LOCKING / UNLOCKING Commands
#define P30_CMD_LOCK_BLOCK_SETUP 0x0060 #define P30_CMD_LOCK_BLOCK_SETUP 0x0060
#define P30_CMD_LOCK_BLOCK 0x0001 #define P30_CMD_LOCK_BLOCK 0x0001
#define P30_CMD_UNLOCK_BLOCK 0x00D0 #define P30_CMD_UNLOCK_BLOCK 0x00D0
#define P30_CMD_LOCK_DOWN_BLOCK 0x002F #define P30_CMD_LOCK_DOWN_BLOCK 0x002F
// PROTECTION Commands // PROTECTION Commands
#define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0 #define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0
// CONFIGURATION Commands // CONFIGURATION Commands
#define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060 #define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060
#define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003 #define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003
#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0') #define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE) #define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE) #define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
#define INSTANCE_FROM_DISKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, DiskIoProtocol, NOR_FLASH_SIGNATURE) #define INSTANCE_FROM_DISKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, DiskIoProtocol, NOR_FLASH_SIGNATURE)
typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE; typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
#pragma pack (1) #pragma pack (1)
typedef struct { typedef struct {
VENDOR_DEVICE_PATH Vendor; VENDOR_DEVICE_PATH Vendor;
UINT8 Index; UINT8 Index;
EFI_DEVICE_PATH_PROTOCOL End; EFI_DEVICE_PATH_PROTOCOL End;
} NOR_FLASH_DEVICE_PATH; } NOR_FLASH_DEVICE_PATH;
#pragma pack () #pragma pack ()
struct _NOR_FLASH_INSTANCE { struct _NOR_FLASH_INSTANCE {
UINT32 Signature; UINT32 Signature;
EFI_HANDLE Handle; EFI_HANDLE Handle;
UINTN DeviceBaseAddress; UINTN DeviceBaseAddress;
UINTN RegionBaseAddress; UINTN RegionBaseAddress;
UINTN Size; UINTN Size;
EFI_LBA StartLba; EFI_LBA StartLba;
EFI_BLOCK_IO_PROTOCOL BlockIoProtocol; EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
EFI_BLOCK_IO_MEDIA Media; EFI_BLOCK_IO_MEDIA Media;
EFI_DISK_IO_PROTOCOL DiskIoProtocol; EFI_DISK_IO_PROTOCOL DiskIoProtocol;
EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
VOID* ShadowBuffer; VOID *ShadowBuffer;
NOR_FLASH_DEVICE_PATH DevicePath; NOR_FLASH_DEVICE_PATH DevicePath;
}; };
EFI_STATUS EFI_STATUS
NorFlashReadCfiData ( NorFlashReadCfiData (
IN UINTN DeviceBaseAddress, IN UINTN DeviceBaseAddress,
IN UINTN CFI_Offset, IN UINTN CFI_Offset,
IN UINT32 NumberOfBytes, IN UINT32 NumberOfBytes,
OUT UINT32 *Data OUT UINT32 *Data
); );
EFI_STATUS EFI_STATUS
NorFlashWriteBuffer ( NorFlashWriteBuffer (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN TargetAddress, IN UINTN TargetAddress,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
IN UINT32 *Buffer IN UINT32 *Buffer
); );
// //
@ -165,8 +164,8 @@ NorFlashWriteBuffer (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashBlockIoReset ( NorFlashBlockIoReset (
IN EFI_BLOCK_IO_PROTOCOL *This, IN EFI_BLOCK_IO_PROTOCOL *This,
IN BOOLEAN ExtendedVerification IN BOOLEAN ExtendedVerification
); );
// //
@ -175,12 +174,12 @@ NorFlashBlockIoReset (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashBlockIoReadBlocks ( NorFlashBlockIoReadBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This, IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId, IN UINT32 MediaId,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
OUT VOID *Buffer OUT VOID *Buffer
); );
// //
// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
@ -188,12 +187,12 @@ NorFlashBlockIoReadBlocks (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashBlockIoWriteBlocks ( NorFlashBlockIoWriteBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This, IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId, IN UINT32 MediaId,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
IN VOID *Buffer IN VOID *Buffer
); );
// //
// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
@ -201,8 +200,8 @@ NorFlashBlockIoWriteBlocks (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashBlockIoFlushBlocks ( NorFlashBlockIoFlushBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This IN EFI_BLOCK_IO_PROTOCOL *This
); );
// //
// DiskIO Protocol function EFI_DISK_IO_PROTOCOL.ReadDisk // DiskIO Protocol function EFI_DISK_IO_PROTOCOL.ReadDisk
@ -210,11 +209,11 @@ NorFlashBlockIoFlushBlocks (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashDiskIoReadDisk ( NorFlashDiskIoReadDisk (
IN EFI_DISK_IO_PROTOCOL *This, IN EFI_DISK_IO_PROTOCOL *This,
IN UINT32 MediaId, IN UINT32 MediaId,
IN UINT64 Offset, IN UINT64 Offset,
IN UINTN BufferSize, IN UINTN BufferSize,
OUT VOID *Buffer OUT VOID *Buffer
); );
// //
@ -223,11 +222,11 @@ NorFlashDiskIoReadDisk (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashDiskIoWriteDisk ( NorFlashDiskIoWriteDisk (
IN EFI_DISK_IO_PROTOCOL *This, IN EFI_DISK_IO_PROTOCOL *This,
IN UINT32 MediaId, IN UINT32 MediaId,
IN UINT64 Offset, IN UINT64 Offset,
IN UINTN BufferSize, IN UINTN BufferSize,
IN VOID *Buffer IN VOID *Buffer
); );
// //
@ -236,76 +235,76 @@ NorFlashDiskIoWriteDisk (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbGetAttributes( FvbGetAttributes (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
OUT EFI_FVB_ATTRIBUTES_2 *Attributes OUT EFI_FVB_ATTRIBUTES_2 *Attributes
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbSetAttributes( FvbSetAttributes (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbGetPhysicalAddress( FvbGetPhysicalAddress (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
OUT EFI_PHYSICAL_ADDRESS *Address OUT EFI_PHYSICAL_ADDRESS *Address
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbGetBlockSize( FvbGetBlockSize (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
IN EFI_LBA Lba, IN EFI_LBA Lba,
OUT UINTN *BlockSize, OUT UINTN *BlockSize,
OUT UINTN *NumberOfBlocks OUT UINTN *NumberOfBlocks
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbRead( FvbRead (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN OUT UINTN *NumBytes, IN OUT UINTN *NumBytes,
IN OUT UINT8 *Buffer IN OUT UINT8 *Buffer
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbWrite( FvbWrite (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN OUT UINTN *NumBytes, IN OUT UINTN *NumBytes,
IN UINT8 *Buffer IN UINT8 *Buffer
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbEraseBlocks( FvbEraseBlocks (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
... ...
); );
EFI_STATUS EFI_STATUS
ValidateFvHeader ( ValidateFvHeader (
IN NOR_FLASH_INSTANCE *Instance IN NOR_FLASH_INSTANCE *Instance
); );
EFI_STATUS EFI_STATUS
InitializeFvAndVariableStoreHeaders ( InitializeFvAndVariableStoreHeaders (
IN NOR_FLASH_INSTANCE *Instance IN NOR_FLASH_INSTANCE *Instance
); );
VOID VOID
EFIAPI EFIAPI
FvbVirtualNotifyEvent ( FvbVirtualNotifyEvent (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
); );
// //
@ -314,111 +313,110 @@ FvbVirtualNotifyEvent (
EFI_STATUS EFI_STATUS
NorFlashWriteFullBlock ( NorFlashWriteFullBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINT32 *DataBuffer, IN UINT32 *DataBuffer,
IN UINT32 BlockSizeInWords IN UINT32 BlockSizeInWords
); );
EFI_STATUS EFI_STATUS
NorFlashUnlockAndEraseSingleBlock ( NorFlashUnlockAndEraseSingleBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
); );
EFI_STATUS EFI_STATUS
NorFlashCreateInstance ( NorFlashCreateInstance (
IN UINTN NorFlashDeviceBase, IN UINTN NorFlashDeviceBase,
IN UINTN NorFlashRegionBase, IN UINTN NorFlashRegionBase,
IN UINTN NorFlashSize, IN UINTN NorFlashSize,
IN UINT32 Index, IN UINT32 Index,
IN UINT32 BlockSize, IN UINT32 BlockSize,
IN BOOLEAN SupportFvb, IN BOOLEAN SupportFvb,
OUT NOR_FLASH_INSTANCE** NorFlashInstance OUT NOR_FLASH_INSTANCE **NorFlashInstance
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashFvbInitialize ( NorFlashFvbInitialize (
IN NOR_FLASH_INSTANCE* Instance IN NOR_FLASH_INSTANCE *Instance
); );
// //
// NorFlash.c // NorFlash.c
// //
EFI_STATUS EFI_STATUS
NorFlashWriteSingleBlock ( NorFlashWriteSingleBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN OUT UINTN *NumBytes, IN OUT UINTN *NumBytes,
IN UINT8 *Buffer IN UINT8 *Buffer
); );
EFI_STATUS EFI_STATUS
NorFlashWriteBlocks ( NorFlashWriteBlocks (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
IN VOID *Buffer IN VOID *Buffer
); );
EFI_STATUS EFI_STATUS
NorFlashReadBlocks ( NorFlashReadBlocks (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
OUT VOID *Buffer OUT VOID *Buffer
); );
EFI_STATUS EFI_STATUS
NorFlashRead ( NorFlashRead (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
OUT VOID *Buffer OUT VOID *Buffer
); );
EFI_STATUS EFI_STATUS
NorFlashWrite ( NorFlashWrite (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN OUT UINTN *NumBytes, IN OUT UINTN *NumBytes,
IN UINT8 *Buffer IN UINT8 *Buffer
); );
EFI_STATUS EFI_STATUS
NorFlashReset ( NorFlashReset (
IN NOR_FLASH_INSTANCE *Instance IN NOR_FLASH_INSTANCE *Instance
); );
EFI_STATUS EFI_STATUS
NorFlashEraseSingleBlock ( NorFlashEraseSingleBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
); );
EFI_STATUS EFI_STATUS
NorFlashUnlockSingleBlockIfNecessary ( NorFlashUnlockSingleBlockIfNecessary (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
); );
EFI_STATUS EFI_STATUS
NorFlashWriteSingleWord ( NorFlashWriteSingleWord (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN WordAddress, IN UINTN WordAddress,
IN UINT32 WriteData IN UINT32 WriteData
); );
VOID VOID
EFIAPI EFIAPI
NorFlashVirtualNotifyEvent ( NorFlashVirtualNotifyEvent (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
); );
#endif /* __NOR_FLASH_H__ */ #endif /* __NOR_FLASH_H__ */

38
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
View File

@ -21,9 +21,9 @@ NorFlashBlockIoReset (
IN BOOLEAN ExtendedVerification IN BOOLEAN ExtendedVerification
) )
{ {
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
Instance = INSTANCE_FROM_BLKIO_THIS(This); Instance = INSTANCE_FROM_BLKIO_THIS (This);
DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReset(MediaId=0x%x)\n", This->Media->MediaId)); DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReset(MediaId=0x%x)\n", This->Media->MediaId));
@ -36,11 +36,11 @@ NorFlashBlockIoReset (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashBlockIoReadBlocks ( NorFlashBlockIoReadBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This, IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId, IN UINT32 MediaId,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
OUT VOID *Buffer OUT VOID *Buffer
) )
{ {
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
@ -51,8 +51,8 @@ NorFlashBlockIoReadBlocks (
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
Instance = INSTANCE_FROM_BLKIO_THIS(This); Instance = INSTANCE_FROM_BLKIO_THIS (This);
Media = This->Media; Media = This->Media;
DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer)); DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
@ -77,28 +77,28 @@ NorFlashBlockIoReadBlocks (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashBlockIoWriteBlocks ( NorFlashBlockIoWriteBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This, IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId, IN UINT32 MediaId,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN BufferSizeInBytes, IN UINTN BufferSizeInBytes,
IN VOID *Buffer IN VOID *Buffer
) )
{ {
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
EFI_STATUS Status; EFI_STATUS Status;
Instance = INSTANCE_FROM_BLKIO_THIS(This); Instance = INSTANCE_FROM_BLKIO_THIS (This);
DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer)); DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
if( !This->Media->MediaPresent ) { if ( !This->Media->MediaPresent ) {
Status = EFI_NO_MEDIA; Status = EFI_NO_MEDIA;
} else if( This->Media->MediaId != MediaId ) { } else if ( This->Media->MediaId != MediaId ) {
Status = EFI_MEDIA_CHANGED; Status = EFI_MEDIA_CHANGED;
} else if( This->Media->ReadOnly ) { } else if ( This->Media->ReadOnly ) {
Status = EFI_WRITE_PROTECTED; Status = EFI_WRITE_PROTECTED;
} else { } else {
Status = NorFlashWriteBlocks (Instance,Lba,BufferSizeInBytes,Buffer); Status = NorFlashWriteBlocks (Instance, Lba, BufferSizeInBytes, Buffer);
} }
return Status; return Status;

305
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c
View File

@ -16,19 +16,19 @@
#include "NorFlash.h" #include "NorFlash.h"
STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent; STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
// //
// Global variable declarations // Global variable declarations
// //
NOR_FLASH_INSTANCE **mNorFlashInstances; NOR_FLASH_INSTANCE **mNorFlashInstances;
UINT32 mNorFlashDeviceCount; UINT32 mNorFlashDeviceCount;
UINTN mFlashNvStorageVariableBase; UINTN mFlashNvStorageVariableBase;
EFI_EVENT mFvbVirtualAddrChangeEvent; EFI_EVENT mFvbVirtualAddrChangeEvent;
NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = { NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
NOR_FLASH_SIGNATURE, // Signature NOR_FLASH_SIGNATURE, // Signature
NULL, // Handle ... NEED TO BE FILLED NULL, // Handle ... NEED TO BE FILLED
0, // DeviceBaseAddress ... NEED TO BE FILLED 0, // DeviceBaseAddress ... NEED TO BE FILLED
0, // RegionBaseAddress ... NEED TO BE FILLED 0, // RegionBaseAddress ... NEED TO BE FILLED
@ -37,26 +37,26 @@ NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
{ {
EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision
NULL, // Media ... NEED TO BE FILLED NULL, // Media ... NEED TO BE FILLED
NorFlashBlockIoReset, // Reset; NorFlashBlockIoReset, // Reset;
NorFlashBlockIoReadBlocks, // ReadBlocks NorFlashBlockIoReadBlocks, // ReadBlocks
NorFlashBlockIoWriteBlocks, // WriteBlocks NorFlashBlockIoWriteBlocks, // WriteBlocks
NorFlashBlockIoFlushBlocks // FlushBlocks NorFlashBlockIoFlushBlocks // FlushBlocks
}, // BlockIoProtocol }, // BlockIoProtocol
{ {
0, // MediaId ... NEED TO BE FILLED 0, // MediaId ... NEED TO BE FILLED
FALSE, // RemovableMedia FALSE, // RemovableMedia
TRUE, // MediaPresent TRUE, // MediaPresent
FALSE, // LogicalPartition FALSE, // LogicalPartition
FALSE, // ReadOnly FALSE, // ReadOnly
FALSE, // WriteCaching; FALSE, // WriteCaching;
0, // BlockSize ... NEED TO BE FILLED 0, // BlockSize ... NEED TO BE FILLED
4, // IoAlign 4, // IoAlign
0, // LastBlock ... NEED TO BE FILLED 0, // LastBlock ... NEED TO BE FILLED
0, // LowestAlignedLba 0, // LowestAlignedLba
1, // LogicalBlocksPerPhysicalBlock 1, // LogicalBlocksPerPhysicalBlock
}, //Media; }, // Media;
{ {
EFI_DISK_IO_PROTOCOL_REVISION, // Revision EFI_DISK_IO_PROTOCOL_REVISION, // Revision
@ -65,15 +65,15 @@ NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
}, },
{ {
FvbGetAttributes, // GetAttributes FvbGetAttributes, // GetAttributes
FvbSetAttributes, // SetAttributes FvbSetAttributes, // SetAttributes
FvbGetPhysicalAddress, // GetPhysicalAddress FvbGetPhysicalAddress, // GetPhysicalAddress
FvbGetBlockSize, // GetBlockSize FvbGetBlockSize, // GetBlockSize
FvbRead, // Read FvbRead, // Read
FvbWrite, // Write FvbWrite, // Write
FvbEraseBlocks, // EraseBlocks FvbEraseBlocks, // EraseBlocks
NULL, //ParentHandle NULL, // ParentHandle
}, // FvbProtoccol; }, // FvbProtoccol;
NULL, // ShadowBuffer NULL, // ShadowBuffer
{ {
{ {
@ -85,7 +85,8 @@ NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
(UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8) (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8)
} }
}, },
{ 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } }, // GUID ... NEED TO BE FILLED { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
}, // GUID ... NEED TO BE FILLED
}, },
0, // Index 0, // Index
{ {
@ -93,43 +94,43 @@ NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
END_ENTIRE_DEVICE_PATH_SUBTYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
{ sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
} }
} // DevicePath } // DevicePath
}; };
EFI_STATUS EFI_STATUS
NorFlashCreateInstance ( NorFlashCreateInstance (
IN UINTN NorFlashDeviceBase, IN UINTN NorFlashDeviceBase,
IN UINTN NorFlashRegionBase, IN UINTN NorFlashRegionBase,
IN UINTN NorFlashSize, IN UINTN NorFlashSize,
IN UINT32 Index, IN UINT32 Index,
IN UINT32 BlockSize, IN UINT32 BlockSize,
IN BOOLEAN SupportFvb, IN BOOLEAN SupportFvb,
OUT NOR_FLASH_INSTANCE** NorFlashInstance OUT NOR_FLASH_INSTANCE **NorFlashInstance
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
NOR_FLASH_INSTANCE* Instance; NOR_FLASH_INSTANCE *Instance;
ASSERT(NorFlashInstance != NULL); ASSERT (NorFlashInstance != NULL);
Instance = AllocateRuntimeCopyPool (sizeof(NOR_FLASH_INSTANCE),&mNorFlashInstanceTemplate); Instance = AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE), &mNorFlashInstanceTemplate);
if (Instance == NULL) { if (Instance == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
Instance->DeviceBaseAddress = NorFlashDeviceBase; Instance->DeviceBaseAddress = NorFlashDeviceBase;
Instance->RegionBaseAddress = NorFlashRegionBase; Instance->RegionBaseAddress = NorFlashRegionBase;
Instance->Size = NorFlashSize; Instance->Size = NorFlashSize;
Instance->BlockIoProtocol.Media = &Instance->Media; Instance->BlockIoProtocol.Media = &Instance->Media;
Instance->Media.MediaId = Index; Instance->Media.MediaId = Index;
Instance->Media.BlockSize = BlockSize; Instance->Media.BlockSize = BlockSize;
Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1; Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1;
CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid); CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid);
Instance->DevicePath.Index = (UINT8)Index; Instance->DevicePath.Index = (UINT8)Index;
Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);; Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);
if (Instance->ShadowBuffer == NULL) { if (Instance->ShadowBuffer == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
@ -138,25 +139,31 @@ NorFlashCreateInstance (
NorFlashFvbInitialize (Instance); NorFlashFvbInitialize (Instance);
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&Instance->Handle, &Instance->Handle,
&gEfiDevicePathProtocolGuid, &Instance->DevicePath, &gEfiDevicePathProtocolGuid,
&gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol, &Instance->DevicePath,
&gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol, &gEfiBlockIoProtocolGuid,
NULL &Instance->BlockIoProtocol,
); &gEfiFirmwareVolumeBlockProtocolGuid,
if (EFI_ERROR(Status)) { &Instance->FvbProtocol,
NULL
);
if (EFI_ERROR (Status)) {
FreePool (Instance); FreePool (Instance);
return Status; return Status;
} }
} else { } else {
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&Instance->Handle, &Instance->Handle,
&gEfiDevicePathProtocolGuid, &Instance->DevicePath, &gEfiDevicePathProtocolGuid,
&gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol, &Instance->DevicePath,
&gEfiDiskIoProtocolGuid, &Instance->DiskIoProtocol, &gEfiBlockIoProtocolGuid,
&Instance->BlockIoProtocol,
&gEfiDiskIoProtocolGuid,
&Instance->DiskIoProtocol,
NULL NULL
); );
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
FreePool (Instance); FreePool (Instance);
return Status; return Status;
} }
@ -171,13 +178,13 @@ NorFlashCreateInstance (
**/ **/
EFI_STATUS EFI_STATUS
NorFlashUnlockAndEraseSingleBlock ( NorFlashUnlockAndEraseSingleBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
EFI_TPL OriginalTPL; EFI_TPL OriginalTPL;
if (!EfiAtRuntime ()) { if (!EfiAtRuntime ()) {
// Raise TPL to TPL_HIGH to stop anyone from interrupting us. // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
@ -196,12 +203,13 @@ NorFlashUnlockAndEraseSingleBlock (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
break; break;
} }
Status = NorFlashEraseSingleBlock (Instance, BlockAddress); Status = NorFlashEraseSingleBlock (Instance, BlockAddress);
Index++; Index++;
} while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED)); } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED));
if (Index == NOR_FLASH_ERASE_RETRY) { if (Index == NOR_FLASH_ERASE_RETRY) {
DEBUG((DEBUG_ERROR,"EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", BlockAddress,Index)); DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", BlockAddress, Index));
} }
if (!EfiAtRuntime ()) { if (!EfiAtRuntime ()) {
@ -214,21 +222,21 @@ NorFlashUnlockAndEraseSingleBlock (
EFI_STATUS EFI_STATUS
NorFlashWriteFullBlock ( NorFlashWriteFullBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINT32 *DataBuffer, IN UINT32 *DataBuffer,
IN UINT32 BlockSizeInWords IN UINT32 BlockSizeInWords
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN WordAddress; UINTN WordAddress;
UINT32 WordIndex; UINT32 WordIndex;
UINTN BufferIndex; UINTN BufferIndex;
UINTN BlockAddress; UINTN BlockAddress;
UINTN BuffersInBlock; UINTN BuffersInBlock;
UINTN RemainingWords; UINTN RemainingWords;
EFI_TPL OriginalTPL; EFI_TPL OriginalTPL;
UINTN Cnt; UINTN Cnt;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@ -248,8 +256,8 @@ NorFlashWriteFullBlock (
} }
Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR, "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n", BlockAddress)); DEBUG ((DEBUG_ERROR, "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n", BlockAddress));
goto EXIT; goto EXIT;
} }
@ -257,25 +265,30 @@ NorFlashWriteFullBlock (
// Check that the address starts at a 32-word boundary, i.e. last 7 bits must be zero // Check that the address starts at a 32-word boundary, i.e. last 7 bits must be zero
if ((WordAddress & BOUNDARY_OF_32_WORDS) == 0x00) { if ((WordAddress & BOUNDARY_OF_32_WORDS) == 0x00) {
// First, break the entire block into buffer-sized chunks. // First, break the entire block into buffer-sized chunks.
BuffersInBlock = (UINTN)(BlockSizeInWords * 4) / P30_MAX_BUFFER_SIZE_IN_BYTES; BuffersInBlock = (UINTN)(BlockSizeInWords * 4) / P30_MAX_BUFFER_SIZE_IN_BYTES;
// Then feed each buffer chunk to the NOR Flash // Then feed each buffer chunk to the NOR Flash
// If a buffer does not contain any data, don't write it. // If a buffer does not contain any data, don't write it.
for(BufferIndex=0; for (BufferIndex = 0;
BufferIndex < BuffersInBlock; BufferIndex < BuffersInBlock;
BufferIndex++, WordAddress += P30_MAX_BUFFER_SIZE_IN_BYTES, DataBuffer += P30_MAX_BUFFER_SIZE_IN_WORDS BufferIndex++, WordAddress += P30_MAX_BUFFER_SIZE_IN_BYTES, DataBuffer += P30_MAX_BUFFER_SIZE_IN_WORDS
) { )
{
// Check the buffer to see if it contains any data (not set all 1s). // Check the buffer to see if it contains any data (not set all 1s).
for (Cnt = 0; Cnt < P30_MAX_BUFFER_SIZE_IN_WORDS; Cnt++) { for (Cnt = 0; Cnt < P30_MAX_BUFFER_SIZE_IN_WORDS; Cnt++) {
if (~DataBuffer[Cnt] != 0 ) { if (~DataBuffer[Cnt] != 0 ) {
// Some data found, write the buffer. // Some data found, write the buffer.
Status = NorFlashWriteBuffer (Instance, WordAddress, P30_MAX_BUFFER_SIZE_IN_BYTES, Status = NorFlashWriteBuffer (
DataBuffer); Instance,
if (EFI_ERROR(Status)) { WordAddress,
P30_MAX_BUFFER_SIZE_IN_BYTES,
DataBuffer
);
if (EFI_ERROR (Status)) {
goto EXIT; goto EXIT;
} }
break; break;
} }
} }
@ -284,20 +297,19 @@ NorFlashWriteFullBlock (
// Finally, finish off any remaining words that are less than the maximum size of the buffer // Finally, finish off any remaining words that are less than the maximum size of the buffer
RemainingWords = BlockSizeInWords % P30_MAX_BUFFER_SIZE_IN_WORDS; RemainingWords = BlockSizeInWords % P30_MAX_BUFFER_SIZE_IN_WORDS;
if(RemainingWords != 0) { if (RemainingWords != 0) {
Status = NorFlashWriteBuffer (Instance, WordAddress, (RemainingWords * 4), DataBuffer); Status = NorFlashWriteBuffer (Instance, WordAddress, (RemainingWords * 4), DataBuffer);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
goto EXIT; goto EXIT;
} }
} }
} else { } else {
// For now, use the single word programming algorithm // For now, use the single word programming algorithm
// It is unlikely that the NOR Flash will exist in an address which falls within a 32 word boundary range, // It is unlikely that the NOR Flash will exist in an address which falls within a 32 word boundary range,
// i.e. which ends in the range 0x......01 - 0x......7F. // i.e. which ends in the range 0x......01 - 0x......7F.
for(WordIndex=0; WordIndex<BlockSizeInWords; WordIndex++, DataBuffer++, WordAddress = WordAddress + 4) { for (WordIndex = 0; WordIndex < BlockSizeInWords; WordIndex++, DataBuffer++, WordAddress = WordAddress + 4) {
Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer); Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
goto EXIT; goto EXIT;
} }
} }
@ -309,64 +321,65 @@ EXIT:
gBS->RestoreTPL (OriginalTPL); gBS->RestoreTPL (OriginalTPL);
} }
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR, "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = \"%r\".\n", WordAddress, Status)); DEBUG ((DEBUG_ERROR, "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = \"%r\".\n", WordAddress, Status));
} }
return Status; return Status;
} }
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashInitialise ( NorFlashInitialise (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 Index; UINT32 Index;
NOR_FLASH_DESCRIPTION* NorFlashDevices; NOR_FLASH_DESCRIPTION *NorFlashDevices;
BOOLEAN ContainVariableStorage; BOOLEAN ContainVariableStorage;
Status = NorFlashPlatformInitialization (); Status = NorFlashPlatformInitialization ();
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR,"NorFlashInitialise: Fail to initialize Nor Flash devices\n")); DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to initialize Nor Flash devices\n"));
return Status; return Status;
} }
Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount); Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR,"NorFlashInitialise: Fail to get Nor Flash devices\n")); DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to get Nor Flash devices\n"));
return Status; return Status;
} }
mNorFlashInstances = AllocateRuntimePool (sizeof(NOR_FLASH_INSTANCE*) * mNorFlashDeviceCount); mNorFlashInstances = AllocateRuntimePool (sizeof (NOR_FLASH_INSTANCE *) * mNorFlashDeviceCount);
for (Index = 0; Index < mNorFlashDeviceCount; Index++) { for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
// Check if this NOR Flash device contain the variable storage region // Check if this NOR Flash device contain the variable storage region
if (PcdGet64 (PcdFlashNvStorageVariableBase64) != 0) { if (PcdGet64 (PcdFlashNvStorageVariableBase64) != 0) {
ContainVariableStorage = ContainVariableStorage =
(NorFlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) && (NorFlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) &&
(PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize) <= (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize) <=
NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size); NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
} else { } else {
ContainVariableStorage = ContainVariableStorage =
(NorFlashDevices[Index].RegionBaseAddress <= PcdGet32 (PcdFlashNvStorageVariableBase)) && (NorFlashDevices[Index].RegionBaseAddress <= PcdGet32 (PcdFlashNvStorageVariableBase)) &&
(PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvStorageVariableSize) <= (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvStorageVariableSize) <=
NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size); NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
} }
Status = NorFlashCreateInstance ( Status = NorFlashCreateInstance (
NorFlashDevices[Index].DeviceBaseAddress, NorFlashDevices[Index].DeviceBaseAddress,
NorFlashDevices[Index].RegionBaseAddress, NorFlashDevices[Index].RegionBaseAddress,
NorFlashDevices[Index].Size, NorFlashDevices[Index].Size,
Index, Index,
NorFlashDevices[Index].BlockSize, NorFlashDevices[Index].BlockSize,
ContainVariableStorage, ContainVariableStorage,
&mNorFlashInstances[Index] &mNorFlashInstances[Index]
); );
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR,"NorFlashInitialise: Fail to create instance for NorFlash[%d]\n",Index)); DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to create instance for NorFlash[%d]\n", Index));
} }
} }
@ -389,16 +402,16 @@ NorFlashInitialise (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashFvbInitialize ( NorFlashFvbInitialize (
IN NOR_FLASH_INSTANCE* Instance IN NOR_FLASH_INSTANCE *Instance
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 FvbNumLba; UINT32 FvbNumLba;
EFI_BOOT_MODE BootMode; EFI_BOOT_MODE BootMode;
UINTN RuntimeMmioRegionSize; UINTN RuntimeMmioRegionSize;
DEBUG((DEBUG_BLKIO,"NorFlashFvbInitialize\n")); DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
ASSERT((Instance != NULL)); ASSERT ((Instance != NULL));
// //
// Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME
@ -411,19 +424,22 @@ NorFlashFvbInitialize (
RuntimeMmioRegionSize = (Instance->RegionBaseAddress - Instance->DeviceBaseAddress) + Instance->Size; RuntimeMmioRegionSize = (Instance->RegionBaseAddress - Instance->DeviceBaseAddress) + Instance->Size;
Status = gDS->AddMemorySpace ( Status = gDS->AddMemorySpace (
EfiGcdMemoryTypeMemoryMappedIo, EfiGcdMemoryTypeMemoryMappedIo,
Instance->DeviceBaseAddress, RuntimeMmioRegionSize, Instance->DeviceBaseAddress,
EFI_MEMORY_UC | EFI_MEMORY_RUNTIME RuntimeMmioRegionSize,
); EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
Status = gDS->SetMemorySpaceAttributes ( Status = gDS->SetMemorySpaceAttributes (
Instance->DeviceBaseAddress, RuntimeMmioRegionSize, Instance->DeviceBaseAddress,
EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); RuntimeMmioRegionSize,
EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
mFlashNvStorageVariableBase = (PcdGet64 (PcdFlashNvStorageVariableBase64) != 0) ? mFlashNvStorageVariableBase = (PcdGet64 (PcdFlashNvStorageVariableBase64) != 0) ?
PcdGet64 (PcdFlashNvStorageVariableBase64) : PcdGet32 (PcdFlashNvStorageVariableBase); PcdGet64 (PcdFlashNvStorageVariableBase64) : PcdGet32 (PcdFlashNvStorageVariableBase);
// Set the index of the first LBA for the FVB // Set the index of the first LBA for the FVB
Instance->StartLba = (mFlashNvStorageVariableBase - Instance->RegionBaseAddress) / Instance->Media.BlockSize; Instance->StartLba = (mFlashNvStorageVariableBase - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
@ -437,23 +453,26 @@ NorFlashFvbInitialize (
} }
// Install the Default FVB header if required // Install the Default FVB header if required
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
// There is no valid header, so time to install one. // There is no valid header, so time to install one.
DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__)); DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__));
DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n", DEBUG ((
__FUNCTION__)); DEBUG_INFO,
"%a: Installing a correct one for this volume.\n",
__FUNCTION__
));
// Erase all the NorFlash that is reserved for variable storage // Erase all the NorFlash that is reserved for variable storage
FvbNumLba = (PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) + PcdGet32(PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize; FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize;
Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR); Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// Install all appropriate headers // Install all appropriate headers
Status = InitializeFvAndVariableStoreHeaders (Instance); Status = InitializeFvAndVariableStoreHeaders (Instance);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
} }

308
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvb.c
View File

@ -20,7 +20,7 @@
#include "NorFlash.h" #include "NorFlash.h"
extern UINTN mFlashNvStorageVariableBase; extern UINTN mFlashNvStorageVariableBase;
/// ///
/// The Firmware Volume Block Protocol is the low-level interface /// The Firmware Volume Block Protocol is the low-level interface
/// to a firmware volume. File-level access to a firmware volume /// to a firmware volume. File-level access to a firmware volume
@ -40,71 +40,90 @@ extern UINTN mFlashNvStorageVariableBase;
**/ **/
EFI_STATUS EFI_STATUS
InitializeFvAndVariableStoreHeaders ( InitializeFvAndVariableStoreHeaders (
IN NOR_FLASH_INSTANCE *Instance IN NOR_FLASH_INSTANCE *Instance
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
VOID* Headers; VOID *Headers;
UINTN HeadersLength; UINTN HeadersLength;
EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
VARIABLE_STORE_HEADER *VariableStoreHeader; VARIABLE_STORE_HEADER *VariableStoreHeader;
UINT32 NvStorageFtwSpareSize; UINT32 NvStorageFtwSpareSize;
UINT32 NvStorageFtwWorkingSize; UINT32 NvStorageFtwWorkingSize;
UINT32 NvStorageVariableSize; UINT32 NvStorageVariableSize;
UINT64 NvStorageFtwSpareBase; UINT64 NvStorageFtwSpareBase;
UINT64 NvStorageFtwWorkingBase; UINT64 NvStorageFtwWorkingBase;
UINT64 NvStorageVariableBase; UINT64 NvStorageVariableBase;
HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER); HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY) + sizeof (VARIABLE_STORE_HEADER);
Headers = AllocateZeroPool(HeadersLength); Headers = AllocateZeroPool (HeadersLength);
NvStorageFtwWorkingSize = PcdGet32 (PcdFlashNvStorageFtwWorkingSize); NvStorageFtwWorkingSize = PcdGet32 (PcdFlashNvStorageFtwWorkingSize);
NvStorageFtwSpareSize = PcdGet32 (PcdFlashNvStorageFtwSpareSize); NvStorageFtwSpareSize = PcdGet32 (PcdFlashNvStorageFtwSpareSize);
NvStorageVariableSize = PcdGet32 (PcdFlashNvStorageVariableSize); NvStorageVariableSize = PcdGet32 (PcdFlashNvStorageVariableSize);
NvStorageFtwSpareBase = (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) != 0) ? NvStorageFtwSpareBase = (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) != 0) ?
PcdGet64 (PcdFlashNvStorageFtwSpareBase64) : PcdGet32 (PcdFlashNvStorageFtwSpareBase); PcdGet64 (PcdFlashNvStorageFtwSpareBase64) : PcdGet32 (PcdFlashNvStorageFtwSpareBase);
NvStorageFtwWorkingBase = (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) != 0) ? NvStorageFtwWorkingBase = (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) != 0) ?
PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) : PcdGet32 (PcdFlashNvStorageFtwWorkingBase); PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) : PcdGet32 (PcdFlashNvStorageFtwWorkingBase);
NvStorageVariableBase = (PcdGet64 (PcdFlashNvStorageVariableBase64) != 0) ? NvStorageVariableBase = (PcdGet64 (PcdFlashNvStorageVariableBase64) != 0) ?
PcdGet64 (PcdFlashNvStorageVariableBase64) : PcdGet32 (PcdFlashNvStorageVariableBase); PcdGet64 (PcdFlashNvStorageVariableBase64) : PcdGet32 (PcdFlashNvStorageVariableBase);
// FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous. // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
if ((NvStorageVariableBase + NvStorageVariableSize) != NvStorageFtwWorkingBase) { if ((NvStorageVariableBase + NvStorageVariableSize) != NvStorageFtwWorkingBase) {
DEBUG ((DEBUG_ERROR, "%a: NvStorageFtwWorkingBase is not contiguous with NvStorageVariableBase region\n", DEBUG ((
__FUNCTION__)); DEBUG_ERROR,
"%a: NvStorageFtwWorkingBase is not contiguous with NvStorageVariableBase region\n",
__FUNCTION__
));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if ((NvStorageFtwWorkingBase + NvStorageFtwWorkingSize) != NvStorageFtwSpareBase) { if ((NvStorageFtwWorkingBase + NvStorageFtwWorkingSize) != NvStorageFtwSpareBase) {
DEBUG ((DEBUG_ERROR, "%a: NvStorageFtwSpareBase is not contiguous with NvStorageFtwWorkingBase region\n", DEBUG ((
__FUNCTION__)); DEBUG_ERROR,
"%a: NvStorageFtwSpareBase is not contiguous with NvStorageFtwWorkingBase region\n",
__FUNCTION__
));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
// Check if the size of the area is at least one block size // Check if the size of the area is at least one block size
if ((NvStorageVariableSize <= 0) || (NvStorageVariableSize / Instance->Media.BlockSize <= 0)) { if ((NvStorageVariableSize <= 0) || (NvStorageVariableSize / Instance->Media.BlockSize <= 0)) {
DEBUG ((DEBUG_ERROR, "%a: NvStorageVariableSize is 0x%x, should be atleast one block size\n", __FUNCTION__, DEBUG ((
NvStorageVariableSize)); DEBUG_ERROR,
"%a: NvStorageVariableSize is 0x%x, should be atleast one block size\n",
__FUNCTION__,
NvStorageVariableSize
));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if ((NvStorageFtwWorkingSize <= 0) || (NvStorageFtwWorkingSize / Instance->Media.BlockSize <= 0)) { if ((NvStorageFtwWorkingSize <= 0) || (NvStorageFtwWorkingSize / Instance->Media.BlockSize <= 0)) {
DEBUG ((DEBUG_ERROR, "%a: NvStorageFtwWorkingSize is 0x%x, should be atleast one block size\n", __FUNCTION__, DEBUG ((
NvStorageFtwWorkingSize)); DEBUG_ERROR,
"%a: NvStorageFtwWorkingSize is 0x%x, should be atleast one block size\n",
__FUNCTION__,
NvStorageFtwWorkingSize
));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if ((NvStorageFtwSpareSize <= 0) || (NvStorageFtwSpareSize / Instance->Media.BlockSize <= 0)) { if ((NvStorageFtwSpareSize <= 0) || (NvStorageFtwSpareSize / Instance->Media.BlockSize <= 0)) {
DEBUG ((DEBUG_ERROR, "%a: NvStorageFtwSpareSize is 0x%x, should be atleast one block size\n", __FUNCTION__, DEBUG ((
NvStorageFtwSpareSize)); DEBUG_ERROR,
"%a: NvStorageFtwSpareSize is 0x%x, should be atleast one block size\n",
__FUNCTION__,
NvStorageFtwSpareSize
));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
// Ensure the Variable area Base Addresses are aligned on a block size boundaries // Ensure the Variable area Base Addresses are aligned on a block size boundaries
if ((NvStorageVariableBase % Instance->Media.BlockSize != 0) || if ((NvStorageVariableBase % Instance->Media.BlockSize != 0) ||
(NvStorageFtwWorkingBase % Instance->Media.BlockSize != 0) || (NvStorageFtwWorkingBase % Instance->Media.BlockSize != 0) ||
(NvStorageFtwSpareBase % Instance->Media.BlockSize != 0)) { (NvStorageFtwSpareBase % Instance->Media.BlockSize != 0))
{
DEBUG ((DEBUG_ERROR, "%a: NvStorage Base addresses must be aligned to block size boundaries", __FUNCTION__)); DEBUG ((DEBUG_ERROR, "%a: NvStorage Base addresses must be aligned to block size boundaries", __FUNCTION__));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -112,38 +131,38 @@ InitializeFvAndVariableStoreHeaders (
// //
// EFI_FIRMWARE_VOLUME_HEADER // EFI_FIRMWARE_VOLUME_HEADER
// //
FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers; FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Headers;
CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid); CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
FirmwareVolumeHeader->FvLength = FirmwareVolumeHeader->FvLength =
PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFlashNvStorageVariableSize) +
PcdGet32(PcdFlashNvStorageFtwWorkingSize) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
PcdGet32(PcdFlashNvStorageFtwSpareSize); PcdGet32 (PcdFlashNvStorageFtwSpareSize);
FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE; FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) ( FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2)(
EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
EFI_FVB2_READ_STATUS | // Reads are currently enabled EFI_FVB2_READ_STATUS | // Reads are currently enabled
EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
EFI_FVB2_MEMORY_MAPPED | // It is memory mapped EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1') EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1')
EFI_FVB2_WRITE_STATUS | // Writes are currently enabled EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled
); );
FirmwareVolumeHeader->HeaderLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY); FirmwareVolumeHeader->HeaderLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY);
FirmwareVolumeHeader->Revision = EFI_FVH_REVISION; FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1; FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize; FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize;
FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0; FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
FirmwareVolumeHeader->BlockMap[1].Length = 0; FirmwareVolumeHeader->BlockMap[1].Length = 0;
FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16*)FirmwareVolumeHeader,FirmwareVolumeHeader->HeaderLength); FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16 *)FirmwareVolumeHeader, FirmwareVolumeHeader->HeaderLength);
// //
// VARIABLE_STORE_HEADER // VARIABLE_STORE_HEADER
// //
VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)Headers + FirmwareVolumeHeader->HeaderLength); VariableStoreHeader = (VARIABLE_STORE_HEADER *)((UINTN)Headers + FirmwareVolumeHeader->HeaderLength);
CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid); CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid);
VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength; VariableStoreHeader->Size = PcdGet32 (PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED; VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
VariableStoreHeader->State = VARIABLE_STORE_HEALTHY; VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
// Install the combined super-header in the NorFlash // Install the combined super-header in the NorFlash
Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers); Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
@ -163,7 +182,7 @@ InitializeFvAndVariableStoreHeaders (
**/ **/
EFI_STATUS EFI_STATUS
ValidateFvHeader ( ValidateFvHeader (
IN NOR_FLASH_INSTANCE *Instance IN NOR_FLASH_INSTANCE *Instance
) )
{ {
UINT16 Checksum; UINT16 Checksum;
@ -172,55 +191,72 @@ ValidateFvHeader (
UINTN VariableStoreLength; UINTN VariableStoreLength;
UINTN FvLength; UINTN FvLength;
FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress; FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Instance->RegionBaseAddress;
FvLength = PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) + FvLength = PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
PcdGet32(PcdFlashNvStorageFtwSpareSize); PcdGet32 (PcdFlashNvStorageFtwSpareSize);
// //
// Verify the header revision, header signature, length // Verify the header revision, header signature, length
// Length of FvBlock cannot be 2**64-1 // Length of FvBlock cannot be 2**64-1
// HeaderLength cannot be an odd number // HeaderLength cannot be an odd number
// //
if ( (FwVolHeader->Revision != EFI_FVH_REVISION) if ( (FwVolHeader->Revision != EFI_FVH_REVISION)
|| (FwVolHeader->Signature != EFI_FVH_SIGNATURE) || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
|| (FwVolHeader->FvLength != FvLength) || (FwVolHeader->FvLength != FvLength)
) )
{ {
DEBUG ((DEBUG_INFO, "%a: No Firmware Volume header present\n", DEBUG ((
__FUNCTION__)); DEBUG_INFO,
"%a: No Firmware Volume header present\n",
__FUNCTION__
));
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
// Check the Firmware Volume Guid // Check the Firmware Volume Guid
if( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) { if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) {
DEBUG ((DEBUG_INFO, "%a: Firmware Volume Guid non-compatible\n", DEBUG ((
__FUNCTION__)); DEBUG_INFO,
"%a: Firmware Volume Guid non-compatible\n",
__FUNCTION__
));
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
// Verify the header checksum // Verify the header checksum
Checksum = CalculateSum16((UINT16*)FwVolHeader, FwVolHeader->HeaderLength); Checksum = CalculateSum16 ((UINT16 *)FwVolHeader, FwVolHeader->HeaderLength);
if (Checksum != 0) { if (Checksum != 0) {
DEBUG ((DEBUG_INFO, "%a: FV checksum is invalid (Checksum:0x%X)\n", DEBUG ((
__FUNCTION__, Checksum)); DEBUG_INFO,
"%a: FV checksum is invalid (Checksum:0x%X)\n",
__FUNCTION__,
Checksum
));
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + FwVolHeader->HeaderLength); VariableStoreHeader = (VARIABLE_STORE_HEADER *)((UINTN)FwVolHeader + FwVolHeader->HeaderLength);
// Check the Variable Store Guid // Check the Variable Store Guid
if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) && if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) &&
!CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid)) { !CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid))
DEBUG ((DEBUG_INFO, "%a: Variable Store Guid non-compatible\n", {
__FUNCTION__)); DEBUG ((
DEBUG_INFO,
"%a: Variable Store Guid non-compatible\n",
__FUNCTION__
));
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength; VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
if (VariableStoreHeader->Size != VariableStoreLength) { if (VariableStoreHeader->Size != VariableStoreLength) {
DEBUG ((DEBUG_INFO, "%a: Variable Store Length does not match\n", DEBUG ((
__FUNCTION__)); DEBUG_INFO,
"%a: Variable Store Length does not match\n",
__FUNCTION__
));
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
@ -242,29 +278,28 @@ ValidateFvHeader (
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbGetAttributes( FvbGetAttributes (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
OUT EFI_FVB_ATTRIBUTES_2 *Attributes OUT EFI_FVB_ATTRIBUTES_2 *Attributes
) )
{ {
EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
Instance = INSTANCE_FROM_FVB_THIS(This); Instance = INSTANCE_FROM_FVB_THIS (This);
FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) ( FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2)(
EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
EFI_FVB2_READ_STATUS | // Reads are currently enabled EFI_FVB2_READ_STATUS | // Reads are currently enabled
EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
EFI_FVB2_MEMORY_MAPPED | // It is memory mapped EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1') EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1')
); );
// Check if it is write protected // Check if it is write protected
if (Instance->Media.ReadOnly != TRUE) { if (Instance->Media.ReadOnly != TRUE) {
FlashFvbAttributes = FlashFvbAttributes | FlashFvbAttributes = FlashFvbAttributes |
EFI_FVB2_WRITE_STATUS | // Writes are currently enabled EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled
@ -298,12 +333,12 @@ FvbGetAttributes(
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbSetAttributes( FvbSetAttributes (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
) )
{ {
DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attributes)); DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n", *Attributes));
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -331,13 +366,13 @@ FvbGetPhysicalAddress (
OUT EFI_PHYSICAL_ADDRESS *Address OUT EFI_PHYSICAL_ADDRESS *Address
) )
{ {
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
Instance = INSTANCE_FROM_FVB_THIS(This); Instance = INSTANCE_FROM_FVB_THIS (This);
DEBUG ((DEBUG_BLKIO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n", Instance->RegionBaseAddress)); DEBUG ((DEBUG_BLKIO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n", Instance->RegionBaseAddress));
ASSERT(Address != NULL); ASSERT (Address != NULL);
*Address = mFlashNvStorageVariableBase; *Address = mFlashNvStorageVariableBase;
return EFI_SUCCESS; return EFI_SUCCESS;
@ -378,10 +413,10 @@ FvbGetBlockSize (
OUT UINTN *NumberOfBlocks OUT UINTN *NumberOfBlocks
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
Instance = INSTANCE_FROM_FVB_THIS(This); Instance = INSTANCE_FROM_FVB_THIS (This);
DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n", Lba, Instance->Media.BlockSize, Instance->Media.LastBlock)); DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n", Lba, Instance->Media.BlockSize, Instance->Media.LastBlock));
@ -390,8 +425,8 @@ FvbGetBlockSize (
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
} else { } else {
// This is easy because in this platform each NorFlash device has equal sized blocks. // This is easy because in this platform each NorFlash device has equal sized blocks.
*BlockSize = (UINTN) Instance->Media.BlockSize; *BlockSize = (UINTN)Instance->Media.BlockSize;
*NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1); *NumberOfBlocks = (UINTN)(Instance->Media.LastBlock - Lba + 1);
DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize: *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n", *BlockSize, *NumberOfBlocks)); DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize: *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n", *BlockSize, *NumberOfBlocks));
@ -445,18 +480,18 @@ FvbGetBlockSize (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbRead ( FvbRead (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN OUT UINTN *NumBytes, IN OUT UINTN *NumBytes,
IN OUT UINT8 *Buffer IN OUT UINT8 *Buffer
) )
{ {
EFI_STATUS TempStatus; EFI_STATUS TempStatus;
UINTN BlockSize; UINTN BlockSize;
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
Instance = INSTANCE_FROM_FVB_THIS(This); Instance = INSTANCE_FROM_FVB_THIS (This);
DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", Instance->StartLba + Lba, Offset, *NumBytes, Buffer)); DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", Instance->StartLba + Lba, Offset, *NumBytes, Buffer));
@ -465,14 +500,15 @@ FvbRead (
// Cache the block size to avoid de-referencing pointers all the time // Cache the block size to avoid de-referencing pointers all the time
BlockSize = Instance->Media.BlockSize; BlockSize = Instance->Media.BlockSize;
DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= BlockSize=0x%x\n", Offset, *NumBytes, BlockSize )); DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= BlockSize=0x%x\n", Offset, *NumBytes, BlockSize));
// The read must not span block boundaries. // The read must not span block boundaries.
// We need to check each variable individually because adding two large values together overflows. // We need to check each variable individually because adding two large values together overflows.
if ((Offset >= BlockSize) || if ((Offset >= BlockSize) ||
(*NumBytes > BlockSize) || (*NumBytes > BlockSize) ||
((Offset + *NumBytes) > BlockSize)) { ((Offset + *NumBytes) > BlockSize))
DEBUG ((DEBUG_ERROR, "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize )); {
DEBUG ((DEBUG_ERROR, "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize));
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
@ -495,6 +531,7 @@ FvbRead (
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -555,14 +592,14 @@ FvbRead (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbWrite ( FvbWrite (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINTN Offset, IN UINTN Offset,
IN OUT UINTN *NumBytes, IN OUT UINTN *NumBytes,
IN UINT8 *Buffer IN UINT8 *Buffer
) )
{ {
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
Instance = INSTANCE_FROM_FVB_THIS (This); Instance = INSTANCE_FROM_FVB_THIS (This);
@ -615,18 +652,18 @@ FvbWrite (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FvbEraseBlocks ( FvbEraseBlocks (
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
... ...
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
VA_LIST Args; VA_LIST Args;
UINTN BlockAddress; // Physical address of Lba to erase UINTN BlockAddress; // Physical address of Lba to erase
EFI_LBA StartingLba; // Lba from which we start erasing EFI_LBA StartingLba; // Lba from which we start erasing
UINTN NumOfLba; // Number of Lba blocks to erase UINTN NumOfLba; // Number of Lba blocks to erase
NOR_FLASH_INSTANCE *Instance; NOR_FLASH_INSTANCE *Instance;
Instance = INSTANCE_FROM_FVB_THIS(This); Instance = INSTANCE_FROM_FVB_THIS (This);
DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n")); DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n"));
@ -648,7 +685,7 @@ FvbEraseBlocks (
// Have we reached the end of the list? // Have we reached the end of the list?
if (StartingLba == EFI_LBA_LIST_TERMINATOR) { if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
//Exit the while loop // Exit the while loop
break; break;
} }
@ -670,6 +707,7 @@ FvbEraseBlocks (
goto EXIT; goto EXIT;
} }
} while (TRUE); } while (TRUE);
VA_END (Args); VA_END (Args);
// //
@ -691,18 +729,17 @@ FvbEraseBlocks (
// Go through each one and erase it // Go through each one and erase it
while (NumOfLba > 0) { while (NumOfLba > 0) {
// Get the physical address of Lba to erase // Get the physical address of Lba to erase
BlockAddress = GET_NOR_BLOCK_ADDRESS ( BlockAddress = GET_NOR_BLOCK_ADDRESS (
Instance->RegionBaseAddress, Instance->RegionBaseAddress,
Instance->StartLba + StartingLba, Instance->StartLba + StartingLba,
Instance->Media.BlockSize Instance->Media.BlockSize
); );
// Erase it // Erase it
DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n", Instance->StartLba + StartingLba, BlockAddress)); DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n", Instance->StartLba + StartingLba, BlockAddress));
Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
VA_END (Args); VA_END (Args);
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
goto EXIT; goto EXIT;
@ -713,6 +750,7 @@ FvbEraseBlocks (
NumOfLba--; NumOfLba--;
} }
} while (TRUE); } while (TRUE);
VA_END (Args); VA_END (Args);
EXIT: EXIT:
@ -730,10 +768,10 @@ EXIT:
VOID VOID
EFIAPI EFIAPI
FvbVirtualNotifyEvent ( FvbVirtualNotifyEvent (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase); EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageVariableBase);
return; return;
} }

253
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c
View File

@ -16,13 +16,13 @@
// //
// Global variable declarations // Global variable declarations
// //
NOR_FLASH_INSTANCE **mNorFlashInstances; NOR_FLASH_INSTANCE **mNorFlashInstances;
UINT32 mNorFlashDeviceCount; UINT32 mNorFlashDeviceCount;
UINTN mFlashNvStorageVariableBase; UINTN mFlashNvStorageVariableBase;
NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = { NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
NOR_FLASH_SIGNATURE, // Signature NOR_FLASH_SIGNATURE, // Signature
NULL, // Handle ... NEED TO BE FILLED NULL, // Handle ... NEED TO BE FILLED
0, // DeviceBaseAddress ... NEED TO BE FILLED 0, // DeviceBaseAddress ... NEED TO BE FILLED
0, // RegionBaseAddress ... NEED TO BE FILLED 0, // RegionBaseAddress ... NEED TO BE FILLED
@ -31,43 +31,43 @@ NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
{ {
EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision
NULL, // Media ... NEED TO BE FILLED NULL, // Media ... NEED TO BE FILLED
NULL, // Reset; NULL, // Reset;
NULL, // ReadBlocks NULL, // ReadBlocks
NULL, // WriteBlocks NULL, // WriteBlocks
NULL // FlushBlocks NULL // FlushBlocks
}, // BlockIoProtocol }, // BlockIoProtocol
{ {
0, // MediaId ... NEED TO BE FILLED 0, // MediaId ... NEED TO BE FILLED
FALSE, // RemovableMedia FALSE, // RemovableMedia
TRUE, // MediaPresent TRUE, // MediaPresent
FALSE, // LogicalPartition FALSE, // LogicalPartition
FALSE, // ReadOnly FALSE, // ReadOnly
FALSE, // WriteCaching; FALSE, // WriteCaching;
0, // BlockSize ... NEED TO BE FILLED 0, // BlockSize ... NEED TO BE FILLED
4, // IoAlign 4, // IoAlign
0, // LastBlock ... NEED TO BE FILLED 0, // LastBlock ... NEED TO BE FILLED
0, // LowestAlignedLba 0, // LowestAlignedLba
1, // LogicalBlocksPerPhysicalBlock 1, // LogicalBlocksPerPhysicalBlock
}, //Media; }, // Media;
{ {
EFI_DISK_IO_PROTOCOL_REVISION, // Revision EFI_DISK_IO_PROTOCOL_REVISION, // Revision
NULL, // ReadDisk NULL, // ReadDisk
NULL // WriteDisk NULL // WriteDisk
}, },
{ {
FvbGetAttributes, // GetAttributes FvbGetAttributes, // GetAttributes
FvbSetAttributes, // SetAttributes FvbSetAttributes, // SetAttributes
FvbGetPhysicalAddress, // GetPhysicalAddress FvbGetPhysicalAddress, // GetPhysicalAddress
FvbGetBlockSize, // GetBlockSize FvbGetBlockSize, // GetBlockSize
FvbRead, // Read FvbRead, // Read
FvbWrite, // Write FvbWrite, // Write
FvbEraseBlocks, // EraseBlocks FvbEraseBlocks, // EraseBlocks
NULL, //ParentHandle NULL, // ParentHandle
}, // FvbProtoccol; }, // FvbProtoccol;
NULL, // ShadowBuffer NULL, // ShadowBuffer
{ {
{ {
@ -79,7 +79,8 @@ NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
(UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8) (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8)
} }
}, },
{ 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } }, // GUID ... NEED TO BE FILLED { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
}, // GUID ... NEED TO BE FILLED
}, },
0, // Index 0, // Index
{ {
@ -87,43 +88,43 @@ NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
END_ENTIRE_DEVICE_PATH_SUBTYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
{ sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
} }
} // DevicePath } // DevicePath
}; };
EFI_STATUS EFI_STATUS
NorFlashCreateInstance ( NorFlashCreateInstance (
IN UINTN NorFlashDeviceBase, IN UINTN NorFlashDeviceBase,
IN UINTN NorFlashRegionBase, IN UINTN NorFlashRegionBase,
IN UINTN NorFlashSize, IN UINTN NorFlashSize,
IN UINT32 Index, IN UINT32 Index,
IN UINT32 BlockSize, IN UINT32 BlockSize,
IN BOOLEAN SupportFvb, IN BOOLEAN SupportFvb,
OUT NOR_FLASH_INSTANCE** NorFlashInstance OUT NOR_FLASH_INSTANCE **NorFlashInstance
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
NOR_FLASH_INSTANCE* Instance; NOR_FLASH_INSTANCE *Instance;
ASSERT(NorFlashInstance != NULL); ASSERT (NorFlashInstance != NULL);
Instance = AllocateRuntimeCopyPool (sizeof(NOR_FLASH_INSTANCE),&mNorFlashInstanceTemplate); Instance = AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE), &mNorFlashInstanceTemplate);
if (Instance == NULL) { if (Instance == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
Instance->DeviceBaseAddress = NorFlashDeviceBase; Instance->DeviceBaseAddress = NorFlashDeviceBase;
Instance->RegionBaseAddress = NorFlashRegionBase; Instance->RegionBaseAddress = NorFlashRegionBase;
Instance->Size = NorFlashSize; Instance->Size = NorFlashSize;
Instance->BlockIoProtocol.Media = &Instance->Media; Instance->BlockIoProtocol.Media = &Instance->Media;
Instance->Media.MediaId = Index; Instance->Media.MediaId = Index;
Instance->Media.BlockSize = BlockSize; Instance->Media.BlockSize = BlockSize;
Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1; Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1;
CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid); CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid);
Instance->DevicePath.Index = (UINT8)Index; Instance->DevicePath.Index = (UINT8)Index;
Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);; Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);
if (Instance->ShadowBuffer == NULL) { if (Instance->ShadowBuffer == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
@ -137,12 +138,12 @@ NorFlashCreateInstance (
EFI_NATIVE_INTERFACE, EFI_NATIVE_INTERFACE,
&Instance->FvbProtocol &Instance->FvbProtocol
); );
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
FreePool (Instance); FreePool (Instance);
return Status; return Status;
} }
} else { } else {
DEBUG((DEBUG_ERROR,"standalone MM NOR Flash driver only support FVB.\n")); DEBUG ((DEBUG_ERROR, "standalone MM NOR Flash driver only support FVB.\n"));
FreePool (Instance); FreePool (Instance);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -156,12 +157,12 @@ NorFlashCreateInstance (
**/ **/
EFI_STATUS EFI_STATUS
NorFlashUnlockAndEraseSingleBlock ( NorFlashUnlockAndEraseSingleBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN UINTN BlockAddress IN UINTN BlockAddress
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
Index = 0; Index = 0;
// The block erase might fail a first time (SW bug ?). Retry it ... // The block erase might fail a first time (SW bug ?). Retry it ...
@ -171,12 +172,13 @@ NorFlashUnlockAndEraseSingleBlock (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
break; break;
} }
Status = NorFlashEraseSingleBlock (Instance, BlockAddress); Status = NorFlashEraseSingleBlock (Instance, BlockAddress);
Index++; Index++;
} while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED)); } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED));
if (Index == NOR_FLASH_ERASE_RETRY) { if (Index == NOR_FLASH_ERASE_RETRY) {
DEBUG((DEBUG_ERROR,"EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", BlockAddress,Index)); DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", BlockAddress, Index));
} }
return Status; return Status;
@ -184,20 +186,20 @@ NorFlashUnlockAndEraseSingleBlock (
EFI_STATUS EFI_STATUS
NorFlashWriteFullBlock ( NorFlashWriteFullBlock (
IN NOR_FLASH_INSTANCE *Instance, IN NOR_FLASH_INSTANCE *Instance,
IN EFI_LBA Lba, IN EFI_LBA Lba,
IN UINT32 *DataBuffer, IN UINT32 *DataBuffer,
IN UINT32 BlockSizeInWords IN UINT32 BlockSizeInWords
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN WordAddress; UINTN WordAddress;
UINT32 WordIndex; UINT32 WordIndex;
UINTN BufferIndex; UINTN BufferIndex;
UINTN BlockAddress; UINTN BlockAddress;
UINTN BuffersInBlock; UINTN BuffersInBlock;
UINTN RemainingWords; UINTN RemainingWords;
UINTN Cnt; UINTN Cnt;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@ -208,8 +210,8 @@ NorFlashWriteFullBlock (
WordAddress = BlockAddress; WordAddress = BlockAddress;
Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR, "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n", BlockAddress)); DEBUG ((DEBUG_ERROR, "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n", BlockAddress));
goto EXIT; goto EXIT;
} }
@ -217,25 +219,30 @@ NorFlashWriteFullBlock (
// Check that the address starts at a 32-word boundary, i.e. last 7 bits must be zero // Check that the address starts at a 32-word boundary, i.e. last 7 bits must be zero
if ((WordAddress & BOUNDARY_OF_32_WORDS) == 0x00) { if ((WordAddress & BOUNDARY_OF_32_WORDS) == 0x00) {
// First, break the entire block into buffer-sized chunks. // First, break the entire block into buffer-sized chunks.
BuffersInBlock = (UINTN)(BlockSizeInWords * 4) / P30_MAX_BUFFER_SIZE_IN_BYTES; BuffersInBlock = (UINTN)(BlockSizeInWords * 4) / P30_MAX_BUFFER_SIZE_IN_BYTES;
// Then feed each buffer chunk to the NOR Flash // Then feed each buffer chunk to the NOR Flash
// If a buffer does not contain any data, don't write it. // If a buffer does not contain any data, don't write it.
for(BufferIndex=0; for (BufferIndex = 0;
BufferIndex < BuffersInBlock; BufferIndex < BuffersInBlock;
BufferIndex++, WordAddress += P30_MAX_BUFFER_SIZE_IN_BYTES, DataBuffer += P30_MAX_BUFFER_SIZE_IN_WORDS BufferIndex++, WordAddress += P30_MAX_BUFFER_SIZE_IN_BYTES, DataBuffer += P30_MAX_BUFFER_SIZE_IN_WORDS
) { )
{
// Check the buffer to see if it contains any data (not set all 1s). // Check the buffer to see if it contains any data (not set all 1s).
for (Cnt = 0; Cnt < P30_MAX_BUFFER_SIZE_IN_WORDS; Cnt++) { for (Cnt = 0; Cnt < P30_MAX_BUFFER_SIZE_IN_WORDS; Cnt++) {
if (~DataBuffer[Cnt] != 0 ) { if (~DataBuffer[Cnt] != 0 ) {
// Some data found, write the buffer. // Some data found, write the buffer.
Status = NorFlashWriteBuffer (Instance, WordAddress, P30_MAX_BUFFER_SIZE_IN_BYTES, Status = NorFlashWriteBuffer (
DataBuffer); Instance,
if (EFI_ERROR(Status)) { WordAddress,
P30_MAX_BUFFER_SIZE_IN_BYTES,
DataBuffer
);
if (EFI_ERROR (Status)) {
goto EXIT; goto EXIT;
} }
break; break;
} }
} }
@ -244,84 +251,84 @@ NorFlashWriteFullBlock (
// Finally, finish off any remaining words that are less than the maximum size of the buffer // Finally, finish off any remaining words that are less than the maximum size of the buffer
RemainingWords = BlockSizeInWords % P30_MAX_BUFFER_SIZE_IN_WORDS; RemainingWords = BlockSizeInWords % P30_MAX_BUFFER_SIZE_IN_WORDS;
if(RemainingWords != 0) { if (RemainingWords != 0) {
Status = NorFlashWriteBuffer (Instance, WordAddress, (RemainingWords * 4), DataBuffer); Status = NorFlashWriteBuffer (Instance, WordAddress, (RemainingWords * 4), DataBuffer);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
goto EXIT; goto EXIT;
} }
} }
} else { } else {
// For now, use the single word programming algorithm // For now, use the single word programming algorithm
// It is unlikely that the NOR Flash will exist in an address which falls within a 32 word boundary range, // It is unlikely that the NOR Flash will exist in an address which falls within a 32 word boundary range,
// i.e. which ends in the range 0x......01 - 0x......7F. // i.e. which ends in the range 0x......01 - 0x......7F.
for(WordIndex=0; WordIndex<BlockSizeInWords; WordIndex++, DataBuffer++, WordAddress = WordAddress + 4) { for (WordIndex = 0; WordIndex < BlockSizeInWords; WordIndex++, DataBuffer++, WordAddress = WordAddress + 4) {
Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer); Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
goto EXIT; goto EXIT;
} }
} }
} }
EXIT: EXIT:
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR, "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = \"%r\".\n", WordAddress, Status)); DEBUG ((DEBUG_ERROR, "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = \"%r\".\n", WordAddress, Status));
} }
return Status; return Status;
} }
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashInitialise ( NorFlashInitialise (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_MM_SYSTEM_TABLE *MmSystemTable IN EFI_MM_SYSTEM_TABLE *MmSystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 Index; UINT32 Index;
NOR_FLASH_DESCRIPTION* NorFlashDevices; NOR_FLASH_DESCRIPTION *NorFlashDevices;
BOOLEAN ContainVariableStorage; BOOLEAN ContainVariableStorage;
Status = NorFlashPlatformInitialization (); Status = NorFlashPlatformInitialization ();
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR,"NorFlashInitialise: Fail to initialize Nor Flash devices\n")); DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to initialize Nor Flash devices\n"));
return Status; return Status;
} }
Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount); Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR,"NorFlashInitialise: Fail to get Nor Flash devices\n")); DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to get Nor Flash devices\n"));
return Status; return Status;
} }
mNorFlashInstances = AllocatePool (sizeof(NOR_FLASH_INSTANCE*) * mNorFlashDeviceCount); mNorFlashInstances = AllocatePool (sizeof (NOR_FLASH_INSTANCE *) * mNorFlashDeviceCount);
for (Index = 0; Index < mNorFlashDeviceCount; Index++) { for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
// Check if this NOR Flash device contain the variable storage region // Check if this NOR Flash device contain the variable storage region
if (FixedPcdGet64 (PcdFlashNvStorageVariableBase64) != 0) { if (FixedPcdGet64 (PcdFlashNvStorageVariableBase64) != 0) {
ContainVariableStorage = ContainVariableStorage =
(NorFlashDevices[Index].RegionBaseAddress <= FixedPcdGet64 (PcdFlashNvStorageVariableBase64)) && (NorFlashDevices[Index].RegionBaseAddress <= FixedPcdGet64 (PcdFlashNvStorageVariableBase64)) &&
(FixedPcdGet64 (PcdFlashNvStorageVariableBase64) + FixedPcdGet32 (PcdFlashNvStorageVariableSize) <= (FixedPcdGet64 (PcdFlashNvStorageVariableBase64) + FixedPcdGet32 (PcdFlashNvStorageVariableSize) <=
NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size); NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
} else { } else {
ContainVariableStorage = ContainVariableStorage =
(NorFlashDevices[Index].RegionBaseAddress <= FixedPcdGet32 (PcdFlashNvStorageVariableBase)) && (NorFlashDevices[Index].RegionBaseAddress <= FixedPcdGet32 (PcdFlashNvStorageVariableBase)) &&
(FixedPcdGet32 (PcdFlashNvStorageVariableBase) + FixedPcdGet32 (PcdFlashNvStorageVariableSize) <= (FixedPcdGet32 (PcdFlashNvStorageVariableBase) + FixedPcdGet32 (PcdFlashNvStorageVariableSize) <=
NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size); NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
} }
Status = NorFlashCreateInstance ( Status = NorFlashCreateInstance (
NorFlashDevices[Index].DeviceBaseAddress, NorFlashDevices[Index].DeviceBaseAddress,
NorFlashDevices[Index].RegionBaseAddress, NorFlashDevices[Index].RegionBaseAddress,
NorFlashDevices[Index].Size, NorFlashDevices[Index].Size,
Index, Index,
NorFlashDevices[Index].BlockSize, NorFlashDevices[Index].BlockSize,
ContainVariableStorage, ContainVariableStorage,
&mNorFlashInstances[Index] &mNorFlashInstances[Index]
); );
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR,"NorFlashInitialise: Fail to create instance for NorFlash[%d]\n",Index)); DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to create instance for NorFlash[%d]\n", Index));
} }
} }
@ -331,17 +338,16 @@ NorFlashInitialise (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NorFlashFvbInitialize ( NorFlashFvbInitialize (
IN NOR_FLASH_INSTANCE* Instance IN NOR_FLASH_INSTANCE *Instance
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 FvbNumLba; UINT32 FvbNumLba;
ASSERT((Instance != NULL)); ASSERT ((Instance != NULL));
mFlashNvStorageVariableBase = (FixedPcdGet64 (PcdFlashNvStorageVariableBase64) != 0) ? mFlashNvStorageVariableBase = (FixedPcdGet64 (PcdFlashNvStorageVariableBase64) != 0) ?
FixedPcdGet64 (PcdFlashNvStorageVariableBase64) : FixedPcdGet32 (PcdFlashNvStorageVariableBase); FixedPcdGet64 (PcdFlashNvStorageVariableBase64) : FixedPcdGet32 (PcdFlashNvStorageVariableBase);
// Set the index of the first LBA for the FVB // Set the index of the first LBA for the FVB
Instance->StartLba = (mFlashNvStorageVariableBase - Instance->RegionBaseAddress) / Instance->Media.BlockSize; Instance->StartLba = (mFlashNvStorageVariableBase - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
@ -349,23 +355,26 @@ NorFlashFvbInitialize (
Status = ValidateFvHeader (Instance); Status = ValidateFvHeader (Instance);
// Install the Default FVB header if required // Install the Default FVB header if required
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
// There is no valid header, so time to install one. // There is no valid header, so time to install one.
DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__)); DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__));
DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n", DEBUG ((
__FUNCTION__)); DEBUG_INFO,
"%a: Installing a correct one for this volume.\n",
__FUNCTION__
));
// Erase all the NorFlash that is reserved for variable storage // Erase all the NorFlash that is reserved for variable storage
FvbNumLba = (PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) + PcdGet32(PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize; FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize;
Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR); Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// Install all appropriate headers // Install all appropriate headers
Status = InitializeFvAndVariableStoreHeaders (Instance); Status = InitializeFvAndVariableStoreHeaders (Instance);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
} }

145
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c
View File

@ -7,7 +7,6 @@
**/ **/
#include <PiDxe.h> #include <PiDxe.h>
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
@ -24,29 +23,31 @@
#include "PL061Gpio.h" #include "PL061Gpio.h"
PLATFORM_GPIO_CONTROLLER *mPL061PlatformGpio; PLATFORM_GPIO_CONTROLLER *mPL061PlatformGpio;
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PL061Locate ( PL061Locate (
IN EMBEDDED_GPIO_PIN Gpio, IN EMBEDDED_GPIO_PIN Gpio,
OUT UINTN *ControllerIndex, OUT UINTN *ControllerIndex,
OUT UINTN *ControllerOffset, OUT UINTN *ControllerOffset,
OUT UINTN *RegisterBase OUT UINTN *RegisterBase
) )
{ {
UINT32 Index; UINT32 Index;
for (Index = 0; Index < mPL061PlatformGpio->GpioControllerCount; Index++) { for (Index = 0; Index < mPL061PlatformGpio->GpioControllerCount; Index++) {
if ( (Gpio >= mPL061PlatformGpio->GpioController[Index].GpioIndex) if ( (Gpio >= mPL061PlatformGpio->GpioController[Index].GpioIndex)
&& (Gpio < mPL061PlatformGpio->GpioController[Index].GpioIndex && (Gpio < mPL061PlatformGpio->GpioController[Index].GpioIndex
+ mPL061PlatformGpio->GpioController[Index].InternalGpioCount)) { + mPL061PlatformGpio->GpioController[Index].InternalGpioCount))
*ControllerIndex = Index; {
*ControllerIndex = Index;
*ControllerOffset = Gpio % mPL061PlatformGpio->GpioController[Index].InternalGpioCount; *ControllerOffset = Gpio % mPL061PlatformGpio->GpioController[Index].InternalGpioCount;
*RegisterBase = mPL061PlatformGpio->GpioController[Index].RegisterBase; *RegisterBase = mPL061PlatformGpio->GpioController[Index].RegisterBase;
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
DEBUG ((DEBUG_ERROR, "%a, failed to locate gpio %d\n", __func__, Gpio)); DEBUG ((DEBUG_ERROR, "%a, failed to locate gpio %d\n", __func__, Gpio));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -72,8 +73,8 @@ STATIC
UINTN UINTN
EFIAPI EFIAPI
PL061EffectiveAddress ( PL061EffectiveAddress (
IN UINTN Address, IN UINTN Address,
IN UINTN Mask IN UINTN Mask
) )
{ {
return ((Address + PL061_GPIO_DATA_REG_OFFSET) + (Mask << 2)); return ((Address + PL061_GPIO_DATA_REG_OFFSET) + (Mask << 2));
@ -83,8 +84,8 @@ STATIC
UINTN UINTN
EFIAPI EFIAPI
PL061GetPins ( PL061GetPins (
IN UINTN Address, IN UINTN Address,
IN UINTN Mask IN UINTN Mask
) )
{ {
return MmioRead8 (PL061EffectiveAddress (Address, Mask)); return MmioRead8 (PL061EffectiveAddress (Address, Mask));
@ -94,9 +95,9 @@ STATIC
VOID VOID
EFIAPI EFIAPI
PL061SetPins ( PL061SetPins (
IN UINTN Address, IN UINTN Address,
IN UINTN Mask, IN UINTN Mask,
IN UINTN Value IN UINTN Value
) )
{ {
MmioWrite8 (PL061EffectiveAddress (Address, Mask), Value); MmioWrite8 (PL061EffectiveAddress (Address, Mask), Value);
@ -105,18 +106,18 @@ PL061SetPins (
/** /**
Function implementations Function implementations
**/ **/
EFI_STATUS EFI_STATUS
PL061Identify ( PL061Identify (
VOID VOID
) )
{ {
UINTN Index; UINTN Index;
UINTN RegisterBase; UINTN RegisterBase;
if ( (mPL061PlatformGpio->GpioCount == 0) if ( (mPL061PlatformGpio->GpioCount == 0)
|| (mPL061PlatformGpio->GpioControllerCount == 0)) { || (mPL061PlatformGpio->GpioControllerCount == 0))
return EFI_NOT_FOUND; {
return EFI_NOT_FOUND;
} }
for (Index = 0; Index < mPL061PlatformGpio->GpioControllerCount; Index++) { for (Index = 0; Index < mPL061PlatformGpio->GpioControllerCount; Index++) {
@ -127,18 +128,20 @@ PL061Identify (
RegisterBase = mPL061PlatformGpio->GpioController[Index].RegisterBase; RegisterBase = mPL061PlatformGpio->GpioController[Index].RegisterBase;
// Check if this is a PrimeCell Peripheral // Check if this is a PrimeCell Peripheral
if ( (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID0) != 0x0D) if ( (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID0) != 0x0D)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID1) != 0xF0) || (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID1) != 0xF0)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID2) != 0x05) || (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID2) != 0x05)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID3) != 0xB1)) { || (MmioRead8 (RegisterBase + PL061_GPIO_PCELL_ID3) != 0xB1))
{
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
// Check if this PrimeCell Peripheral is the PL061 GPIO // Check if this PrimeCell Peripheral is the PL061 GPIO
if ( (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID0) != 0x61) if ( (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID0) != 0x61)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID1) != 0x10) || (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID1) != 0x10)
|| ((MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID2) & 0xF) != 0x04) || ((MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID2) & 0xF) != 0x04)
|| (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID3) != 0x00)) { || (MmioRead8 (RegisterBase + PL061_GPIO_PERIPH_ID3) != 0x00))
{
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
} }
@ -166,13 +169,13 @@ Returns:
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
Get ( Get (
IN EMBEDDED_GPIO *This, IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio, IN EMBEDDED_GPIO_PIN Gpio,
OUT UINTN *Value OUT UINTN *Value
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index, Offset, RegisterBase; UINTN Index, Offset, RegisterBase;
Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase); Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@ -181,7 +184,7 @@ Get (
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset)) != 0) { if (PL061GetPins (RegisterBase, GPIO_PIN_MASK (Offset)) != 0) {
*Value = 1; *Value = 1;
} else { } else {
*Value = 0; *Value = 0;
@ -216,32 +219,33 @@ Set (
IN EMBEDDED_GPIO_MODE Mode IN EMBEDDED_GPIO_MODE Mode
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index, Offset, RegisterBase; UINTN Index, Offset, RegisterBase;
Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase); Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
switch (Mode) switch (Mode) {
{
case GPIO_MODE_INPUT: case GPIO_MODE_INPUT:
// Set the corresponding direction bit to LOW for input // Set the corresponding direction bit to LOW for input
MmioAnd8 (RegisterBase + PL061_GPIO_DIR_REG, MmioAnd8 (
~GPIO_PIN_MASK(Offset) & 0xFF); RegisterBase + PL061_GPIO_DIR_REG,
~GPIO_PIN_MASK(Offset) & 0xFF
);
break; break;
case GPIO_MODE_OUTPUT_0: case GPIO_MODE_OUTPUT_0:
// Set the corresponding direction bit to HIGH for output // Set the corresponding direction bit to HIGH for output
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK (Offset));
// Set the corresponding data bit to LOW for 0 // Set the corresponding data bit to LOW for 0
PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0); PL061SetPins (RegisterBase, GPIO_PIN_MASK (Offset), 0);
break; break;
case GPIO_MODE_OUTPUT_1: case GPIO_MODE_OUTPUT_1:
// Set the corresponding direction bit to HIGH for output // Set the corresponding direction bit to HIGH for output
MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK(Offset)); MmioOr8 (RegisterBase + PL061_GPIO_DIR_REG, GPIO_PIN_MASK (Offset));
// Set the corresponding data bit to HIGH for 1 // Set the corresponding data bit to HIGH for 1
PL061SetPins (RegisterBase, GPIO_PIN_MASK(Offset), 0xff); PL061SetPins (RegisterBase, GPIO_PIN_MASK (Offset), 0xff);
break; break;
default: default:
@ -278,8 +282,8 @@ GetMode (
OUT EMBEDDED_GPIO_MODE *Mode OUT EMBEDDED_GPIO_MODE *Mode
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index, Offset, RegisterBase; UINTN Index, Offset, RegisterBase;
Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase); Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@ -290,9 +294,9 @@ GetMode (
} }
// Check if it is input or output // Check if it is input or output
if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK(Offset)) { if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK (Offset)) {
// Pin set to output // Pin set to output
if (PL061GetPins (RegisterBase, GPIO_PIN_MASK(Offset)) != 0) { if (PL061GetPins (RegisterBase, GPIO_PIN_MASK (Offset)) != 0) {
*Mode = GPIO_MODE_OUTPUT_1; *Mode = GPIO_MODE_OUTPUT_1;
} else { } else {
*Mode = GPIO_MODE_OUTPUT_0; *Mode = GPIO_MODE_OUTPUT_0;
@ -336,7 +340,7 @@ SetPull (
/** /**
Protocol variable definition Protocol variable definition
**/ **/
EMBEDDED_GPIO gGpio = { EMBEDDED_GPIO gGpio = {
Get, Get,
Set, Set,
GetMode, GetMode,
@ -357,13 +361,13 @@ EMBEDDED_GPIO gGpio = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PL061InstallProtocol ( PL061InstallProtocol (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_HANDLE Handle; EFI_HANDLE Handle;
GPIO_CONTROLLER *GpioController; GPIO_CONTROLLER *GpioController;
// //
// Make sure the Gpio protocol has not been installed in the system yet. // Make sure the Gpio protocol has not been installed in the system yet.
@ -379,29 +383,30 @@ PL061InstallProtocol (
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
mPL061PlatformGpio->GpioCount = PL061_GPIO_PINS; mPL061PlatformGpio->GpioCount = PL061_GPIO_PINS;
mPL061PlatformGpio->GpioControllerCount = 1; mPL061PlatformGpio->GpioControllerCount = 1;
mPL061PlatformGpio->GpioController = (GPIO_CONTROLLER *)((UINTN) mPL061PlatformGpio + sizeof (PLATFORM_GPIO_CONTROLLER)); mPL061PlatformGpio->GpioController = (GPIO_CONTROLLER *)((UINTN)mPL061PlatformGpio + sizeof (PLATFORM_GPIO_CONTROLLER));
GpioController = mPL061PlatformGpio->GpioController; GpioController = mPL061PlatformGpio->GpioController;
GpioController->RegisterBase = (UINTN) PcdGet32 (PcdPL061GpioBase); GpioController->RegisterBase = (UINTN)PcdGet32 (PcdPL061GpioBase);
GpioController->GpioIndex = 0; GpioController->GpioIndex = 0;
GpioController->InternalGpioCount = PL061_GPIO_PINS; GpioController->InternalGpioCount = PL061_GPIO_PINS;
} }
Status = PL061Identify(); Status = PL061Identify ();
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
// Install the Embedded GPIO Protocol onto a new handle // Install the Embedded GPIO Protocol onto a new handle
Handle = NULL; Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces( Status = gBS->InstallMultipleProtocolInterfaces (
&Handle, &Handle,
&gEmbeddedGpioProtocolGuid, &gGpio, &gEmbeddedGpioProtocolGuid,
&gGpio,
NULL NULL
); );
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
Status = EFI_OUT_OF_RESOURCES; Status = EFI_OUT_OF_RESOURCES;
} }

45
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h
View File

@ -6,38 +6,37 @@
**/ **/
#ifndef __PL061_GPIO_H__ #ifndef __PL061_GPIO_H__
#define __PL061_GPIO_H__ #define __PL061_GPIO_H__
#include <Protocol/EmbeddedGpio.h> #include <Protocol/EmbeddedGpio.h>
// PL061 GPIO Registers // PL061 GPIO Registers
#define PL061_GPIO_DATA_REG_OFFSET ((UINTN) 0x000) #define PL061_GPIO_DATA_REG_OFFSET ((UINTN) 0x000)
#define PL061_GPIO_DATA_REG 0x000 #define PL061_GPIO_DATA_REG 0x000
#define PL061_GPIO_DIR_REG 0x400 #define PL061_GPIO_DIR_REG 0x400
#define PL061_GPIO_IS_REG 0x404 #define PL061_GPIO_IS_REG 0x404
#define PL061_GPIO_IBE_REG 0x408 #define PL061_GPIO_IBE_REG 0x408
#define PL061_GPIO_IEV_REG 0x40C #define PL061_GPIO_IEV_REG 0x40C
#define PL061_GPIO_IE_REG 0x410 #define PL061_GPIO_IE_REG 0x410
#define PL061_GPIO_RIS_REG 0x414 #define PL061_GPIO_RIS_REG 0x414
#define PL061_GPIO_MIS_REG 0x410 #define PL061_GPIO_MIS_REG 0x410
#define PL061_GPIO_IC_REG 0x41C #define PL061_GPIO_IC_REG 0x41C
#define PL061_GPIO_AFSEL_REG 0x420 #define PL061_GPIO_AFSEL_REG 0x420
#define PL061_GPIO_PERIPH_ID0 0xFE0 #define PL061_GPIO_PERIPH_ID0 0xFE0
#define PL061_GPIO_PERIPH_ID1 0xFE4 #define PL061_GPIO_PERIPH_ID1 0xFE4
#define PL061_GPIO_PERIPH_ID2 0xFE8 #define PL061_GPIO_PERIPH_ID2 0xFE8
#define PL061_GPIO_PERIPH_ID3 0xFEC #define PL061_GPIO_PERIPH_ID3 0xFEC
#define PL061_GPIO_PCELL_ID0 0xFF0 #define PL061_GPIO_PCELL_ID0 0xFF0
#define PL061_GPIO_PCELL_ID1 0xFF4 #define PL061_GPIO_PCELL_ID1 0xFF4
#define PL061_GPIO_PCELL_ID2 0xFF8 #define PL061_GPIO_PCELL_ID2 0xFF8
#define PL061_GPIO_PCELL_ID3 0xFFC #define PL061_GPIO_PCELL_ID3 0xFFC
#define PL061_GPIO_PINS 8 #define PL061_GPIO_PINS 8
// All bits low except one bit high, native bit length // All bits low except one bit high, native bit length
#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin))) #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
#endif // __PL061_GPIO_H__ #endif // __PL061_GPIO_H__

67
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
View File

@ -7,7 +7,6 @@
**/ **/
#include <PiDxe.h> #include <PiDxe.h>
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
@ -68,8 +67,8 @@ STATIC
VOID VOID
EFIAPI EFIAPI
SP805InterruptHandler ( SP805InterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
SP805Unlock (); SP805Unlock ();
@ -171,15 +170,15 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SP805RegisterHandler ( SP805RegisterHandler (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
) )
{ {
if (mWatchdogNotify == NULL && NotifyFunction == NULL) { if ((mWatchdogNotify == NULL) && (NotifyFunction == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (mWatchdogNotify != NULL && NotifyFunction != NULL) { if ((mWatchdogNotify != NULL) && (NotifyFunction != NULL)) {
return EFI_ALREADY_STARTED; return EFI_ALREADY_STARTED;
} }
@ -219,8 +218,8 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SP805SetTimerPeriod ( SP805SetTimerPeriod (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod // In 100ns units IN UINT64 TimerPeriod // In 100ns units
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -291,8 +290,8 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SP805GetTimerPeriod ( SP805GetTimerPeriod (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod OUT UINT64 *TimerPeriod
) )
{ {
if (TimerPeriod == NULL) { if (TimerPeriod == NULL) {
@ -335,7 +334,7 @@ SP805GetTimerPeriod (
Retrieves the period of the timer interrupt in 100 nS units. Retrieves the period of the timer interrupt in 100 nS units.
**/ **/
STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = { STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
SP805RegisterHandler, SP805RegisterHandler,
SP805SetTimerPeriod, SP805SetTimerPeriod,
SP805GetTimerPeriod SP805GetTimerPeriod
@ -355,16 +354,19 @@ STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SP805Initialize ( SP805Initialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_HANDLE Handle; EFI_HANDLE Handle;
// Find the interrupt controller protocol. ASSERT if not found. // Find the interrupt controller protocol. ASSERT if not found.
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, Status = gBS->LocateProtocol (
(VOID **)&mInterrupt); &gHardwareInterruptProtocolGuid,
NULL,
(VOID **)&mInterrupt
);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Unlock access to the SP805 registers // Unlock access to the SP805 registers
@ -386,17 +388,26 @@ SP805Initialize (
SP805Lock (); SP805Lock ();
if (PcdGet32 (PcdSP805WatchdogInterrupt) > 0) { if (PcdGet32 (PcdSP805WatchdogInterrupt) > 0) {
Status = mInterrupt->RegisterInterruptSource (mInterrupt, Status = mInterrupt->RegisterInterruptSource (
mInterrupt,
PcdGet32 (PcdSP805WatchdogInterrupt), PcdGet32 (PcdSP805WatchdogInterrupt),
SP805InterruptHandler); SP805InterruptHandler
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: failed to register watchdog interrupt - %r\n", DEBUG ((
__FUNCTION__, Status)); DEBUG_ERROR,
"%a: failed to register watchdog interrupt - %r\n",
__FUNCTION__,
Status
));
return Status; return Status;
} }
} else { } else {
DEBUG ((DEBUG_WARN, "%a: no interrupt specified, running in RESET mode only\n", DEBUG ((
__FUNCTION__)); DEBUG_WARN,
"%a: no interrupt specified, running in RESET mode only\n",
__FUNCTION__
));
} }
// //
@ -406,8 +417,13 @@ SP805Initialize (
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid); ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
// Register for an ExitBootServicesEvent // Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, Status = gBS->CreateEvent (
ExitBootServicesEvent, NULL, &mEfiExitBootServicesEvent); EVT_SIGNAL_EXIT_BOOT_SERVICES,
TPL_NOTIFY,
ExitBootServicesEvent,
NULL,
&mEfiExitBootServicesEvent
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Status = EFI_OUT_OF_RESOURCES; Status = EFI_OUT_OF_RESOURCES;
goto EXIT; goto EXIT;
@ -417,7 +433,8 @@ SP805Initialize (
Handle = NULL; Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&Handle, &Handle,
&gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer, &gEfiWatchdogTimerArchProtocolGuid,
&mWatchdogTimer,
NULL NULL
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {

33
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h
View File

@ -6,28 +6,27 @@
**/ **/
#ifndef __SP805_WATCHDOG_H__ #ifndef __SP805_WATCHDOG_H__
#define __SP805_WATCHDOG_H__ #define __SP805_WATCHDOG_H__
// SP805 Watchdog Registers // SP805 Watchdog Registers
#define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000) #define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)
#define SP805_WDOG_CURRENT_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004) #define SP805_WDOG_CURRENT_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)
#define SP805_WDOG_CONTROL_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008) #define SP805_WDOG_CONTROL_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)
#define SP805_WDOG_INT_CLR_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C) #define SP805_WDOG_INT_CLR_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)
#define SP805_WDOG_RAW_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010) #define SP805_WDOG_RAW_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)
#define SP805_WDOG_MSK_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014) #define SP805_WDOG_MSK_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)
#define SP805_WDOG_LOCK_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00) #define SP805_WDOG_LOCK_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)
#define SP805_WDOG_PERIPH_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0) #define SP805_WDOG_PERIPH_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)
#define SP805_WDOG_PERIPH_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4) #define SP805_WDOG_PERIPH_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)
#define SP805_WDOG_PERIPH_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8) #define SP805_WDOG_PERIPH_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)
#define SP805_WDOG_PERIPH_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC) #define SP805_WDOG_PERIPH_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)
#define SP805_WDOG_PCELL_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0) #define SP805_WDOG_PCELL_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)
#define SP805_WDOG_PCELL_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4) #define SP805_WDOG_PCELL_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)
#define SP805_WDOG_PCELL_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8) #define SP805_WDOG_PCELL_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)
#define SP805_WDOG_PCELL_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC) #define SP805_WDOG_PCELL_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)
// Timer control register bit definitions // Timer control register bit definitions
#define SP805_WDOG_CTRL_INTEN BIT0 #define SP805_WDOG_CTRL_INTEN BIT0
@ -39,4 +38,4 @@
#define SP805_WDOG_LOCK_IS_LOCKED 0x00000001 #define SP805_WDOG_LOCK_IS_LOCKED 0x00000001
#define SP805_WDOG_SPECIAL_UNLOCK_CODE 0x1ACCE551 #define SP805_WDOG_SPECIAL_UNLOCK_CODE 0x1ACCE551
#endif // __SP805_WATCHDOG_H__ #endif // __SP805_WATCHDOG_H__

8
ArmPlatformPkg/Include/Library/ArmPlatformLib.h
View File

@ -32,7 +32,7 @@
**/ **/
UINTN UINTN
ArmPlatformGetCorePosition ( ArmPlatformGetCorePosition (
IN UINTN MpId IN UINTN MpId
); );
/** /**
@ -47,7 +47,7 @@ ArmPlatformGetCorePosition (
**/ **/
UINTN UINTN
ArmPlatformIsPrimaryCore ( ArmPlatformIsPrimaryCore (
IN UINTN MpId IN UINTN MpId
); );
/** /**
@ -102,7 +102,7 @@ ArmPlatformPeiBootAction (
**/ **/
RETURN_STATUS RETURN_STATUS
ArmPlatformInitialize ( ArmPlatformInitialize (
IN UINTN MpId IN UINTN MpId
); );
/** /**
@ -117,7 +117,7 @@ ArmPlatformInitialize (
**/ **/
VOID VOID
ArmPlatformGetVirtualMemoryMap ( ArmPlatformGetVirtualMemoryMap (
OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
); );
/** /**

300
ArmPlatformPkg/Include/Library/LcdPlatformLib.h
View File

@ -10,188 +10,188 @@
#include <Protocol/GraphicsOutput.h> #include <Protocol/GraphicsOutput.h>
#define LCD_VRAM_SIZE SIZE_8MB #define LCD_VRAM_SIZE SIZE_8MB
// Modes definitions // Modes definitions
#define VGA 0 #define VGA 0
#define SVGA 1 #define SVGA 1
#define XGA 2 #define XGA 2
#define SXGA 3 #define SXGA 3
#define WSXGA 4 #define WSXGA 4
#define UXGA 5 #define UXGA 5
#define HD 6 #define HD 6
#define WVGA 7 #define WVGA 7
#define QHD 8 #define QHD 8
#define WSVGA 9 #define WSVGA 9
#define HD720 10 #define HD720 10
#define WXGA 11 #define WXGA 11
// VGA Mode: 640 x 480 // VGA Mode: 640 x 480
#define VGA_H_RES_PIXELS 640 #define VGA_H_RES_PIXELS 640
#define VGA_V_RES_PIXELS 480 #define VGA_V_RES_PIXELS 480
#define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */ #define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */
#define VGA_H_SYNC ( 80 - 1) #define VGA_H_SYNC ( 80 - 1)
#define VGA_H_FRONT_PORCH ( 16 - 1) #define VGA_H_FRONT_PORCH ( 16 - 1)
#define VGA_H_BACK_PORCH ( 64 - 1) #define VGA_H_BACK_PORCH ( 64 - 1)
#define VGA_V_SYNC ( 4 - 1) #define VGA_V_SYNC ( 4 - 1)
#define VGA_V_FRONT_PORCH ( 3 - 1) #define VGA_V_FRONT_PORCH ( 3 - 1)
#define VGA_V_BACK_PORCH ( 13 - 1) #define VGA_V_BACK_PORCH ( 13 - 1)
// SVGA Mode: 800 x 600 // SVGA Mode: 800 x 600
#define SVGA_H_RES_PIXELS 800 #define SVGA_H_RES_PIXELS 800
#define SVGA_V_RES_PIXELS 600 #define SVGA_V_RES_PIXELS 600
#define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */ #define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */
#define SVGA_H_SYNC ( 80 - 1) #define SVGA_H_SYNC ( 80 - 1)
#define SVGA_H_FRONT_PORCH ( 32 - 1) #define SVGA_H_FRONT_PORCH ( 32 - 1)
#define SVGA_H_BACK_PORCH (112 - 1) #define SVGA_H_BACK_PORCH (112 - 1)
#define SVGA_V_SYNC ( 4 - 1) #define SVGA_V_SYNC ( 4 - 1)
#define SVGA_V_FRONT_PORCH ( 3 - 1) #define SVGA_V_FRONT_PORCH ( 3 - 1)
#define SVGA_V_BACK_PORCH ( 17 - 1) #define SVGA_V_BACK_PORCH ( 17 - 1)
// XGA Mode: 1024 x 768 // XGA Mode: 1024 x 768
#define XGA_H_RES_PIXELS 1024 #define XGA_H_RES_PIXELS 1024
#define XGA_V_RES_PIXELS 768 #define XGA_V_RES_PIXELS 768
#define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */ #define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */
#define XGA_H_SYNC (104 - 1) #define XGA_H_SYNC (104 - 1)
#define XGA_H_FRONT_PORCH ( 48 - 1) #define XGA_H_FRONT_PORCH ( 48 - 1)
#define XGA_H_BACK_PORCH (152 - 1) #define XGA_H_BACK_PORCH (152 - 1)
#define XGA_V_SYNC ( 4 - 1) #define XGA_V_SYNC ( 4 - 1)
#define XGA_V_FRONT_PORCH ( 3 - 1) #define XGA_V_FRONT_PORCH ( 3 - 1)
#define XGA_V_BACK_PORCH ( 23 - 1) #define XGA_V_BACK_PORCH ( 23 - 1)
// SXGA Mode: 1280 x 1024 // SXGA Mode: 1280 x 1024
#define SXGA_H_RES_PIXELS 1280 #define SXGA_H_RES_PIXELS 1280
#define SXGA_V_RES_PIXELS 1024 #define SXGA_V_RES_PIXELS 1024
#define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */ #define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */
#define SXGA_H_SYNC (136 - 1) #define SXGA_H_SYNC (136 - 1)
#define SXGA_H_FRONT_PORCH ( 80 - 1) #define SXGA_H_FRONT_PORCH ( 80 - 1)
#define SXGA_H_BACK_PORCH (216 - 1) #define SXGA_H_BACK_PORCH (216 - 1)
#define SXGA_V_SYNC ( 7 - 1) #define SXGA_V_SYNC ( 7 - 1)
#define SXGA_V_FRONT_PORCH ( 3 - 1) #define SXGA_V_FRONT_PORCH ( 3 - 1)
#define SXGA_V_BACK_PORCH ( 29 - 1) #define SXGA_V_BACK_PORCH ( 29 - 1)
// WSXGA+ Mode: 1680 x 1050 // WSXGA+ Mode: 1680 x 1050
#define WSXGA_H_RES_PIXELS 1680 #define WSXGA_H_RES_PIXELS 1680
#define WSXGA_V_RES_PIXELS 1050 #define WSXGA_V_RES_PIXELS 1050
#define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */ #define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */
#define WSXGA_H_SYNC (170 - 1) #define WSXGA_H_SYNC (170 - 1)
#define WSXGA_H_FRONT_PORCH (104 - 1) #define WSXGA_H_FRONT_PORCH (104 - 1)
#define WSXGA_H_BACK_PORCH (274 - 1) #define WSXGA_H_BACK_PORCH (274 - 1)
#define WSXGA_V_SYNC ( 5 - 1) #define WSXGA_V_SYNC ( 5 - 1)
#define WSXGA_V_FRONT_PORCH ( 4 - 1) #define WSXGA_V_FRONT_PORCH ( 4 - 1)
#define WSXGA_V_BACK_PORCH ( 41 - 1) #define WSXGA_V_BACK_PORCH ( 41 - 1)
// UXGA Mode: 1600 x 1200 // UXGA Mode: 1600 x 1200
#define UXGA_H_RES_PIXELS 1600 #define UXGA_H_RES_PIXELS 1600
#define UXGA_V_RES_PIXELS 1200 #define UXGA_V_RES_PIXELS 1200
#define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */ #define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */
#define UXGA_H_SYNC (168 - 1) #define UXGA_H_SYNC (168 - 1)
#define UXGA_H_FRONT_PORCH (112 - 1) #define UXGA_H_FRONT_PORCH (112 - 1)
#define UXGA_H_BACK_PORCH (280 - 1) #define UXGA_H_BACK_PORCH (280 - 1)
#define UXGA_V_SYNC ( 4 - 1) #define UXGA_V_SYNC ( 4 - 1)
#define UXGA_V_FRONT_PORCH ( 3 - 1) #define UXGA_V_FRONT_PORCH ( 3 - 1)
#define UXGA_V_BACK_PORCH ( 38 - 1) #define UXGA_V_BACK_PORCH ( 38 - 1)
// HD Mode: 1920 x 1080 // HD Mode: 1920 x 1080
#define HD_H_RES_PIXELS 1920 #define HD_H_RES_PIXELS 1920
#define HD_V_RES_PIXELS 1080 #define HD_V_RES_PIXELS 1080
#define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */ #define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */
#define HD_H_SYNC ( 79 - 1) #define HD_H_SYNC ( 79 - 1)
#define HD_H_FRONT_PORCH (128 - 1) #define HD_H_FRONT_PORCH (128 - 1)
#define HD_H_BACK_PORCH (328 - 1) #define HD_H_BACK_PORCH (328 - 1)
#define HD_V_SYNC ( 5 - 1) #define HD_V_SYNC ( 5 - 1)
#define HD_V_FRONT_PORCH ( 3 - 1) #define HD_V_FRONT_PORCH ( 3 - 1)
#define HD_V_BACK_PORCH ( 32 - 1) #define HD_V_BACK_PORCH ( 32 - 1)
// WVGA Mode: 800 x 480 // WVGA Mode: 800 x 480
#define WVGA_H_RES_PIXELS 800 #define WVGA_H_RES_PIXELS 800
#define WVGA_V_RES_PIXELS 480 #define WVGA_V_RES_PIXELS 480
#define WVGA_OSC_FREQUENCY 29500000 /* 0x01C22260 */ #define WVGA_OSC_FREQUENCY 29500000 /* 0x01C22260 */
#define WVGA_H_SYNC ( 72 - 1) #define WVGA_H_SYNC ( 72 - 1)
#define WVGA_H_FRONT_PORCH ( 24 - 1) #define WVGA_H_FRONT_PORCH ( 24 - 1)
#define WVGA_H_BACK_PORCH ( 96 - 1) #define WVGA_H_BACK_PORCH ( 96 - 1)
#define WVGA_V_SYNC ( 7 - 1) #define WVGA_V_SYNC ( 7 - 1)
#define WVGA_V_FRONT_PORCH ( 3 - 1) #define WVGA_V_FRONT_PORCH ( 3 - 1)
#define WVGA_V_BACK_PORCH ( 10 - 1) #define WVGA_V_BACK_PORCH ( 10 - 1)
// QHD Mode: 960 x 540 // QHD Mode: 960 x 540
#define QHD_H_RES_PIXELS 960 #define QHD_H_RES_PIXELS 960
#define QHD_V_RES_PIXELS 540 #define QHD_V_RES_PIXELS 540
#define QHD_OSC_FREQUENCY 40750000 /* 0x026DCBB0 */ #define QHD_OSC_FREQUENCY 40750000 /* 0x026DCBB0 */
#define QHD_H_SYNC ( 96 - 1) #define QHD_H_SYNC ( 96 - 1)
#define QHD_H_FRONT_PORCH ( 32 - 1) #define QHD_H_FRONT_PORCH ( 32 - 1)
#define QHD_H_BACK_PORCH (128 - 1) #define QHD_H_BACK_PORCH (128 - 1)
#define QHD_V_SYNC ( 5 - 1) #define QHD_V_SYNC ( 5 - 1)
#define QHD_V_FRONT_PORCH ( 3 - 1) #define QHD_V_FRONT_PORCH ( 3 - 1)
#define QHD_V_BACK_PORCH ( 14 - 1) #define QHD_V_BACK_PORCH ( 14 - 1)
// WSVGA Mode: 1024 x 600 // WSVGA Mode: 1024 x 600
#define WSVGA_H_RES_PIXELS 1024 #define WSVGA_H_RES_PIXELS 1024
#define WSVGA_V_RES_PIXELS 600 #define WSVGA_V_RES_PIXELS 600
#define WSVGA_OSC_FREQUENCY 49000000 /* 0x02EBAE40 */ #define WSVGA_OSC_FREQUENCY 49000000 /* 0x02EBAE40 */
#define WSVGA_H_SYNC (104 - 1) #define WSVGA_H_SYNC (104 - 1)
#define WSVGA_H_FRONT_PORCH ( 40 - 1) #define WSVGA_H_FRONT_PORCH ( 40 - 1)
#define WSVGA_H_BACK_PORCH (144 - 1) #define WSVGA_H_BACK_PORCH (144 - 1)
#define WSVGA_V_SYNC ( 10 - 1) #define WSVGA_V_SYNC ( 10 - 1)
#define WSVGA_V_FRONT_PORCH ( 3 - 1) #define WSVGA_V_FRONT_PORCH ( 3 - 1)
#define WSVGA_V_BACK_PORCH ( 11 - 1) #define WSVGA_V_BACK_PORCH ( 11 - 1)
// HD720 Mode: 1280 x 720 // HD720 Mode: 1280 x 720
#define HD720_H_RES_PIXELS 1280 #define HD720_H_RES_PIXELS 1280
#define HD720_V_RES_PIXELS 720 #define HD720_V_RES_PIXELS 720
#define HD720_OSC_FREQUENCY 74500000 /* 0x0470C7A0 */ #define HD720_OSC_FREQUENCY 74500000 /* 0x0470C7A0 */
#define HD720_H_SYNC (128 - 1) #define HD720_H_SYNC (128 - 1)
#define HD720_H_FRONT_PORCH ( 64 - 1) #define HD720_H_FRONT_PORCH ( 64 - 1)
#define HD720_H_BACK_PORCH (192 - 1) #define HD720_H_BACK_PORCH (192 - 1)
#define HD720_V_SYNC ( 5 - 1) #define HD720_V_SYNC ( 5 - 1)
#define HD720_V_FRONT_PORCH ( 3 - 1) #define HD720_V_FRONT_PORCH ( 3 - 1)
#define HD720_V_BACK_PORCH ( 20 - 1) #define HD720_V_BACK_PORCH ( 20 - 1)
// WXGA Mode: 1280 x 800 // WXGA Mode: 1280 x 800
#define WXGA_H_RES_PIXELS 1280 #define WXGA_H_RES_PIXELS 1280
#define WXGA_V_RES_PIXELS 800 #define WXGA_V_RES_PIXELS 800
#define WXGA_OSC_FREQUENCY 83500000 /* 0x04FA1BE0 */ #define WXGA_OSC_FREQUENCY 83500000 /* 0x04FA1BE0 */
#define WXGA_H_SYNC (128 - 1) #define WXGA_H_SYNC (128 - 1)
#define WXGA_H_FRONT_PORCH ( 72 - 1) #define WXGA_H_FRONT_PORCH ( 72 - 1)
#define WXGA_H_BACK_PORCH (200 - 1) #define WXGA_H_BACK_PORCH (200 - 1)
#define WXGA_V_SYNC ( 6 - 1) #define WXGA_V_SYNC ( 6 - 1)
#define WXGA_V_FRONT_PORCH ( 3 - 1) #define WXGA_V_FRONT_PORCH ( 3 - 1)
#define WXGA_V_BACK_PORCH ( 22 - 1) #define WXGA_V_BACK_PORCH ( 22 - 1)
// Colour Masks // Colour Masks
#define LCD_24BPP_RED_MASK 0x00FF0000 #define LCD_24BPP_RED_MASK 0x00FF0000
#define LCD_24BPP_GREEN_MASK 0x0000FF00 #define LCD_24BPP_GREEN_MASK 0x0000FF00
#define LCD_24BPP_BLUE_MASK 0x000000FF #define LCD_24BPP_BLUE_MASK 0x000000FF
#define LCD_24BPP_RESERVED_MASK 0xFF000000 #define LCD_24BPP_RESERVED_MASK 0xFF000000
#define LCD_16BPP_555_RED_MASK 0x00007C00 #define LCD_16BPP_555_RED_MASK 0x00007C00
#define LCD_16BPP_555_GREEN_MASK 0x000003E0 #define LCD_16BPP_555_GREEN_MASK 0x000003E0
#define LCD_16BPP_555_BLUE_MASK 0x0000001F #define LCD_16BPP_555_BLUE_MASK 0x0000001F
#define LCD_16BPP_555_RESERVED_MASK 0x00000000 #define LCD_16BPP_555_RESERVED_MASK 0x00000000
#define LCD_16BPP_565_RED_MASK 0x0000F800 #define LCD_16BPP_565_RED_MASK 0x0000F800
#define LCD_16BPP_565_GREEN_MASK 0x000007E0 #define LCD_16BPP_565_GREEN_MASK 0x000007E0
#define LCD_16BPP_565_BLUE_MASK 0x0000001F #define LCD_16BPP_565_BLUE_MASK 0x0000001F
#define LCD_16BPP_565_RESERVED_MASK 0x00008000 #define LCD_16BPP_565_RESERVED_MASK 0x00008000
#define LCD_12BPP_444_RED_MASK 0x00000F00 #define LCD_12BPP_444_RED_MASK 0x00000F00
#define LCD_12BPP_444_GREEN_MASK 0x000000F0 #define LCD_12BPP_444_GREEN_MASK 0x000000F0
#define LCD_12BPP_444_BLUE_MASK 0x0000000F #define LCD_12BPP_444_BLUE_MASK 0x0000000F
#define LCD_12BPP_444_RESERVED_MASK 0x0000F000 #define LCD_12BPP_444_RESERVED_MASK 0x0000F000
/** The enumeration maps the PL111 LcdBpp values used in the LCD Control /** The enumeration maps the PL111 LcdBpp values used in the LCD Control
Register Register
@ -210,10 +210,10 @@ typedef enum {
// Display timing settings. // Display timing settings.
typedef struct { typedef struct {
UINT32 Resolution; UINT32 Resolution;
UINT32 Sync; UINT32 Sync;
UINT32 BackPorch; UINT32 BackPorch;
UINT32 FrontPorch; UINT32 FrontPorch;
} SCAN_TIMINGS; } SCAN_TIMINGS;
/** Platform related initialization function. /** Platform related initialization function.
@ -225,7 +225,7 @@ typedef struct {
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformInitializeDisplay ( LcdPlatformInitializeDisplay (
IN EFI_HANDLE Handle IN EFI_HANDLE Handle
); );
/** Allocate VRAM memory in DRAM for the framebuffer /** Allocate VRAM memory in DRAM for the framebuffer
@ -242,8 +242,8 @@ LcdPlatformInitializeDisplay (
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformGetVram ( LcdPlatformGetVram (
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, OUT EFI_PHYSICAL_ADDRESS *VramBaseAddress,
OUT UINTN* VramSize OUT UINTN *VramSize
); );
/** Return total number of modes supported. /** Return total number of modes supported.
@ -268,7 +268,7 @@ LcdPlatformGetMaxMode (
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformSetMode ( LcdPlatformSetMode (
IN UINT32 ModeNumber IN UINT32 ModeNumber
); );
/** Return information for the requested mode number. /** Return information for the requested mode number.
@ -303,9 +303,9 @@ LcdPlatformQueryMode (
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformGetTimings ( LcdPlatformGetTimings (
IN UINT32 ModeNumber, IN UINT32 ModeNumber,
OUT SCAN_TIMINGS **Horizontal, OUT SCAN_TIMINGS **Horizontal,
OUT SCAN_TIMINGS **Vertical OUT SCAN_TIMINGS **Vertical
); );
/** Return bits per pixel information for a mode number. /** Return bits per pixel information for a mode number.
@ -320,8 +320,8 @@ LcdPlatformGetTimings (
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformGetBpp ( LcdPlatformGetBpp (
IN UINT32 ModeNumber, IN UINT32 ModeNumber,
OUT LCD_BPP* Bpp OUT LCD_BPP *Bpp
); );
#endif /* LCD_PLATFORM_LIB_H_ */ #endif /* LCD_PLATFORM_LIB_H_ */

12
ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h
View File

@ -10,10 +10,10 @@
#define _NORFLASHPLATFORMLIB_H_ #define _NORFLASHPLATFORMLIB_H_
typedef struct { typedef struct {
UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA) UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
UINTN RegionBaseAddress; // Start address of one single region UINTN RegionBaseAddress; // Start address of one single region
UINTN Size; UINTN Size;
UINTN BlockSize; UINTN BlockSize;
} NOR_FLASH_DESCRIPTION; } NOR_FLASH_DESCRIPTION;
EFI_STATUS EFI_STATUS
@ -23,8 +23,8 @@ NorFlashPlatformInitialization (
EFI_STATUS EFI_STATUS
NorFlashPlatformGetDevices ( NorFlashPlatformGetDevices (
OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions, OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions,
OUT UINT32 *Count OUT UINT32 *Count
); );
#endif /* _NORFLASHPLATFORMLIB_H_ */ #endif /* _NORFLASHPLATFORMLIB_H_ */

16
ArmPlatformPkg/Include/Library/PL011UartLib.h
View File

@ -127,7 +127,7 @@ PL011UartSetControl (
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
PL011UartGetControl ( PL011UartGetControl (
IN UINTN UartBase, IN UINTN UartBase,
OUT UINT32 *Control OUT UINT32 *Control
); );
@ -144,9 +144,9 @@ PL011UartGetControl (
UINTN UINTN
EFIAPI EFIAPI
PL011UartWrite ( PL011UartWrite (
IN UINTN UartBase, IN UINTN UartBase,
IN UINT8 *Buffer, IN UINT8 *Buffer,
IN UINTN NumberOfBytes IN UINTN NumberOfBytes
); );
/** /**
@ -162,9 +162,9 @@ PL011UartWrite (
UINTN UINTN
EFIAPI EFIAPI
PL011UartRead ( PL011UartRead (
IN UINTN UartBase, IN UINTN UartBase,
OUT UINT8 *Buffer, OUT UINT8 *Buffer,
IN UINTN NumberOfBytes IN UINTN NumberOfBytes
); );
/** /**
@ -177,7 +177,7 @@ PL011UartRead (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
PL011UartPoll ( PL011UartPoll (
IN UINTN UartBase IN UINTN UartBase
); );
#endif #endif

86
ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c
View File

@ -17,7 +17,7 @@
#include "ArmMaliDp.h" #include "ArmMaliDp.h"
// CORE_ID of the MALI DP // CORE_ID of the MALI DP
STATIC UINT32 mDpDeviceId; STATIC UINT32 mDpDeviceId;
/** Disable the graphics layer /** Disable the graphics layer
@ -25,7 +25,9 @@ STATIC UINT32 mDpDeviceId;
**/ **/
STATIC STATIC
VOID VOID
LayerGraphicsDisable (VOID) LayerGraphicsDisable (
VOID
)
{ {
MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE); MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE);
} }
@ -36,7 +38,9 @@ LayerGraphicsDisable (VOID)
**/ **/
STATIC STATIC
VOID VOID
LayerGraphicsEnable (VOID) LayerGraphicsEnable (
VOID
)
{ {
MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE); MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE);
} }
@ -49,7 +53,7 @@ LayerGraphicsEnable (VOID)
STATIC STATIC
VOID VOID
LayerGraphicsSetFrame ( LayerGraphicsSetFrame (
IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
) )
{ {
// Disable the graphics layer. // Disable the graphics layer.
@ -84,12 +88,12 @@ LayerGraphicsSetFrame (
STATIC STATIC
VOID VOID
LayerGraphicsConfig ( LayerGraphicsConfig (
IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat, IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat,
IN CONST UINT32 HRes, IN CONST UINT32 HRes,
IN CONST UINT32 VRes IN CONST UINT32 VRes
) )
{ {
UINT32 PixelFormat; UINT32 PixelFormat;
// Disable the graphics layer before configuring any settings. // Disable the graphics layer before configuring any settings.
LayerGraphicsDisable (); LayerGraphicsDisable ();
@ -134,26 +138,26 @@ LayerGraphicsConfig (
STATIC STATIC
VOID VOID
SetDisplayEngineTiming ( SetDisplayEngineTiming (
IN CONST SCAN_TIMINGS * CONST Horizontal, IN CONST SCAN_TIMINGS *CONST Horizontal,
IN CONST SCAN_TIMINGS * CONST Vertical IN CONST SCAN_TIMINGS *CONST Vertical
) )
{ {
UINTN RegHIntervals; UINTN RegHIntervals;
UINTN RegVIntervals; UINTN RegVIntervals;
UINTN RegSyncControl; UINTN RegSyncControl;
UINTN RegHVActiveSize; UINTN RegHVActiveSize;
if (mDpDeviceId == MALIDP_500) { if (mDpDeviceId == MALIDP_500) {
// MALI DP500 timing registers. // MALI DP500 timing registers.
RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS; RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS;
RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS; RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS;
RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL; RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL;
RegHVActiveSize = DP_BASE + DP_DE_DP500_HV_ACTIVESIZE; RegHVActiveSize = DP_BASE + DP_DE_DP500_HV_ACTIVESIZE;
} else { } else {
// MALI DP550/DP650 timing registers. // MALI DP550/DP650 timing registers.
RegHIntervals = DP_BASE + DP_DE_H_INTERVALS; RegHIntervals = DP_BASE + DP_DE_H_INTERVALS;
RegVIntervals = DP_BASE + DP_DE_V_INTERVALS; RegVIntervals = DP_BASE + DP_DE_V_INTERVALS;
RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL; RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL;
RegHVActiveSize = DP_BASE + DP_DE_HV_ACTIVESIZE; RegHVActiveSize = DP_BASE + DP_DE_HV_ACTIVESIZE;
} }
@ -194,11 +198,11 @@ UINT32
ArmMaliDpGetCoreId ( ArmMaliDpGetCoreId (
) )
{ {
UINT32 DpCoreId; UINT32 DpCoreId;
// First check for DP500 as register offset for DP550/DP650 CORE_ID // First check for DP500 as register offset for DP550/DP650 CORE_ID
// is beyond 3K/4K register space of the DP500. // is beyond 3K/4K register space of the DP500.
DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID); DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID);
DpCoreId >>= DP_DE_DP500_CORE_ID_SHIFT; DpCoreId >>= DP_DE_DP500_CORE_ID_SHIFT;
if (DpCoreId == MALIDP_500) { if (DpCoreId == MALIDP_500) {
@ -206,7 +210,7 @@ ArmMaliDpGetCoreId (
} }
// Check for DP550 or DP650. // Check for DP550 or DP650.
DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID); DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID);
DpCoreId >>= DP_DC_CORE_ID_SHIFT; DpCoreId >>= DP_DC_CORE_ID_SHIFT;
if ((DpCoreId == MALIDP_550) || (DpCoreId == MALIDP_650)) { if ((DpCoreId == MALIDP_550) || (DpCoreId == MALIDP_650)) {
@ -227,9 +231,12 @@ ArmMaliDpGetCoreId (
on the platform. on the platform.
**/ **/
EFI_STATUS EFI_STATUS
LcdIdentify (VOID) LcdIdentify (
VOID
)
{ {
DEBUG ((DEBUG_WARN, DEBUG ((
DEBUG_WARN,
"Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n", "Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n",
DP_BASE DP_BASE
)); ));
@ -239,8 +246,8 @@ LcdIdentify (VOID)
} }
if (mDpDeviceId == MALIDP_NOT_PRESENT) { if (mDpDeviceId == MALIDP_NOT_PRESENT) {
DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n")); DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n"));
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId)); DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId));
@ -256,7 +263,7 @@ LcdIdentify (VOID)
**/ **/
EFI_STATUS EFI_STATUS
LcdInitialize ( LcdInitialize (
IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
) )
{ {
DEBUG ((DEBUG_WARN, "Framebuffer base address = %p\n", FrameBaseAddress)); DEBUG ((DEBUG_WARN, "Framebuffer base address = %p\n", FrameBaseAddress));
@ -266,8 +273,11 @@ LcdInitialize (
} }
if (mDpDeviceId == MALIDP_NOT_PRESENT) { if (mDpDeviceId == MALIDP_NOT_PRESENT) {
DEBUG ((DEBUG_ERROR, "ARM Mali DP initialization failed," DEBUG ((
"no ARM Mali DP present\n")); DEBUG_ERROR,
"ARM Mali DP initialization failed,"
"no ARM Mali DP present\n"
));
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
@ -285,7 +295,9 @@ LcdInitialize (
**/ **/
STATIC STATIC
VOID VOID
SetConfigurationMode (VOID) SetConfigurationMode (
VOID
)
{ {
// Request configuration Mode. // Request configuration Mode.
if (mDpDeviceId == MALIDP_500) { if (mDpDeviceId == MALIDP_500) {
@ -303,7 +315,9 @@ SetConfigurationMode (VOID)
**/ **/
STATIC STATIC
VOID VOID
SetNormalMode (VOID) SetNormalMode (
VOID
)
{ {
// Disable configuration Mode. // Disable configuration Mode.
if (mDpDeviceId == MALIDP_500) { if (mDpDeviceId == MALIDP_500) {
@ -321,7 +335,9 @@ SetNormalMode (VOID)
**/ **/
STATIC STATIC
VOID VOID
SetConfigValid (VOID) SetConfigValid (
VOID
)
{ {
if (mDpDeviceId == MALIDP_500) { if (mDpDeviceId == MALIDP_500) {
MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID); MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID);
@ -396,7 +412,9 @@ LcdSetMode (
**/ **/
VOID VOID
LcdShutdown (VOID) LcdShutdown (
VOID
)
{ {
// Disable graphics layer. // Disable graphics layer.
LayerGraphicsDisable (); LayerGraphicsDisable ();

307
ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h
View File

@ -6,232 +6,233 @@
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
#ifndef ARMMALIDP_H_ #ifndef ARMMALIDP_H_
#define ARMMALIDP_H_ #define ARMMALIDP_H_
#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase)) #define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))
// MALI DP Ids // MALI DP Ids
#define MALIDP_NOT_PRESENT 0xFFF #define MALIDP_NOT_PRESENT 0xFFF
#define MALIDP_500 0x500 #define MALIDP_500 0x500
#define MALIDP_550 0x550 #define MALIDP_550 0x550
#define MALIDP_650 0x650 #define MALIDP_650 0x650
// DP500 Peripheral Ids // DP500 Peripheral Ids
#define DP500_ID_PART_0 0x00 #define DP500_ID_PART_0 0x00
#define DP500_ID_DES_0 0xB #define DP500_ID_DES_0 0xB
#define DP500_ID_PART_1 0x5 #define DP500_ID_PART_1 0x5
#define DP500_ID_REVISION 0x1 #define DP500_ID_REVISION 0x1
#define DP500_ID_JEDEC 0x1 #define DP500_ID_JEDEC 0x1
#define DP500_ID_DES_1 0x3 #define DP500_ID_DES_1 0x3
#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0) #define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)
#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \ #define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \
| DP500_ID_PART_1) | DP500_ID_PART_1)
#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \ #define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \
| (DP500_ID_JEDEC << 3) \ | (DP500_ID_JEDEC << 3) \
| (DP500_ID_DES_1)) | (DP500_ID_DES_1))
// DP550 Peripheral Ids // DP550 Peripheral Ids
#define DP550_ID_PART_0 0x50 #define DP550_ID_PART_0 0x50
#define DP550_ID_DES_0 0xB #define DP550_ID_DES_0 0xB
#define DP550_ID_PART_1 0x5 #define DP550_ID_PART_1 0x5
#define DP550_ID_REVISION 0x0 #define DP550_ID_REVISION 0x0
#define DP550_ID_JEDEC 0x1 #define DP550_ID_JEDEC 0x1
#define DP550_ID_DES_1 0x3 #define DP550_ID_DES_1 0x3
#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0) #define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)
#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \ #define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \
| DP550_ID_PART_1) | DP550_ID_PART_1)
#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \ #define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \
| (DP550_ID_JEDEC << 3) \ | (DP550_ID_JEDEC << 3) \
| (DP550_ID_DES_1)) | (DP550_ID_DES_1))
// DP650 Peripheral Ids // DP650 Peripheral Ids
#define DP650_ID_PART_0 0x50 #define DP650_ID_PART_0 0x50
#define DP650_ID_DES_0 0xB #define DP650_ID_DES_0 0xB
#define DP650_ID_PART_1 0x6 #define DP650_ID_PART_1 0x6
#define DP650_ID_REVISION 0x0 #define DP650_ID_REVISION 0x0
#define DP650_ID_JEDEC 0x1 #define DP650_ID_JEDEC 0x1
#define DP650_ID_DES_1 0x3 #define DP650_ID_DES_1 0x3
#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0) #define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)
#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \ #define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \
| DP650_ID_PART_1) | DP650_ID_PART_1)
#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \ #define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \
| (DP650_ID_JEDEC << 3) \ | (DP650_ID_JEDEC << 3) \
| (DP650_ID_DES_1)) | (DP650_ID_DES_1))
// Display Engine (DE) control register offsets for DP550/DP650 // Display Engine (DE) control register offsets for DP550/DP650
#define DP_DE_STATUS 0x00000 #define DP_DE_STATUS 0x00000
#define DP_DE_IRQ_SET 0x00004 #define DP_DE_IRQ_SET 0x00004
#define DP_DE_IRQ_MASK 0x00008 #define DP_DE_IRQ_MASK 0x00008
#define DP_DE_IRQ_CLEAR 0x0000C #define DP_DE_IRQ_CLEAR 0x0000C
#define DP_DE_CONTROL 0x00010 #define DP_DE_CONTROL 0x00010
#define DP_DE_PROG_LINE 0x00014 #define DP_DE_PROG_LINE 0x00014
#define DP_DE_AXI_CONTROL 0x00018 #define DP_DE_AXI_CONTROL 0x00018
#define DP_DE_AXI_QOS 0x0001C #define DP_DE_AXI_QOS 0x0001C
#define DP_DE_DISPLAY_FUNCTION 0x00020 #define DP_DE_DISPLAY_FUNCTION 0x00020
#define DP_DE_H_INTERVALS 0x00030 #define DP_DE_H_INTERVALS 0x00030
#define DP_DE_V_INTERVALS 0x00034 #define DP_DE_V_INTERVALS 0x00034
#define DP_DE_SYNC_CONTROL 0x00038 #define DP_DE_SYNC_CONTROL 0x00038
#define DP_DE_HV_ACTIVESIZE 0x0003C #define DP_DE_HV_ACTIVESIZE 0x0003C
#define DP_DE_DISPLAY_SIDEBAND 0x00040 #define DP_DE_DISPLAY_SIDEBAND 0x00040
#define DP_DE_BACKGROUND_COLOR 0x00044 #define DP_DE_BACKGROUND_COLOR 0x00044
#define DP_DE_DISPLAY_SPLIT 0x00048 #define DP_DE_DISPLAY_SPLIT 0x00048
#define DP_DE_OUTPUT_DEPTH 0x0004C #define DP_DE_OUTPUT_DEPTH 0x0004C
// Display Engine (DE) control register offsets for DP500 // Display Engine (DE) control register offsets for DP500
#define DP_DE_DP500_CORE_ID 0x00018 #define DP_DE_DP500_CORE_ID 0x00018
#define DP_DE_DP500_CONTROL 0x0000C #define DP_DE_DP500_CONTROL 0x0000C
#define DP_DE_DP500_PROG_LINE 0x00010 #define DP_DE_DP500_PROG_LINE 0x00010
#define DP_DE_DP500_H_INTERVALS 0x00028 #define DP_DE_DP500_H_INTERVALS 0x00028
#define DP_DE_DP500_V_INTERVALS 0x0002C #define DP_DE_DP500_V_INTERVALS 0x0002C
#define DP_DE_DP500_SYNC_CONTROL 0x00030 #define DP_DE_DP500_SYNC_CONTROL 0x00030
#define DP_DE_DP500_HV_ACTIVESIZE 0x00034 #define DP_DE_DP500_HV_ACTIVESIZE 0x00034
#define DP_DE_DP500_BG_COLOR_RG 0x0003C #define DP_DE_DP500_BG_COLOR_RG 0x0003C
#define DP_DE_DP500_BG_COLOR_B 0x00040 #define DP_DE_DP500_BG_COLOR_B 0x00040
/* Display Engine (DE) graphics layer (LG) register offsets /* Display Engine (DE) graphics layer (LG) register offsets
* NOTE: For DP500 it will be LG2. * NOTE: For DP500 it will be LG2.
*/ */
#define DE_LG_OFFSET 0x00300 #define DE_LG_OFFSET 0x00300
#define DP_DE_LG_FORMAT (DE_LG_OFFSET) #define DP_DE_LG_FORMAT (DE_LG_OFFSET)
#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04) #define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)
#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08) #define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)
#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C) #define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)
#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10) #define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)
#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14) #define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)
#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18) #define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)
#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C) #define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)
#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20) #define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)
#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C) #define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)
#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30) #define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)
#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48) #define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)
// Display core (DC) control register offsets. // Display core (DC) control register offsets.
#define DP_DC_OFFSET 0x0C000 #define DP_DC_OFFSET 0x0C000
#define DP_DC_STATUS (DP_DC_OFFSET + 0x00) #define DP_DC_STATUS (DP_DC_OFFSET + 0x00)
#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04) #define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)
#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08) #define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)
#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C) #define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)
#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10) #define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)
#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14) #define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)
#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18) #define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)
// DP500 has a global configuration register. // DP500 has a global configuration register.
#define DP_DP500_CONFIG_VALID (0xF00) #define DP_DP500_CONFIG_VALID (0xF00)
// Display core ID register offsets. // Display core ID register offsets.
#define DP_DC_ID_OFFSET 0x0FF00 #define DP_DC_ID_OFFSET 0x0FF00
#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0) #define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)
#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4) #define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)
#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0) #define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)
#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4) #define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)
#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8) #define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)
#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0) #define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)
#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4) #define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)
#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8) #define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)
#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC) #define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)
#define DP_DP500_ID_OFFSET 0x0F00 #define DP_DP500_ID_OFFSET 0x0F00
#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0) #define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)
#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4) #define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)
#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0) #define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)
#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4) #define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)
#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8) #define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)
#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0) #define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)
#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4) #define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)
#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8) #define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)
#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC) #define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)
// Display status configuration mode activation flag // Display status configuration mode activation flag
#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16) #define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)
// Display core control configuration mode // Display core control configuration mode
#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18) #define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)
#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17) #define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)
#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16) #define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)
#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16) #define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16)
#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17) #define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17)
// Display core configuration valid register // Display core configuration valid register
#define DP_DC_CONFIG_VALID_CVAL (0x1U) #define DP_DC_CONFIG_VALID_CVAL (0x1U)
// DC_CORE_ID // DC_CORE_ID
// Display core version register PRODUCT_ID // Display core version register PRODUCT_ID
#define DP_DC_CORE_ID_SHIFT 16 #define DP_DC_CORE_ID_SHIFT 16
#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT #define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT
// Timing settings // Timing settings
#define DP_DE_HBACKPORCH_SHIFT 16 #define DP_DE_HBACKPORCH_SHIFT 16
#define DP_DE_VBACKPORCH_SHIFT 16 #define DP_DE_VBACKPORCH_SHIFT 16
#define DP_DE_VSP_SHIFT 28 #define DP_DE_VSP_SHIFT 28
#define DP_DE_VSYNCWIDTH_SHIFT 16 #define DP_DE_VSYNCWIDTH_SHIFT 16
#define DP_DE_HSP_SHIFT 13 #define DP_DE_HSP_SHIFT 13
#define DP_DE_V_ACTIVE_SHIFT 16 #define DP_DE_V_ACTIVE_SHIFT 16
// BACKGROUND_COLOR // BACKGROUND_COLOR
#define DP_DE_BG_R_PIXEL_SHIFT 16 #define DP_DE_BG_R_PIXEL_SHIFT 16
#define DP_DE_BG_G_PIXEL_SHIFT 8 #define DP_DE_BG_G_PIXEL_SHIFT 8
//Graphics layer LG_FORMAT Pixel Format // Graphics layer LG_FORMAT Pixel Format
#define DP_PIXEL_FORMAT_ARGB_8888 0x8 #define DP_PIXEL_FORMAT_ARGB_8888 0x8
#define DP_PIXEL_FORMAT_ABGR_8888 0x9 #define DP_PIXEL_FORMAT_ABGR_8888 0x9
#define DP_PIXEL_FORMAT_RGBA_8888 0xA #define DP_PIXEL_FORMAT_RGBA_8888 0xA
#define DP_PIXEL_FORMAT_BGRA_8888 0xB #define DP_PIXEL_FORMAT_BGRA_8888 0xB
#define DP_PIXEL_FORMAT_XRGB_8888 0x10 #define DP_PIXEL_FORMAT_XRGB_8888 0x10
#define DP_PIXEL_FORMAT_XBGR_8888 0x11 #define DP_PIXEL_FORMAT_XBGR_8888 0x11
#define DP_PIXEL_FORMAT_RGBX_8888 0x12 #define DP_PIXEL_FORMAT_RGBX_8888 0x12
#define DP_PIXEL_FORMAT_BGRX_8888 0x13 #define DP_PIXEL_FORMAT_BGRX_8888 0x13
#define DP_PIXEL_FORMAT_RGB_888 0x18 #define DP_PIXEL_FORMAT_RGB_888 0x18
#define DP_PIXEL_FORMAT_BGR_888 0x19 #define DP_PIXEL_FORMAT_BGR_888 0x19
// DP500 format code are different than DP550/DP650 // DP500 format code are different than DP550/DP650
#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2 #define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2
#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3 #define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3
#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4 #define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4
#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5 #define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5
// Graphics layer LG_PTR_LOW and LG_PTR_HIGH // Graphics layer LG_PTR_LOW and LG_PTR_HIGH
#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU #define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU
#define DP_DE_LG_PTR_HIGH_SHIFT 32 #define DP_DE_LG_PTR_HIGH_SHIFT 32
// Graphics layer LG_CONTROL register characteristics // Graphics layer LG_CONTROL register characteristics
#define DP_DE_LG_L_ALPHA_SHIFT 16 #define DP_DE_LG_L_ALPHA_SHIFT 16
#define DP_DE_LG_CHK_SHIFT 15 #define DP_DE_LG_CHK_SHIFT 15
#define DP_DE_LG_PMUL_SHIFT 14 #define DP_DE_LG_PMUL_SHIFT 14
#define DP_DE_LG_COM_SHIFT 12 #define DP_DE_LG_COM_SHIFT 12
#define DP_DE_LG_VFP_SHIFT 11 #define DP_DE_LG_VFP_SHIFT 11
#define DP_DE_LG_HFP_SHIFT 10 #define DP_DE_LG_HFP_SHIFT 10
#define DP_DE_LG_ROTATION_SHIFT 8 #define DP_DE_LG_ROTATION_SHIFT 8
#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U #define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U
#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U #define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U
#define DP_DE_LG_LAYER_BLEND_BG 0x2U #define DP_DE_LG_LAYER_BLEND_BG 0x2U
#define DP_DE_LG_PIXEL_BLEND_BG 0x3U #define DP_DE_LG_PIXEL_BLEND_BG 0x3U
#define DP_DE_LG_ENABLE 0x1U #define DP_DE_LG_ENABLE 0x1U
// Graphics layer LG_IN_SIZE register characteristics // Graphics layer LG_IN_SIZE register characteristics
#define DP_DE_LG_V_IN_SIZE_SHIFT 16 #define DP_DE_LG_V_IN_SIZE_SHIFT 16
// Graphics layer LG_CMP_SIZE register characteristics // Graphics layer LG_CMP_SIZE register characteristics
#define DP_DE_LG_V_CMP_SIZE_SHIFT 16 #define DP_DE_LG_V_CMP_SIZE_SHIFT 16
#define DP_DE_LG_V_OFFSET_SHIFT 16 #define DP_DE_LG_V_OFFSET_SHIFT 16
// Helper display timing macro functions. // Helper display timing macro functions.
#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp) #define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)
#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp) #define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)
#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw) #define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)
#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor) #define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)
// Helper layer graphics macros. // Helper layer graphics macros.
#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor) #define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)
#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor) #define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)
#endif /* ARMMALIDP_H_ */ #endif /* ARMMALIDP_H_ */

28
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.c
View File

@ -11,8 +11,7 @@
#include <Ppi/ArmMpCoreInfo.h> #include <Ppi/ArmMpCoreInfo.h>
ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
{ {
// Cluster 0, Core 0 // Cluster 0, Core 0
0x0, 0x0, 0x0, 0x0,
@ -88,26 +87,26 @@ ArmPlatformGetBootMode (
**/ **/
RETURN_STATUS RETURN_STATUS
ArmPlatformInitialize ( ArmPlatformInitialize (
IN UINTN MpId IN UINTN MpId
) )
{ {
if (!ArmPlatformIsPrimaryCore (MpId)) { if (!ArmPlatformIsPrimaryCore (MpId)) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
//TODO: Implement me // TODO: Implement me
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
EFI_STATUS EFI_STATUS
PrePeiCoreGetMpCoreInfo ( PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount, OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable OUT ARM_CORE_INFO **ArmCoreTable
) )
{ {
if (ArmIsMpCore()) { if (ArmIsMpCore ()) {
*CoreCount = sizeof(mArmPlatformNullMpCoreInfoTable) / sizeof(ARM_CORE_INFO); *CoreCount = sizeof (mArmPlatformNullMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
*ArmCoreTable = mArmPlatformNullMpCoreInfoTable; *ArmCoreTable = mArmPlatformNullMpCoreInfoTable;
return EFI_SUCCESS; return EFI_SUCCESS;
} else { } else {
@ -115,9 +114,9 @@ PrePeiCoreGetMpCoreInfo (
} }
} }
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{ {
EFI_PEI_PPI_DESCRIPTOR_PPI, EFI_PEI_PPI_DESCRIPTOR_PPI,
&gArmMpCoreInfoPpiGuid, &gArmMpCoreInfoPpiGuid,
@ -131,12 +130,11 @@ ArmPlatformGetPlatformPpiList (
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
) )
{ {
if (ArmIsMpCore()) { if (ArmIsMpCore ()) {
*PpiListSize = sizeof(gPlatformPpiTable); *PpiListSize = sizeof (gPlatformPpiTable);
*PpiList = gPlatformPpiTable; *PpiList = gPlatformPpiTable;
} else { } else {
*PpiListSize = 0; *PpiListSize = 0;
*PpiList = NULL; *PpiList = NULL;
} }
} }

4
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullMem.c
View File

@ -21,8 +21,8 @@
**/ **/
VOID VOID
ArmPlatformGetVirtualMemoryMap ( ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
) )
{ {
ASSERT(0); ASSERT (0);
} }

28
ArmPlatformPkg/Library/HdLcd/HdLcd.c
View File

@ -16,7 +16,7 @@
#include "HdLcd.h" #include "HdLcd.h"
#define BYTES_PER_PIXEL 4 #define BYTES_PER_PIXEL 4
/** Initialize display. /** Initialize display.
@ -26,7 +26,7 @@
**/ **/
EFI_STATUS EFI_STATUS
LcdInitialize ( LcdInitialize (
IN EFI_PHYSICAL_ADDRESS VramBaseAddress IN EFI_PHYSICAL_ADDRESS VramBaseAddress
) )
{ {
// Disable the controller // Disable the controller
@ -39,7 +39,7 @@ LcdInitialize (
MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress); MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress);
// Setup various registers that never change // Setup various registers that never change
MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES); MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES);
@ -63,9 +63,9 @@ LcdSetMode (
IN UINT32 ModeNumber IN UINT32 ModeNumber
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
SCAN_TIMINGS *Horizontal; SCAN_TIMINGS *Horizontal;
SCAN_TIMINGS *Vertical; SCAN_TIMINGS *Vertical;
EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
@ -100,11 +100,11 @@ LcdSetMode (
: PixelBlueGreenRedReserved8BitPerColor; : PixelBlueGreenRedReserved8BitPerColor;
if (ModeInfo.PixelFormat == PixelFormat) { if (ModeInfo.PixelFormat == PixelFormat) {
MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16); MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16);
MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 0); MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 0);
} else { } else {
MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 16); MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 16);
MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0); MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0);
} }
MmioWrite32 (HDLCD_REG_GREEN_SELECT, (8 << 8) | 8); MmioWrite32 (HDLCD_REG_GREEN_SELECT, (8 << 8) | 8);
@ -126,15 +126,15 @@ LcdSetMode (
MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1); MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1);
// Set the vertical timing information // Set the vertical timing information
MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync); MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync);
MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch); MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch);
MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1); MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1);
MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, Vertical->FrontPorch); MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, Vertical->FrontPorch);
// Set the horizontal timing information // Set the horizontal timing information
MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync); MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync);
MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch); MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch);
MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1); MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1);
MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, Horizontal->FrontPorch); MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, Horizontal->FrontPorch);
// Enable the controller // Enable the controller

100
ArmPlatformPkg/Library/HdLcd/HdLcd.h
View File

@ -10,75 +10,75 @@
#define HDLCD_H_ #define HDLCD_H_
// HDLCD Controller Register Offsets // HDLCD Controller Register Offsets
#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000) #define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010) #define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014) #define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018) #define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C) #define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100) #define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104) #define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108) #define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C) #define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110) #define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200) #define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204) #define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208) #define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C) #define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210) #define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214) #define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218) #define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C) #define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220) #define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230) #define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240) #define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244) #define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248) #define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C) #define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
// HDLCD Values of registers // HDLCD Values of registers
// HDLCD Interrupt mask, clear and status register // HDLCD Interrupt mask, clear and status register
#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */ #define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */ #define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
#define HDLCD_SYNC BIT2 /* Vertical sync */ #define HDLCD_SYNC BIT2 /* Vertical sync */
#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */ #define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
// CLCD_CONTROL Control register // CLCD_CONTROL Control register
#define HDLCD_DISABLE 0 #define HDLCD_DISABLE 0
#define HDLCD_ENABLE BIT0 #define HDLCD_ENABLE BIT0
// Bus Options // Bus Options
#define HDLCD_BURST_1 BIT0 #define HDLCD_BURST_1 BIT0
#define HDLCD_BURST_2 BIT1 #define HDLCD_BURST_2 BIT1
#define HDLCD_BURST_4 BIT2 #define HDLCD_BURST_4 BIT2
#define HDLCD_BURST_8 BIT3 #define HDLCD_BURST_8 BIT3
#define HDLCD_BURST_16 BIT4 #define HDLCD_BURST_16 BIT4
// Polarities - HIGH // Polarities - HIGH
#define HDLCD_VSYNC_HIGH BIT0 #define HDLCD_VSYNC_HIGH BIT0
#define HDLCD_HSYNC_HIGH BIT1 #define HDLCD_HSYNC_HIGH BIT1
#define HDLCD_DATEN_HIGH BIT2 #define HDLCD_DATEN_HIGH BIT2
#define HDLCD_DATA_HIGH BIT3 #define HDLCD_DATA_HIGH BIT3
#define HDLCD_PXCLK_HIGH BIT4 #define HDLCD_PXCLK_HIGH BIT4
// Polarities - LOW (for completion and for ease of understanding the hardware settings) // Polarities - LOW (for completion and for ease of understanding the hardware settings)
#define HDLCD_VSYNC_LOW 0 #define HDLCD_VSYNC_LOW 0
#define HDLCD_HSYNC_LOW 0 #define HDLCD_HSYNC_LOW 0
#define HDLCD_DATEN_LOW 0 #define HDLCD_DATEN_LOW 0
#define HDLCD_DATA_LOW 0 #define HDLCD_DATA_LOW 0
#define HDLCD_PXCLK_LOW 0 #define HDLCD_PXCLK_LOW 0
// Default polarities // Default polarities
#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \ #define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \ HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \
HDLCD_VSYNC_HIGH) HDLCD_VSYNC_HIGH)
// Pixel Format // Pixel Format
#define HDLCD_LITTLE_ENDIAN (0 << 31) #define HDLCD_LITTLE_ENDIAN (0 << 31)
#define HDLCD_BIG_ENDIAN (1 << 31) #define HDLCD_BIG_ENDIAN (1 << 31)
// Number of bytes per pixel // Number of bytes per pixel
#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) #define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
#define HDLCD_PRODUCT_ID 0x1CDC #define HDLCD_PRODUCT_ID 0x1CDC
#endif /* HDLCD_H_ */ #endif /* HDLCD_H_ */

18
ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.c
View File

@ -20,7 +20,7 @@
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformInitializeDisplay ( LcdPlatformInitializeDisplay (
IN EFI_HANDLE Handle IN EFI_HANDLE Handle
) )
{ {
ASSERT (FALSE); ASSERT (FALSE);
@ -40,8 +40,8 @@ LcdPlatformInitializeDisplay (
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformGetVram ( LcdPlatformGetVram (
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, OUT EFI_PHYSICAL_ADDRESS *VramBaseAddress,
OUT UINTN* VramSize OUT UINTN *VramSize
) )
{ {
ASSERT (FALSE); ASSERT (FALSE);
@ -73,7 +73,7 @@ LcdPlatformGetMaxMode (
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformSetMode ( LcdPlatformSetMode (
IN UINT32 ModeNumber IN UINT32 ModeNumber
) )
{ {
ASSERT (FALSE); ASSERT (FALSE);
@ -116,9 +116,9 @@ LcdPlatformQueryMode (
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformGetTimings ( LcdPlatformGetTimings (
IN UINT32 ModeNumber, IN UINT32 ModeNumber,
OUT SCAN_TIMINGS **Horizontal, OUT SCAN_TIMINGS **Horizontal,
OUT SCAN_TIMINGS **Vertical OUT SCAN_TIMINGS **Vertical
) )
{ {
ASSERT (FALSE); ASSERT (FALSE);
@ -136,8 +136,8 @@ LcdPlatformGetTimings (
**/ **/
EFI_STATUS EFI_STATUS
LcdPlatformGetBpp ( LcdPlatformGetBpp (
IN UINT32 ModeNumber, IN UINT32 ModeNumber,
OUT LCD_BPP* Bpp OUT LCD_BPP *Bpp
) )
{ {
ASSERT (FALSE); ASSERT (FALSE);

6
ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.c
View File

@ -18,11 +18,11 @@ NorFlashPlatformInitialization (
EFI_STATUS EFI_STATUS
NorFlashPlatformGetDevices ( NorFlashPlatformGetDevices (
OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions, OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions,
OUT UINT32 *Count OUT UINT32 *Count
) )
{ {
*NorFlashDescriptions = NULL; *NorFlashDescriptions = NULL;
*Count = 0; *Count = 0;
return EFI_SUCCESS; return EFI_SUCCESS;
} }

23
ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c
View File

@ -35,15 +35,15 @@ SerialPortInitialize (
UINT8 DataBits; UINT8 DataBits;
EFI_STOP_BITS_TYPE StopBits; EFI_STOP_BITS_TYPE StopBits;
BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate); BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
ReceiveFifoDepth = 0; // Use default FIFO depth ReceiveFifoDepth = 0; // Use default FIFO depth
Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
DataBits = FixedPcdGet8 (PcdUartDefaultDataBits); DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits); StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
return PL011UartInitializePort ( return PL011UartInitializePort (
(UINTN)PcdGet64 (PcdSerialRegisterBase), (UINTN)PcdGet64 (PcdSerialRegisterBase),
PL011UartClockGetFreq(), PL011UartClockGetFreq (),
&BaudRate, &BaudRate,
&ReceiveFifoDepth, &ReceiveFifoDepth,
&Parity, &Parity,
@ -65,8 +65,8 @@ SerialPortInitialize (
UINTN UINTN
EFIAPI EFIAPI
SerialPortWrite ( SerialPortWrite (
IN UINT8 *Buffer, IN UINT8 *Buffer,
IN UINTN NumberOfBytes IN UINTN NumberOfBytes
) )
{ {
return PL011UartWrite ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes); return PL011UartWrite ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
@ -85,9 +85,9 @@ SerialPortWrite (
UINTN UINTN
EFIAPI EFIAPI
SerialPortRead ( SerialPortRead (
OUT UINT8 *Buffer, OUT UINT8 *Buffer,
IN UINTN NumberOfBytes IN UINTN NumberOfBytes
) )
{ {
return PL011UartRead ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes); return PL011UartRead ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
} }
@ -107,6 +107,7 @@ SerialPortPoll (
{ {
return PL011UartPoll ((UINTN)PcdGet64 (PcdSerialRegisterBase)); return PL011UartPoll ((UINTN)PcdGet64 (PcdSerialRegisterBase));
} }
/** /**
Set new attributes to PL011. Set new attributes to PL011.
@ -151,7 +152,7 @@ SerialPortSetAttributes (
{ {
return PL011UartInitializePort ( return PL011UartInitializePort (
(UINTN)PcdGet64 (PcdSerialRegisterBase), (UINTN)PcdGet64 (PcdSerialRegisterBase),
PL011UartClockGetFreq(), PL011UartClockGetFreq (),
BaudRate, BaudRate,
ReceiveFifoDepth, ReceiveFifoDepth,
Parity, Parity,

158
ArmPlatformPkg/Library/PL011UartLib/PL011Uart.h
View File

@ -9,106 +9,106 @@
#ifndef __PL011_UART_H__ #ifndef __PL011_UART_H__
#define __PL011_UART_H__ #define __PL011_UART_H__
#define PL011_VARIANT_ZTE 1 #define PL011_VARIANT_ZTE 1
// PL011 Registers // PL011 Registers
#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
#define UARTDR 0x004 #define UARTDR 0x004
#define UARTRSR 0x010 #define UARTRSR 0x010
#define UARTECR 0x010 #define UARTECR 0x010
#define UARTFR 0x014 #define UARTFR 0x014
#define UARTIBRD 0x024 #define UARTIBRD 0x024
#define UARTFBRD 0x028 #define UARTFBRD 0x028
#define UARTLCR_H 0x030 #define UARTLCR_H 0x030
#define UARTCR 0x034 #define UARTCR 0x034
#define UARTIFLS 0x038 #define UARTIFLS 0x038
#define UARTIMSC 0x040 #define UARTIMSC 0x040
#define UARTRIS 0x044 #define UARTRIS 0x044
#define UARTMIS 0x048 #define UARTMIS 0x048
#define UARTICR 0x04c #define UARTICR 0x04c
#define UARTDMACR 0x050 #define UARTDMACR 0x050
#else #else
#define UARTDR 0x000 #define UARTDR 0x000
#define UARTRSR 0x004 #define UARTRSR 0x004
#define UARTECR 0x004 #define UARTECR 0x004
#define UARTFR 0x018 #define UARTFR 0x018
#define UARTILPR 0x020 #define UARTILPR 0x020
#define UARTIBRD 0x024 #define UARTIBRD 0x024
#define UARTFBRD 0x028 #define UARTFBRD 0x028
#define UARTLCR_H 0x02C #define UARTLCR_H 0x02C
#define UARTCR 0x030 #define UARTCR 0x030
#define UARTIFLS 0x034 #define UARTIFLS 0x034
#define UARTIMSC 0x038 #define UARTIMSC 0x038
#define UARTRIS 0x03C #define UARTRIS 0x03C
#define UARTMIS 0x040 #define UARTMIS 0x040
#define UARTICR 0x044 #define UARTICR 0x044
#define UARTDMACR 0x048 #define UARTDMACR 0x048
#endif #endif
#define UARTPID0 0xFE0 #define UARTPID0 0xFE0
#define UARTPID1 0xFE4 #define UARTPID1 0xFE4
#define UARTPID2 0xFE8 #define UARTPID2 0xFE8
#define UARTPID3 0xFEC #define UARTPID3 0xFEC
// Data status bits // Data status bits
#define UART_DATA_ERROR_MASK 0x0F00 #define UART_DATA_ERROR_MASK 0x0F00
// Status reg bits // Status reg bits
#define UART_STATUS_ERROR_MASK 0x0F #define UART_STATUS_ERROR_MASK 0x0F
// Flag reg bits // Flag reg bits
#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
#define PL011_UARTFR_RI (1 << 0) // Ring indicator #define PL011_UARTFR_RI (1 << 0) // Ring indicator
#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full #define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty #define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
#define PL011_UARTFR_BUSY (1 << 8) // UART busy #define PL011_UARTFR_BUSY (1 << 8) // UART busy
#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
#define PL011_UARTFR_DSR (1 << 3) // Data set ready #define PL011_UARTFR_DSR (1 << 3) // Data set ready
#define PL011_UARTFR_CTS (1 << 1) // Clear to send #define PL011_UARTFR_CTS (1 << 1) // Clear to send
#else #else
#define PL011_UARTFR_RI (1 << 8) // Ring indicator #define PL011_UARTFR_RI (1 << 8) // Ring indicator
#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full #define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty #define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
#define PL011_UARTFR_BUSY (1 << 3) // UART busy #define PL011_UARTFR_BUSY (1 << 3) // UART busy
#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
#define PL011_UARTFR_DSR (1 << 1) // Data set ready #define PL011_UARTFR_DSR (1 << 1) // Data set ready
#define PL011_UARTFR_CTS (1 << 0) // Clear to send #define PL011_UARTFR_CTS (1 << 0) // Clear to send
#endif #endif
// Flag reg bits - alternative names // Flag reg bits - alternative names
#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE #define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF #define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF #define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE #define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY #define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
// Control reg bits // Control reg bits
#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable #define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable #define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
#define PL011_UARTCR_RTS (1 << 11) // Request to send #define PL011_UARTCR_RTS (1 << 11) // Request to send
#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready. #define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
#define PL011_UARTCR_RXE (1 << 9) // Receive enable #define PL011_UARTCR_RXE (1 << 9) // Receive enable
#define PL011_UARTCR_TXE (1 << 8) // Transmit enable #define PL011_UARTCR_TXE (1 << 8) // Transmit enable
#define PL011_UARTCR_LBE (1 << 7) // Loopback enable #define PL011_UARTCR_LBE (1 << 7) // Loopback enable
#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable #define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
// Line Control Register Bits // Line Control Register Bits
#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select #define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
#define PL011_UARTLCR_H_WLEN_8 (3 << 5) #define PL011_UARTLCR_H_WLEN_8 (3 << 5)
#define PL011_UARTLCR_H_WLEN_7 (2 << 5) #define PL011_UARTLCR_H_WLEN_7 (2 << 5)
#define PL011_UARTLCR_H_WLEN_6 (1 << 5) #define PL011_UARTLCR_H_WLEN_6 (1 << 5)
#define PL011_UARTLCR_H_WLEN_5 (0 << 5) #define PL011_UARTLCR_H_WLEN_5 (0 << 5)
#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable #define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select #define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select #define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable #define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
#define PL011_UARTLCR_H_BRK (1 << 0) // Send break #define PL011_UARTLCR_H_BRK (1 << 0) // Send break
#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF) #define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)
#define PL011_VER_R1P4 0x2 #define PL011_VER_R1P4 0x2
#endif #endif

180
ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c
View File

@ -25,7 +25,7 @@
// EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only // EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only
// control bit that is not supported. // control bit that is not supported.
// //
STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE; STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
/** /**
@ -73,16 +73,16 @@ PL011UartInitializePort (
IN OUT EFI_STOP_BITS_TYPE *StopBits IN OUT EFI_STOP_BITS_TYPE *StopBits
) )
{ {
UINT32 LineControl; UINT32 LineControl;
UINT32 Divisor; UINT32 Divisor;
UINT32 Integer; UINT32 Integer;
UINT32 Fractional; UINT32 Fractional;
UINT32 HardwareFifoDepth; UINT32 HardwareFifoDepth;
UINT32 UartPid2; UINT32 UartPid2;
HardwareFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); HardwareFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
if (HardwareFifoDepth == 0) { if (HardwareFifoDepth == 0) {
UartPid2 = MmioRead32 (UartBase + UARTPID2); UartPid2 = MmioRead32 (UartBase + UARTPID2);
HardwareFifoDepth = (PL011_UARTPID2_VER (UartPid2) > PL011_VER_R1P4) ? 32 : 16; HardwareFifoDepth = (PL011_UARTPID2_VER (UartPid2) > PL011_VER_R1P4) ? 32 : 16;
} }
@ -91,7 +91,7 @@ PL011UartInitializePort (
// down, there is no maximum FIFO size. // down, there is no maximum FIFO size.
if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) { if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {
// Enable FIFO // Enable FIFO
LineControl = PL011_UARTLCR_H_FEN; LineControl = PL011_UARTLCR_H_FEN;
*ReceiveFifoDepth = HardwareFifoDepth; *ReceiveFifoDepth = HardwareFifoDepth;
} else { } else {
// Disable FIFO // Disable FIFO
@ -104,67 +104,67 @@ PL011UartInitializePort (
// Parity // Parity
// //
switch (*Parity) { switch (*Parity) {
case DefaultParity: case DefaultParity:
*Parity = NoParity; *Parity = NoParity;
case NoParity: case NoParity:
// Nothing to do. Parity is disabled by default. // Nothing to do. Parity is disabled by default.
break; break;
case EvenParity: case EvenParity:
LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS); LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
break; break;
case OddParity: case OddParity:
LineControl |= PL011_UARTLCR_H_PEN; LineControl |= PL011_UARTLCR_H_PEN;
break; break;
case MarkParity: case MarkParity:
LineControl |= ( PL011_UARTLCR_H_PEN \ LineControl |= (PL011_UARTLCR_H_PEN \
| PL011_UARTLCR_H_SPS \ | PL011_UARTLCR_H_SPS \
| PL011_UARTLCR_H_EPS); | PL011_UARTLCR_H_EPS);
break; break;
case SpaceParity: case SpaceParity:
LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS); LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
break; break;
default: default:
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
} }
// //
// Data Bits // Data Bits
// //
switch (*DataBits) { switch (*DataBits) {
case 0: case 0:
*DataBits = 8; *DataBits = 8;
case 8: case 8:
LineControl |= PL011_UARTLCR_H_WLEN_8; LineControl |= PL011_UARTLCR_H_WLEN_8;
break; break;
case 7: case 7:
LineControl |= PL011_UARTLCR_H_WLEN_7; LineControl |= PL011_UARTLCR_H_WLEN_7;
break; break;
case 6: case 6:
LineControl |= PL011_UARTLCR_H_WLEN_6; LineControl |= PL011_UARTLCR_H_WLEN_6;
break; break;
case 5: case 5:
LineControl |= PL011_UARTLCR_H_WLEN_5; LineControl |= PL011_UARTLCR_H_WLEN_5;
break; break;
default: default:
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
} }
// //
// Stop Bits // Stop Bits
// //
switch (*StopBits) { switch (*StopBits) {
case DefaultStopBits: case DefaultStopBits:
*StopBits = OneStopBit; *StopBits = OneStopBit;
case OneStopBit: case OneStopBit:
// Nothing to do. One stop bit is enabled by default. // Nothing to do. One stop bit is enabled by default.
break; break;
case TwoStopBits: case TwoStopBits:
LineControl |= PL011_UARTLCR_H_STP2; LineControl |= PL011_UARTLCR_H_STP2;
break; break;
case OneFiveStopBits: case OneFiveStopBits:
// Only 1 or 2 stop bits are supported // Only 1 or 2 stop bits are supported
default: default:
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
} }
// Don't send the LineControl value to the PL011 yet, // Don't send the LineControl value to the PL011 yet,
@ -178,7 +178,7 @@ PL011UartInitializePort (
// If PL011 Integer value has been defined then always ignore the BAUD rate // If PL011 Integer value has been defined then always ignore the BAUD rate
if (FixedPcdGet32 (PL011UartInteger) != 0) { if (FixedPcdGet32 (PL011UartInteger) != 0) {
Integer = FixedPcdGet32 (PL011UartInteger); Integer = FixedPcdGet32 (PL011UartInteger);
Fractional = FixedPcdGet32 (PL011UartFractional); Fractional = FixedPcdGet32 (PL011UartFractional);
} else { } else {
// If BAUD rate is zero then replace it with the system default value // If BAUD rate is zero then replace it with the system default value
@ -188,12 +188,13 @@ PL011UartInitializePort (
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
} }
} }
if (0 == UartClkInHz) { if (0 == UartClkInHz) {
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
} }
Divisor = (UartClkInHz * 4) / *BaudRate; Divisor = (UartClkInHz * 4) / *BaudRate;
Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS; Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
Fractional = Divisor & FRACTION_PART_MASK; Fractional = Divisor & FRACTION_PART_MASK;
} }
@ -202,15 +203,17 @@ PL011UartInitializePort (
// and re-initialize only if the settings are different. // and re-initialize only if the settings are different.
// //
if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) && if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&
(MmioRead32 (UartBase + UARTLCR_H) == LineControl) && (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
(MmioRead32 (UartBase + UARTIBRD) == Integer) && (MmioRead32 (UartBase + UARTIBRD) == Integer) &&
(MmioRead32 (UartBase + UARTFBRD) == Fractional)) { (MmioRead32 (UartBase + UARTFBRD) == Fractional))
{
// Nothing to do - already initialized with correct attributes // Nothing to do - already initialized with correct attributes
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
// Wait for the end of transmission // Wait for the end of transmission
while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0); while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0) {
}
// Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed // Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed
// when the UART is enabled" // when the UART is enabled"
@ -227,8 +230,10 @@ PL011UartInitializePort (
MmioWrite32 (UartBase + UARTECR, 0); MmioWrite32 (UartBase + UARTECR, 0);
// Enable Tx, Rx, and UART overall // Enable Tx, Rx, and UART overall
MmioWrite32 (UartBase + UARTCR, MmioWrite32 (
PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN); UartBase + UARTCR,
PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN
);
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@ -263,8 +268,8 @@ PL011UartInitializePort (
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
PL011UartSetControl ( PL011UartSetControl (
IN UINTN UartBase, IN UINTN UartBase,
IN UINT32 Control IN UINT32 Control
) )
{ {
UINT32 Bits; UINT32 Bits;
@ -340,15 +345,14 @@ PL011UartSetControl (
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
PL011UartGetControl ( PL011UartGetControl (
IN UINTN UartBase, IN UINTN UartBase,
OUT UINT32 *Control OUT UINT32 *Control
) )
{ {
UINT32 FlagRegister; UINT32 FlagRegister;
UINT32 ControlRegister; UINT32 ControlRegister;
FlagRegister = MmioRead32 (UartBase + UARTFR);
FlagRegister = MmioRead32 (UartBase + UARTFR);
ControlRegister = MmioRead32 (UartBase + UARTCR); ControlRegister = MmioRead32 (UartBase + UARTCR);
*Control = 0; *Control = 0;
@ -386,7 +390,8 @@ PL011UartGetControl (
} }
if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
== (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) { == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
{
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE; *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
} }
@ -410,16 +415,17 @@ PL011UartGetControl (
UINTN UINTN
EFIAPI EFIAPI
PL011UartWrite ( PL011UartWrite (
IN UINTN UartBase, IN UINTN UartBase,
IN UINT8 *Buffer, IN UINT8 *Buffer,
IN UINTN NumberOfBytes IN UINTN NumberOfBytes
) )
{ {
UINT8* CONST Final = &Buffer[NumberOfBytes]; UINT8 *CONST Final = &Buffer[NumberOfBytes];
while (Buffer < Final) { while (Buffer < Final) {
// Wait until UART able to accept another char // Wait until UART able to accept another char
while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK)); while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK)) {
}
MmioWrite8 (UartBase + UARTDR, *Buffer++); MmioWrite8 (UartBase + UARTDR, *Buffer++);
} }
@ -440,15 +446,17 @@ PL011UartWrite (
UINTN UINTN
EFIAPI EFIAPI
PL011UartRead ( PL011UartRead (
IN UINTN UartBase, IN UINTN UartBase,
OUT UINT8 *Buffer, OUT UINT8 *Buffer,
IN UINTN NumberOfBytes IN UINTN NumberOfBytes
) )
{ {
UINTN Count; UINTN Count;
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) { for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0); while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0) {
}
*Buffer = MmioRead8 (UartBase + UARTDR); *Buffer = MmioRead8 (UartBase + UARTDR);
} }
@ -465,7 +473,7 @@ PL011UartRead (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
PL011UartPoll ( PL011UartPoll (
IN UINTN UartBase IN UINTN UartBase
) )
{ {
return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0); return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);

43
ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClock.h
View File

@ -6,34 +6,33 @@
**/ **/
#ifndef __PL031_REAL_TIME_CLOCK_H__ #ifndef __PL031_REAL_TIME_CLOCK_H__
#define __PL031_REAL_TIME_CLOCK_H__ #define __PL031_REAL_TIME_CLOCK_H__
// PL031 Registers // PL031 Registers
#define PL031_RTC_DR_DATA_REGISTER 0x000 #define PL031_RTC_DR_DATA_REGISTER 0x000
#define PL031_RTC_MR_MATCH_REGISTER 0x004 #define PL031_RTC_MR_MATCH_REGISTER 0x004
#define PL031_RTC_LR_LOAD_REGISTER 0x008 #define PL031_RTC_LR_LOAD_REGISTER 0x008
#define PL031_RTC_CR_CONTROL_REGISTER 0x00C #define PL031_RTC_CR_CONTROL_REGISTER 0x00C
#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010 #define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010
#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014 #define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014
#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018 #define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018
#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C #define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C
#define PL031_RTC_PERIPH_ID0 0xFE0 #define PL031_RTC_PERIPH_ID0 0xFE0
#define PL031_RTC_PERIPH_ID1 0xFE4 #define PL031_RTC_PERIPH_ID1 0xFE4
#define PL031_RTC_PERIPH_ID2 0xFE8 #define PL031_RTC_PERIPH_ID2 0xFE8
#define PL031_RTC_PERIPH_ID3 0xFEC #define PL031_RTC_PERIPH_ID3 0xFEC
#define PL031_RTC_PCELL_ID0 0xFF0 #define PL031_RTC_PCELL_ID0 0xFF0
#define PL031_RTC_PCELL_ID1 0xFF4 #define PL031_RTC_PCELL_ID1 0xFF4
#define PL031_RTC_PCELL_ID2 0xFF8 #define PL031_RTC_PCELL_ID2 0xFF8
#define PL031_RTC_PCELL_ID3 0xFFC #define PL031_RTC_PCELL_ID3 0xFFC
// PL031 Values // PL031 Values
#define PL031_RTC_ENABLED 0x00000001 #define PL031_RTC_ENABLED 0x00000001
#define PL031_SET_IRQ_MASK 0x00000001 #define PL031_SET_IRQ_MASK 0x00000001
#define PL031_IRQ_TRIGGERED 0x00000001 #define PL031_IRQ_TRIGGERED 0x00000001
#define PL031_CLEAR_IRQ 0x00000001 #define PL031_CLEAR_IRQ 0x00000001
#define PL031_COUNTS_PER_SECOND 1 #define PL031_COUNTS_PER_SECOND 1
#endif #endif

77
ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c
View File

@ -31,38 +31,40 @@
#include "PL031RealTimeClock.h" #include "PL031RealTimeClock.h"
STATIC BOOLEAN mPL031Initialized = FALSE; STATIC BOOLEAN mPL031Initialized = FALSE;
STATIC EFI_EVENT mRtcVirtualAddrChangeEvent; STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
STATIC UINTN mPL031RtcBase; STATIC UINTN mPL031RtcBase;
EFI_STATUS EFI_STATUS
IdentifyPL031 ( IdentifyPL031 (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
// Check if this is a PrimeCell Peripheral // Check if this is a PrimeCell Peripheral
if ( (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID0) != 0x0D) if ( (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID0) != 0x0D)
|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID1) != 0xF0) || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID1) != 0xF0)
|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID2) != 0x05) || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID2) != 0x05)
|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID3) != 0xB1)) { || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID3) != 0xB1))
{
Status = EFI_NOT_FOUND; Status = EFI_NOT_FOUND;
goto EXIT; goto EXIT;
} }
// Check if this PrimeCell Peripheral is the PL031 Real Time Clock // Check if this PrimeCell Peripheral is the PL031 Real Time Clock
if ( (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID0) != 0x31) if ( (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID0) != 0x31)
|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID1) != 0x10) || (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID1) != 0x10)
|| ((MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID2) & 0xF) != 0x04) || ((MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID2) & 0xF) != 0x04)
|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID3) != 0x00)) { || (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID3) != 0x00))
{
Status = EFI_NOT_FOUND; Status = EFI_NOT_FOUND;
goto EXIT; goto EXIT;
} }
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
EXIT: EXIT:
return Status; return Status;
} }
@ -71,10 +73,10 @@ InitializePL031 (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
// Prepare the hardware // Prepare the hardware
Status = IdentifyPL031(); Status = IdentifyPL031 ();
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
goto EXIT; goto EXIT;
} }
@ -96,7 +98,7 @@ InitializePL031 (
mPL031Initialized = TRUE; mPL031Initialized = TRUE;
EXIT: EXIT:
return Status; return Status;
} }
@ -117,8 +119,8 @@ InitializePL031 (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LibGetTime ( LibGetTime (
OUT EFI_TIME *Time, OUT EFI_TIME *Time,
OUT EFI_TIME_CAPABILITIES *Capabilities OUT EFI_TIME_CAPABILITIES *Capabilities
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -154,17 +156,16 @@ LibGetTime (
// Update the Capabilities info // Update the Capabilities info
if (Capabilities != NULL) { if (Capabilities != NULL) {
// PL031 runs at frequency 1Hz // PL031 runs at frequency 1Hz
Capabilities->Resolution = PL031_COUNTS_PER_SECOND; Capabilities->Resolution = PL031_COUNTS_PER_SECOND;
// Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000 // Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000
Capabilities->Accuracy = (UINT32)PcdGet32 (PcdPL031RtcPpmAccuracy); Capabilities->Accuracy = (UINT32)PcdGet32 (PcdPL031RtcPpmAccuracy);
// FALSE: Setting the time does not clear the values below the resolution level // FALSE: Setting the time does not clear the values below the resolution level
Capabilities->SetsToZero = FALSE; Capabilities->SetsToZero = FALSE;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Sets the current local time and date information. Sets the current local time and date information.
@ -178,7 +179,7 @@ LibGetTime (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LibSetTime ( LibSetTime (
IN EFI_TIME *Time IN EFI_TIME *Time
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -217,7 +218,6 @@ LibSetTime (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Returns the current wakeup alarm clock setting. Returns the current wakeup alarm clock setting.
@ -233,16 +233,15 @@ LibSetTime (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LibGetWakeupTime ( LibGetWakeupTime (
OUT BOOLEAN *Enabled, OUT BOOLEAN *Enabled,
OUT BOOLEAN *Pending, OUT BOOLEAN *Pending,
OUT EFI_TIME *Time OUT EFI_TIME *Time
) )
{ {
// Not a required feature // Not a required feature
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
/** /**
Sets the system wakeup alarm clock time. Sets the system wakeup alarm clock time.
@ -259,8 +258,8 @@ LibGetWakeupTime (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LibSetWakeupTime ( LibSetWakeupTime (
IN BOOLEAN Enabled, IN BOOLEAN Enabled,
OUT EFI_TIME *Time OUT EFI_TIME *Time
) )
{ {
// Not a required feature // Not a required feature
@ -278,8 +277,8 @@ LibSetWakeupTime (
VOID VOID
EFIAPI EFIAPI
LibRtcVirtualNotifyEvent ( LibRtcVirtualNotifyEvent (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
// //
@ -288,7 +287,7 @@ LibRtcVirtualNotifyEvent (
// to virtual address. After the OS transitions to calling in virtual mode, all future // to virtual address. After the OS transitions to calling in virtual mode, all future
// runtime calls will be made in virtual mode. // runtime calls will be made in virtual mode.
// //
EfiConvertPointer (0x0, (VOID**)&mPL031RtcBase); EfiConvertPointer (0x0, (VOID **)&mPL031RtcBase);
return; return;
} }
@ -305,12 +304,12 @@ LibRtcVirtualNotifyEvent (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LibRtcInitialize ( LibRtcInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_HANDLE Handle; EFI_HANDLE Handle;
// Initialize RTC Base Address // Initialize RTC Base Address
mPL031RtcBase = PcdGet32 (PcdPL031RtcBase); mPL031RtcBase = PcdGet32 (PcdPL031RtcBase);
@ -318,7 +317,8 @@ LibRtcInitialize (
// Declare the controller as EFI_MEMORY_RUNTIME // Declare the controller as EFI_MEMORY_RUNTIME
Status = gDS->AddMemorySpace ( Status = gDS->AddMemorySpace (
EfiGcdMemoryTypeMemoryMappedIo, EfiGcdMemoryTypeMemoryMappedIo,
mPL031RtcBase, SIZE_4KB, mPL031RtcBase,
SIZE_4KB,
EFI_MEMORY_UC | EFI_MEMORY_RUNTIME EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -334,9 +334,10 @@ LibRtcInitialize (
Handle = NULL; Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&Handle, &Handle,
&gEfiRealTimeClockArchProtocolGuid, NULL, &gEfiRealTimeClockArchProtocolGuid,
NULL,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// //

38
ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c
View File

@ -26,20 +26,25 @@ LcdIdentify (
VOID VOID
) )
{ {
DEBUG ((DEBUG_WARN, "Probing ID registers at 0x%lx for a PL111\n", DEBUG ((
PL111_REG_CLCD_PERIPH_ID_0)); DEBUG_WARN,
"Probing ID registers at 0x%lx for a PL111\n",
PL111_REG_CLCD_PERIPH_ID_0
));
// Check if this is a PL111 // Check if this is a PL111
if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 && if ((MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0) &&
MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 && (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1) &&
(MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 && ((MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2) &&
MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 && (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3) &&
MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 && (MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0) &&
MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 && (MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1) &&
MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 && (MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2) &&
MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) { (MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3))
{
return EFI_SUCCESS; return EFI_SUCCESS;
} }
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
@ -51,7 +56,7 @@ LcdIdentify (
**/ **/
EFI_STATUS EFI_STATUS
LcdInitialize ( LcdInitialize (
IN EFI_PHYSICAL_ADDRESS VramBaseAddress IN EFI_PHYSICAL_ADDRESS VramBaseAddress
) )
{ {
// Define start of the VRAM. This never changes for any graphics mode // Define start of the VRAM. This never changes for any graphics mode
@ -76,11 +81,11 @@ LcdSetMode (
IN UINT32 ModeNumber IN UINT32 ModeNumber
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
SCAN_TIMINGS *Horizontal; SCAN_TIMINGS *Horizontal;
SCAN_TIMINGS *Vertical; SCAN_TIMINGS *Vertical;
UINT32 LcdControl; UINT32 LcdControl;
LCD_BPP LcdBpp; LCD_BPP LcdBpp;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;
@ -148,6 +153,7 @@ LcdSetMode (
if (ModeInfo.PixelFormat == PixelBlueGreenRedReserved8BitPerColor) { if (ModeInfo.PixelFormat == PixelBlueGreenRedReserved8BitPerColor) {
LcdControl |= PL111_CTRL_BGR; LcdControl |= PL111_CTRL_BGR;
} }
MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl); MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
return EFI_SUCCESS; return EFI_SUCCESS;

178
ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h
View File

@ -16,39 +16,39 @@
**********************************************************************/ **********************************************************************/
// Controller Register Offsets // Controller Register Offsets
#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) #define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) #define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) #define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) #define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) #define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) #define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) #define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) #define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) #define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) #define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) #define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) #define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) #define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) #define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
// Identification Register Offsets // Identification Register Offsets
#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) #define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) #define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) #define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) #define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) #define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) #define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) #define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) #define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
#define PL111_CLCD_PERIPH_ID_0 0x11 #define PL111_CLCD_PERIPH_ID_0 0x11
#define PL111_CLCD_PERIPH_ID_1 0x11 #define PL111_CLCD_PERIPH_ID_1 0x11
#define PL111_CLCD_PERIPH_ID_2 0x04 #define PL111_CLCD_PERIPH_ID_2 0x04
#define PL111_CLCD_PERIPH_ID_3 0x00 #define PL111_CLCD_PERIPH_ID_3 0x00
#define PL111_CLCD_P_CELL_ID_0 0x0D #define PL111_CLCD_P_CELL_ID_0 0x0D
#define PL111_CLCD_P_CELL_ID_1 0xF0 #define PL111_CLCD_P_CELL_ID_1 0xF0
#define PL111_CLCD_P_CELL_ID_2 0x05 #define PL111_CLCD_P_CELL_ID_2 0x05
#define PL111_CLCD_P_CELL_ID_3 0xB1 #define PL111_CLCD_P_CELL_ID_3 0xB1
/**********************************************************************/ /**********************************************************************/
@ -61,83 +61,83 @@
/**********************************************************************/ /**********************************************************************/
// Register: PL111_REG_LCD_TIMING_0 // Register: PL111_REG_LCD_TIMING_0
#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) #define HOR_AXIS_PANEL(hbp, hfp, hsw, hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
// Register: PL111_REG_LCD_TIMING_1 // Register: PL111_REG_LCD_TIMING_1
#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) #define VER_AXIS_PANEL(vbp, vfp, vsw, ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
// Register: PL111_REG_LCD_TIMING_2 // Register: PL111_REG_LCD_TIMING_2
#define PL111_BIT_SHIFT_PCD_HI 27 #define PL111_BIT_SHIFT_PCD_HI 27
#define PL111_BIT_SHIFT_BCD 26 #define PL111_BIT_SHIFT_BCD 26
#define PL111_BIT_SHIFT_CPL 16 #define PL111_BIT_SHIFT_CPL 16
#define PL111_BIT_SHIFT_IOE 14 #define PL111_BIT_SHIFT_IOE 14
#define PL111_BIT_SHIFT_IPC 13 #define PL111_BIT_SHIFT_IPC 13
#define PL111_BIT_SHIFT_IHS 12 #define PL111_BIT_SHIFT_IHS 12
#define PL111_BIT_SHIFT_IVS 11 #define PL111_BIT_SHIFT_IVS 11
#define PL111_BIT_SHIFT_ACB 6 #define PL111_BIT_SHIFT_ACB 6
#define PL111_BIT_SHIFT_CLKSEL 5 #define PL111_BIT_SHIFT_CLKSEL 5
#define PL111_BIT_SHIFT_PCD_LO 0 #define PL111_BIT_SHIFT_PCD_LO 0
#define PL111_BCD (1 << 26) #define PL111_BCD (1 << 26)
#define PL111_IPC (1 << 13) #define PL111_IPC (1 << 13)
#define PL111_IHS (1 << 12) #define PL111_IHS (1 << 12)
#define PL111_IVS (1 << 11) #define PL111_IVS (1 << 11)
#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) #define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
// Register: PL111_REG_LCD_TIMING_3 // Register: PL111_REG_LCD_TIMING_3
#define PL111_BIT_SHIFT_LEE 16 #define PL111_BIT_SHIFT_LEE 16
#define PL111_BIT_SHIFT_LED 0 #define PL111_BIT_SHIFT_LED 0
#define PL111_CTRL_WATERMARK (1 << 16) #define PL111_CTRL_WATERMARK (1 << 16)
#define PL111_CTRL_LCD_V_COMP (1 << 12) #define PL111_CTRL_LCD_V_COMP (1 << 12)
#define PL111_CTRL_LCD_PWR (1 << 11) #define PL111_CTRL_LCD_PWR (1 << 11)
#define PL111_CTRL_BEPO (1 << 10) #define PL111_CTRL_BEPO (1 << 10)
#define PL111_CTRL_BEBO (1 << 9) #define PL111_CTRL_BEBO (1 << 9)
#define PL111_CTRL_BGR (1 << 8) #define PL111_CTRL_BGR (1 << 8)
#define PL111_CTRL_LCD_DUAL (1 << 7) #define PL111_CTRL_LCD_DUAL (1 << 7)
#define PL111_CTRL_LCD_MONO_8 (1 << 6) #define PL111_CTRL_LCD_MONO_8 (1 << 6)
#define PL111_CTRL_LCD_TFT (1 << 5) #define PL111_CTRL_LCD_TFT (1 << 5)
#define PL111_CTRL_LCD_BW (1 << 4) #define PL111_CTRL_LCD_BW (1 << 4)
#define PL111_CTRL_LCD_1BPP (0 << 1) #define PL111_CTRL_LCD_1BPP (0 << 1)
#define PL111_CTRL_LCD_2BPP (1 << 1) #define PL111_CTRL_LCD_2BPP (1 << 1)
#define PL111_CTRL_LCD_4BPP (2 << 1) #define PL111_CTRL_LCD_4BPP (2 << 1)
#define PL111_CTRL_LCD_8BPP (3 << 1) #define PL111_CTRL_LCD_8BPP (3 << 1)
#define PL111_CTRL_LCD_16BPP (4 << 1) #define PL111_CTRL_LCD_16BPP (4 << 1)
#define PL111_CTRL_LCD_24BPP (5 << 1) #define PL111_CTRL_LCD_24BPP (5 << 1)
#define PL111_CTRL_LCD_16BPP_565 (6 << 1) #define PL111_CTRL_LCD_16BPP_565 (6 << 1)
#define PL111_CTRL_LCD_12BPP_444 (7 << 1) #define PL111_CTRL_LCD_12BPP_444 (7 << 1)
#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) #define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
#define PL111_CTRL_LCD_EN 1 #define PL111_CTRL_LCD_EN 1
/**********************************************************************/ /**********************************************************************/
// Register: PL111_REG_LCD_TIMING_0 // Register: PL111_REG_LCD_TIMING_0
#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) #define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) #define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
// Register: PL111_REG_LCD_TIMING_1 // Register: PL111_REG_LCD_TIMING_1
#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) #define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) #define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) #define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) #define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
// Register: PL111_REG_LCD_TIMING_2 // Register: PL111_REG_LCD_TIMING_2
#define PL111_BIT_MASK_PCD_HI 0xF8000000 #define PL111_BIT_MASK_PCD_HI 0xF8000000
#define PL111_BIT_MASK_BCD 0x04000000 #define PL111_BIT_MASK_BCD 0x04000000
#define PL111_BIT_MASK_CPL 0x03FF0000 #define PL111_BIT_MASK_CPL 0x03FF0000
#define PL111_BIT_MASK_IOE 0x00004000 #define PL111_BIT_MASK_IOE 0x00004000
#define PL111_BIT_MASK_IPC 0x00002000 #define PL111_BIT_MASK_IPC 0x00002000
#define PL111_BIT_MASK_IHS 0x00001000 #define PL111_BIT_MASK_IHS 0x00001000
#define PL111_BIT_MASK_IVS 0x00000800 #define PL111_BIT_MASK_IVS 0x00000800
#define PL111_BIT_MASK_ACB 0x000007C0 #define PL111_BIT_MASK_ACB 0x000007C0
#define PL111_BIT_MASK_CLKSEL 0x00000020 #define PL111_BIT_MASK_CLKSEL 0x00000020
#define PL111_BIT_MASK_PCD_LO 0x0000001F #define PL111_BIT_MASK_PCD_LO 0x0000001F
// Register: PL111_REG_LCD_TIMING_3 // Register: PL111_REG_LCD_TIMING_3
#define PL111_BIT_MASK_LEE 0x00010000 #define PL111_BIT_MASK_LEE 0x00010000
#define PL111_BIT_MASK_LED 0x0000007F #define PL111_BIT_MASK_LED 0x0000007F
#endif /* _PL111LCD_H__ */ #endif /* _PL111LCD_H__ */

8
ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointer.c
View File

@ -25,11 +25,9 @@ PrePeiGetHobList (
VOID VOID
) )
{ {
return (VOID *)ArmReadTpidrurw(); return (VOID *)ArmReadTpidrurw ();
} }
/** /**
Updates the pointer to the HOB list. Updates the pointer to the HOB list.
@ -39,10 +37,10 @@ PrePeiGetHobList (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PrePeiSetHobList ( PrePeiSetHobList (
IN VOID *HobList IN VOID *HobList
) )
{ {
ArmWriteTpidrurw((UINTN)HobList); ArmWriteTpidrurw ((UINTN)HobList);
return EFI_SUCCESS; return EFI_SUCCESS;
} }

107
ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.c
View File

@ -26,12 +26,11 @@ InitMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
) )
{ {
VOID *TranslationTableBase;
UINTN TranslationTableSize;
RETURN_STATUS Status;
VOID *TranslationTableBase; // Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
UINTN TranslationTableSize;
RETURN_STATUS Status;
//Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
// DRAM (even at the top of DRAM as it is the first permanent memory allocation) // DRAM (even at the top of DRAM as it is the first permanent memory allocation)
Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize); Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -58,18 +57,18 @@ Returns:
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MemoryPeim ( MemoryPeim (
IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
IN UINT64 UefiMemorySize IN UINT64 UefiMemorySize
) )
{ {
ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
UINT64 ResourceLength; UINT64 ResourceLength;
EFI_PEI_HOB_POINTERS NextHob; EFI_PEI_HOB_POINTERS NextHob;
EFI_PHYSICAL_ADDRESS FdTop; EFI_PHYSICAL_ADDRESS FdTop;
EFI_PHYSICAL_ADDRESS SystemMemoryTop; EFI_PHYSICAL_ADDRESS SystemMemoryTop;
EFI_PHYSICAL_ADDRESS ResourceTop; EFI_PHYSICAL_ADDRESS ResourceTop;
BOOLEAN Found; BOOLEAN Found;
// Get Virtual Memory Map from the Platform Library // Get Virtual Memory Map from the Platform Library
ArmPlatformGetVirtualMemoryMap (&MemoryTable); ArmPlatformGetVirtualMemoryMap (&MemoryTable);
@ -81,18 +80,18 @@ MemoryPeim (
// Now, the permanent memory has been installed, we can call AllocatePages() // Now, the permanent memory has been installed, we can call AllocatePages()
// //
ResourceAttributes = ( ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED EFI_RESOURCE_ATTRIBUTE_TESTED
); );
// //
// Check if the resource for the main system memory has been declared // Check if the resource for the main system memory has been declared
// //
Found = FALSE; Found = FALSE;
NextHob.Raw = GetHobList (); NextHob.Raw = GetHobList ();
while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) { while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) && if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
@ -102,17 +101,18 @@ MemoryPeim (
Found = TRUE; Found = TRUE;
break; break;
} }
NextHob.Raw = GET_NEXT_HOB (NextHob); NextHob.Raw = GET_NEXT_HOB (NextHob);
} }
if (!Found) { if (!Found) {
// Reserved the memory space occupied by the firmware volume // Reserved the memory space occupied by the firmware volume
BuildResourceDescriptorHob ( BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY, EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes, ResourceAttributes,
PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemoryBase),
PcdGet64 (PcdSystemMemorySize) PcdGet64 (PcdSystemMemorySize)
); );
} }
// //
@ -120,7 +120,7 @@ MemoryPeim (
// //
SystemMemoryTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemoryBase) + (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemorySize); SystemMemoryTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemoryBase) + (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemorySize);
FdTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdFdBaseAddress) + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFdSize); FdTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdFdBaseAddress) + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFdSize);
// EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE // EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE
// core to overwrite this area we must create a memory allocation HOB for the region, // core to overwrite this area we must create a memory allocation HOB for the region,
@ -136,27 +136,31 @@ MemoryPeim (
(FdTop <= NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength)) (FdTop <= NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))
{ {
ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute; ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
ResourceLength = NextHob.ResourceDescriptor->ResourceLength; ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength; ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
if (PcdGet64 (PcdFdBaseAddress) == NextHob.ResourceDescriptor->PhysicalStart) { if (PcdGet64 (PcdFdBaseAddress) == NextHob.ResourceDescriptor->PhysicalStart) {
if (SystemMemoryTop != FdTop) { if (SystemMemoryTop != FdTop) {
// Create the System Memory HOB for the firmware // Create the System Memory HOB for the firmware
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, BuildResourceDescriptorHob (
ResourceAttributes, EFI_RESOURCE_SYSTEM_MEMORY,
PcdGet64 (PcdFdBaseAddress), ResourceAttributes,
PcdGet32 (PcdFdSize)); PcdGet64 (PcdFdBaseAddress),
PcdGet32 (PcdFdSize)
);
// Top of the FD is system memory available for UEFI // Top of the FD is system memory available for UEFI
NextHob.ResourceDescriptor->PhysicalStart += PcdGet32(PcdFdSize); NextHob.ResourceDescriptor->PhysicalStart += PcdGet32 (PcdFdSize);
NextHob.ResourceDescriptor->ResourceLength -= PcdGet32(PcdFdSize); NextHob.ResourceDescriptor->ResourceLength -= PcdGet32 (PcdFdSize);
} }
} else { } else {
// Create the System Memory HOB for the firmware // Create the System Memory HOB for the firmware
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, BuildResourceDescriptorHob (
ResourceAttributes, EFI_RESOURCE_SYSTEM_MEMORY,
PcdGet64 (PcdFdBaseAddress), ResourceAttributes,
PcdGet32 (PcdFdSize)); PcdGet64 (PcdFdBaseAddress),
PcdGet32 (PcdFdSize)
);
// Update the HOB // Update the HOB
NextHob.ResourceDescriptor->ResourceLength = PcdGet64 (PcdFdBaseAddress) - NextHob.ResourceDescriptor->PhysicalStart; NextHob.ResourceDescriptor->ResourceLength = PcdGet64 (PcdFdBaseAddress) - NextHob.ResourceDescriptor->PhysicalStart;
@ -164,25 +168,30 @@ MemoryPeim (
// If there is some memory available on the top of the FD then create a HOB // If there is some memory available on the top of the FD then create a HOB
if (FdTop < NextHob.ResourceDescriptor->PhysicalStart + ResourceLength) { if (FdTop < NextHob.ResourceDescriptor->PhysicalStart + ResourceLength) {
// Create the System Memory HOB for the remaining region (top of the FD) // Create the System Memory HOB for the remaining region (top of the FD)
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, BuildResourceDescriptorHob (
ResourceAttributes, EFI_RESOURCE_SYSTEM_MEMORY,
FdTop, ResourceAttributes,
ResourceTop - FdTop); FdTop,
ResourceTop - FdTop
);
} }
} }
// Mark the memory covering the Firmware Device as boot services data // Mark the memory covering the Firmware Device as boot services data
BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress), BuildMemoryAllocationHob (
PcdGet32 (PcdFdSize), PcdGet64 (PcdFdBaseAddress),
EfiBootServicesData); PcdGet32 (PcdFdSize),
EfiBootServicesData
);
Found = TRUE; Found = TRUE;
break; break;
} }
NextHob.Raw = GET_NEXT_HOB (NextHob); NextHob.Raw = GET_NEXT_HOB (NextHob);
} }
ASSERT(Found); ASSERT (Found);
} }
// Build Memory Allocation Hob // Build Memory Allocation Hob

23
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.c
View File

@ -27,8 +27,8 @@
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MemoryPeim ( MemoryPeim (
IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
IN UINT64 UefiMemorySize IN UINT64 UefiMemorySize
); );
// May want to put this into a library so you only need the PCD settings if you are using the feature? // May want to put this into a library so you only need the PCD settings if you are using the feature?
@ -37,7 +37,7 @@ BuildMemoryTypeInformationHob (
VOID VOID
) )
{ {
EFI_MEMORY_TYPE_INFORMATION Info[10]; EFI_MEMORY_TYPE_INFORMATION Info[10];
Info[0].Type = EfiACPIReclaimMemory; Info[0].Type = EfiACPIReclaimMemory;
Info[0].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory); Info[0].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory);
@ -88,12 +88,12 @@ InitializeMemory (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN SystemMemoryBase; UINTN SystemMemoryBase;
UINT64 SystemMemoryTop; UINT64 SystemMemoryTop;
UINTN FdBase; UINTN FdBase;
UINTN FdTop; UINTN FdTop;
UINTN UefiMemoryBase; UINTN UefiMemoryBase;
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Memory Init PEIM Loaded\n")); DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Memory Init PEIM Loaded\n"));
@ -102,12 +102,13 @@ InitializeMemory (
ASSERT (PcdGet64 (PcdSystemMemoryBase) < (UINT64)MAX_ALLOC_ADDRESS); ASSERT (PcdGet64 (PcdSystemMemoryBase) < (UINT64)MAX_ALLOC_ADDRESS);
SystemMemoryBase = (UINTN)PcdGet64 (PcdSystemMemoryBase); SystemMemoryBase = (UINTN)PcdGet64 (PcdSystemMemoryBase);
SystemMemoryTop = SystemMemoryBase + PcdGet64 (PcdSystemMemorySize); SystemMemoryTop = SystemMemoryBase + PcdGet64 (PcdSystemMemorySize);
if (SystemMemoryTop - 1 > MAX_ALLOC_ADDRESS) { if (SystemMemoryTop - 1 > MAX_ALLOC_ADDRESS) {
SystemMemoryTop = (UINT64)MAX_ALLOC_ADDRESS + 1; SystemMemoryTop = (UINT64)MAX_ALLOC_ADDRESS + 1;
} }
FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress); FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize); FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);
// //
// Declare the UEFI memory to PEI // Declare the UEFI memory to PEI

4
ArmPlatformPkg/PlatformPei/PlatformPeim.c
View File

@ -76,8 +76,8 @@ InitializePlatformPeim (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_BOOT_MODE BootMode; EFI_BOOT_MODE BootMode;
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Platform PEIM Loaded\n")); DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Platform PEIM Loaded\n"));

44
ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
View File

@ -14,33 +14,33 @@
VOID VOID
PeiCommonExceptionEntry ( PeiCommonExceptionEntry (
IN UINT32 Entry, IN UINT32 Entry,
IN UINTN LR IN UINTN LR
) )
{ {
CHAR8 Buffer[100]; CHAR8 Buffer[100];
UINTN CharCount; UINTN CharCount;
switch (Entry) { switch (Entry) {
case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS: case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Synchronous Exception at 0x%X\n\r", LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Synchronous Exception at 0x%X\n\r", LR);
break; break;
case EXCEPT_AARCH64_IRQ: case EXCEPT_AARCH64_IRQ:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r", LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "IRQ Exception at 0x%X\n\r", LR);
break; break;
case EXCEPT_AARCH64_FIQ: case EXCEPT_AARCH64_FIQ:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r", LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "FIQ Exception at 0x%X\n\r", LR);
break; break;
case EXCEPT_AARCH64_SERROR: case EXCEPT_AARCH64_SERROR:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SError/Abort Exception at 0x%X\n\r", LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "SError/Abort Exception at 0x%X\n\r", LR);
break; break;
default: default:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r", LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Unknown Exception at 0x%X\n\r", LR);
break; break;
} }
SerialPortWrite ((UINT8 *) Buffer, CharCount); SerialPortWrite ((UINT8 *)Buffer, CharCount);
while(1); while (1) {
}
} }

69
ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c
View File

@ -14,43 +14,44 @@
VOID VOID
PeiCommonExceptionEntry ( PeiCommonExceptionEntry (
IN UINT32 Entry, IN UINT32 Entry,
IN UINTN LR IN UINTN LR
) )
{ {
CHAR8 Buffer[100]; CHAR8 Buffer[100];
UINTN CharCount; UINTN CharCount;
switch (Entry) { switch (Entry) {
case 0: case 0:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Reset Exception at 0x%X\n\r", LR);
break; break;
case 1: case 1:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Undefined Exception at 0x%X\n\r", LR);
break; break;
case 2: case 2:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "SWI Exception at 0x%X\n\r", LR);
break; break;
case 3: case 3:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "PrefetchAbort Exception at 0x%X\n\r", LR);
break; break;
case 4: case 4:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "DataAbort Exception at 0x%X\n\r", LR);
break; break;
case 5: case 5:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Reserved Exception at 0x%X\n\r", LR);
break; break;
case 6: case 6:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "IRQ Exception at 0x%X\n\r", LR);
break; break;
case 7: case 7:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "FIQ Exception at 0x%X\n\r", LR);
break; break;
default: default:
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Unknown Exception at 0x%X\n\r", LR);
break; break;
} }
SerialPortWrite ((UINT8 *) Buffer, CharCount);
while(1);
}
SerialPortWrite ((UINT8 *)Buffer, CharCount);
while (1) {
}
}

47
ArmPlatformPkg/PrePeiCore/MainMPCore.c
View File

@ -24,7 +24,7 @@
VOID VOID
EFIAPI EFIAPI
SecondaryMain ( SecondaryMain (
IN UINTN MpId IN UINTN MpId
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -37,18 +37,21 @@ SecondaryMain (
ARM_CORE_INFO *ArmCoreInfoTable; ARM_CORE_INFO *ArmCoreInfoTable;
UINT32 ClusterId; UINT32 ClusterId;
UINT32 CoreId; UINT32 CoreId;
VOID (*SecondaryStart)(VOID);
UINTN SecondaryEntryAddr;
UINTN AcknowledgeInterrupt;
UINTN InterruptId;
ClusterId = GET_CLUSTER_ID(MpId); VOID (*SecondaryStart)(
CoreId = GET_CORE_ID(MpId); VOID
);
UINTN SecondaryEntryAddr;
UINTN AcknowledgeInterrupt;
UINTN InterruptId;
ClusterId = GET_CLUSTER_ID (MpId);
CoreId = GET_CORE_ID (MpId);
// Get the gArmMpCoreInfoPpiGuid // Get the gArmMpCoreInfoPpiGuid
PpiListSize = 0; PpiListSize = 0;
ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList); ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR); PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
for (Index = 0; Index < PpiListCount; Index++, PpiList++) { for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) { if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
break; break;
@ -59,8 +62,8 @@ SecondaryMain (
ASSERT (Index != PpiListCount); ASSERT (Index != PpiListCount);
ArmMpCoreInfoPpi = PpiList->Ppi; ArmMpCoreInfoPpi = PpiList->Ppi;
ArmCoreCount = 0; ArmCoreCount = 0;
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable); Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Find the core in the ArmCoreTable // Find the core in the ArmCoreTable
@ -92,11 +95,11 @@ SecondaryMain (
} while (SecondaryEntryAddr == 0); } while (SecondaryEntryAddr == 0);
// Jump to secondary core entry point. // Jump to secondary core entry point.
SecondaryStart = (VOID (*)())SecondaryEntryAddr; SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
SecondaryStart(); SecondaryStart ();
// The secondaries shouldn't reach here // The secondaries shouldn't reach here
ASSERT(FALSE); ASSERT (FALSE);
} }
VOID VOID
@ -105,26 +108,26 @@ PrimaryMain (
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
) )
{ {
EFI_SEC_PEI_HAND_OFF SecCoreData; EFI_SEC_PEI_HAND_OFF SecCoreData;
UINTN PpiListSize; UINTN PpiListSize;
EFI_PEI_PPI_DESCRIPTOR *PpiList; EFI_PEI_PPI_DESCRIPTOR *PpiList;
UINTN TemporaryRamBase; UINTN TemporaryRamBase;
UINTN TemporaryRamSize; UINTN TemporaryRamSize;
CreatePpiList (&PpiListSize, &PpiList); CreatePpiList (&PpiListSize, &PpiList);
// Enable the GIC Distributor // Enable the GIC Distributor
ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase)); ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) { if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces // Sending SGI to all the Secondary CPU interfaces
ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId)); ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
} }
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
// the base of the primary core stack // the base of the primary core stack
PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT); PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize; TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize; TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
@ -133,7 +136,7 @@ PrimaryMain (
// Note: this must be in sync with the stuff in the asm file // Note: this must be in sync with the stuff in the asm file
// Note also: HOBs (pei temp ram) MUST be above stack // Note also: HOBs (pei temp ram) MUST be above stack
// //
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress); SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize); SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack) SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)

18
ArmPlatformPkg/PrePeiCore/MainUniCore.c
View File

@ -11,10 +11,10 @@
VOID VOID
EFIAPI EFIAPI
SecondaryMain ( SecondaryMain (
IN UINTN MpId IN UINTN MpId
) )
{ {
ASSERT(FALSE); ASSERT (FALSE);
} }
VOID VOID
@ -23,17 +23,17 @@ PrimaryMain (
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
) )
{ {
EFI_SEC_PEI_HAND_OFF SecCoreData; EFI_SEC_PEI_HAND_OFF SecCoreData;
UINTN PpiListSize; UINTN PpiListSize;
EFI_PEI_PPI_DESCRIPTOR *PpiList; EFI_PEI_PPI_DESCRIPTOR *PpiList;
UINTN TemporaryRamBase; UINTN TemporaryRamBase;
UINTN TemporaryRamSize; UINTN TemporaryRamSize;
CreatePpiList (&PpiListSize, &PpiList); CreatePpiList (&PpiListSize, &PpiList);
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
// the base of the primary core stack // the base of the primary core stack
PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT); PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize; TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize; TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
@ -42,7 +42,7 @@ PrimaryMain (
// Note: this must be in sync with the stuff in the asm file // Note: this must be in sync with the stuff in the asm file
// Note also: HOBs (pei temp ram) MUST be above stack // Note also: HOBs (pei temp ram) MUST be above stack
// //
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress); SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize); SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack) SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)

54
ArmPlatformPkg/PrePeiCore/PrePeiCore.c
View File

@ -14,13 +14,13 @@
#include "PrePeiCore.h" #include "PrePeiCore.h"
CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport }; CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };
CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = { CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {
{ {
EFI_PEI_PPI_DESCRIPTOR_PPI, EFI_PEI_PPI_DESCRIPTOR_PPI,
&gEfiTemporaryRamSupportPpiGuid, &gEfiTemporaryRamSupportPpiGuid,
(VOID *) &mTemporaryRamSupportPpi (VOID *)&mTemporaryRamSupportPpi
} }
}; };
@ -30,10 +30,10 @@ CreatePpiList (
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
) )
{ {
EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList; EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
UINTN PlatformPpiListSize; UINTN PlatformPpiListSize;
UINTN ListBase; UINTN ListBase;
EFI_PEI_PPI_DESCRIPTOR *LastPpi; EFI_PEI_PPI_DESCRIPTOR *LastPpi;
// Get the Platform PPIs // Get the Platform PPIs
PlatformPpiListSize = 0; PlatformPpiListSize = 0;
@ -41,15 +41,15 @@ CreatePpiList (
// Copy the Common and Platform PPis in Temporary Memory // Copy the Common and Platform PPis in Temporary Memory
ListBase = PcdGet64 (PcdCPUCoresStackBase); ListBase = PcdGet64 (PcdCPUCoresStackBase);
CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable)); CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));
CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize); CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
// Set the Terminate flag on the last PPI entry // Set the Terminate flag on the last PPI entry
LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1; LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;
LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
*PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase; *PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;
*PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize; *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;
} }
VOID VOID
@ -65,8 +65,10 @@ CEntryPoint (
// Enable Instruction Caches on all cores. // Enable Instruction Caches on all cores.
ArmEnableInstructionCache (); ArmEnableInstructionCache ();
InvalidateDataCacheRange ((VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), InvalidateDataCacheRange (
PcdGet32 (PcdCPUCorePrimaryStackSize)); (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
PcdGet32 (PcdCPUCorePrimaryStackSize)
);
// //
// Note: Doesn't have to Enable CPU interface in non-secure world, // Note: Doesn't have to Enable CPU interface in non-secure world,
@ -84,7 +86,7 @@ CEntryPoint (
ArmEnableVFP (); ArmEnableVFP ();
} }
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on. // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
// If not primary Jump to Secondary Main // If not primary Jump to Secondary Main
if (ArmPlatformIsPrimaryCore (MpId)) { if (ArmPlatformIsPrimaryCore (MpId)) {
@ -108,25 +110,25 @@ CEntryPoint (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PrePeiCoreTemporaryRamSupport ( PrePeiCoreTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize IN UINTN CopySize
) )
{ {
VOID *OldHeap; VOID *OldHeap;
VOID *NewHeap; VOID *NewHeap;
VOID *OldStack; VOID *OldStack;
VOID *NewStack; VOID *NewStack;
UINTN HeapSize; UINTN HeapSize;
HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT); HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;
NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize)); NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize); OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);
NewStack = (VOID*)(UINTN)PermanentMemoryBase; NewStack = (VOID *)(UINTN)PermanentMemoryBase;
// //
// Migrate the temporary memory stack to permanent memory stack. // Migrate the temporary memory stack to permanent memory stack.

22
ArmPlatformPkg/PrePeiCore/PrePeiCore.h
View File

@ -6,6 +6,7 @@
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
#ifndef __PREPEICORE_H_ #ifndef __PREPEICORE_H_
#define __PREPEICORE_H_ #define __PREPEICORE_H_
@ -28,19 +29,22 @@ CreatePpiList (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PrePeiCoreTemporaryRamSupport ( PrePeiCoreTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize IN UINTN CopySize
); );
VOID VOID
SecSwitchStack ( SecSwitchStack (
INTN StackDelta INTN StackDelta
); );
// Vector Table for Pei Phase // Vector Table for Pei Phase
VOID PeiVectorTable (VOID); VOID
PeiVectorTable (
VOID
);
VOID VOID
EFIAPI EFIAPI
@ -60,13 +64,13 @@ PrimaryMain (
VOID VOID
EFIAPI EFIAPI
SecondaryMain ( SecondaryMain (
IN UINTN MpId IN UINTN MpId
); );
VOID VOID
PeiCommonExceptionEntry ( PeiCommonExceptionEntry (
IN UINT32 Entry, IN UINT32 Entry,
IN UINTN LR IN UINTN LR
); );
#endif #endif

1
ArmPlatformPkg/PrePi/Arm/ArchPrePi.c
View File

@ -20,4 +20,3 @@ ArchInitialize (
ArmEnableVFP (); ArmEnableVFP ();
} }
} }

55
ArmPlatformPkg/PrePi/MainMPCore.c
View File

@ -14,52 +14,55 @@
VOID VOID
PrimaryMain ( PrimaryMain (
IN UINTN UefiMemoryBase, IN UINTN UefiMemoryBase,
IN UINTN StacksBase, IN UINTN StacksBase,
IN UINT64 StartTimeStamp IN UINT64 StartTimeStamp
) )
{ {
// Enable the GIC Distributor // Enable the GIC Distributor
ArmGicEnableDistributor(PcdGet64(PcdGicDistributorBase)); ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) { if (!FixedPcdGet32 (PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces // Sending SGI to all the Secondary CPU interfaces
ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId)); ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
} }
PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp); PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
// We must never return // We must never return
ASSERT(FALSE); ASSERT (FALSE);
} }
VOID VOID
SecondaryMain ( SecondaryMain (
IN UINTN MpId IN UINTN MpId
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi; ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN Index; UINTN Index;
UINTN ArmCoreCount; UINTN ArmCoreCount;
ARM_CORE_INFO *ArmCoreInfoTable; ARM_CORE_INFO *ArmCoreInfoTable;
UINT32 ClusterId; UINT32 ClusterId;
UINT32 CoreId; UINT32 CoreId;
VOID (*SecondaryStart)(VOID);
UINTN SecondaryEntryAddr;
UINTN AcknowledgeInterrupt;
UINTN InterruptId;
ClusterId = GET_CLUSTER_ID(MpId); VOID (*SecondaryStart)(
CoreId = GET_CORE_ID(MpId); VOID
);
UINTN SecondaryEntryAddr;
UINTN AcknowledgeInterrupt;
UINTN InterruptId;
ClusterId = GET_CLUSTER_ID (MpId);
CoreId = GET_CORE_ID (MpId);
// On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid) // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi); Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
ArmCoreCount = 0; ArmCoreCount = 0;
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable); Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Find the core in the ArmCoreTable // Find the core in the ArmCoreTable
@ -91,9 +94,9 @@ SecondaryMain (
} while (SecondaryEntryAddr == 0); } while (SecondaryEntryAddr == 0);
// Jump to secondary core entry point. // Jump to secondary core entry point.
SecondaryStart = (VOID (*)())SecondaryEntryAddr; SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
SecondaryStart(); SecondaryStart ();
// The secondaries shouldn't reach here // The secondaries shouldn't reach here
ASSERT(FALSE); ASSERT (FALSE);
} }

13
ArmPlatformPkg/PrePi/MainUniCore.c
View File

@ -10,23 +10,22 @@
VOID VOID
PrimaryMain ( PrimaryMain (
IN UINTN UefiMemoryBase, IN UINTN UefiMemoryBase,
IN UINTN StacksBase, IN UINTN StacksBase,
IN UINT64 StartTimeStamp IN UINT64 StartTimeStamp
) )
{ {
PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp); PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
// We must never return // We must never return
ASSERT(FALSE); ASSERT (FALSE);
} }
VOID VOID
SecondaryMain ( SecondaryMain (
IN UINTN MpId IN UINTN MpId
) )
{ {
// We must never get into this function on UniCore system // We must never get into this function on UniCore system
ASSERT(FALSE); ASSERT (FALSE);
} }

90
ArmPlatformPkg/PrePi/PrePi.c
View File

@ -22,11 +22,11 @@
#include "PrePi.h" #include "PrePi.h"
#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \ #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) ||\
((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase))) ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))
UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) + UINT64 mSystemMemoryEnd = FixedPcdGet64 (PcdSystemMemoryBase) +
FixedPcdGet64(PcdSystemMemorySize) - 1; FixedPcdGet64 (PcdSystemMemorySize) - 1;
EFI_STATUS EFI_STATUS
GetPlatformPpi ( GetPlatformPpi (
@ -41,7 +41,7 @@ GetPlatformPpi (
PpiListSize = 0; PpiListSize = 0;
ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList); ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR); PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
for (Index = 0; Index < PpiListCount; Index++, PpiList++) { for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) { if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
*Ppi = PpiList->Ppi; *Ppi = PpiList->Ppi;
@ -54,34 +54,42 @@ GetPlatformPpi (
VOID VOID
PrePiMain ( PrePiMain (
IN UINTN UefiMemoryBase, IN UINTN UefiMemoryBase,
IN UINTN StacksBase, IN UINTN StacksBase,
IN UINT64 StartTimeStamp IN UINT64 StartTimeStamp
) )
{ {
EFI_HOB_HANDOFF_INFO_TABLE* HobList; EFI_HOB_HANDOFF_INFO_TABLE *HobList;
ARM_MP_CORE_INFO_PPI* ArmMpCoreInfoPpi; ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN ArmCoreCount; UINTN ArmCoreCount;
ARM_CORE_INFO* ArmCoreInfoTable; ARM_CORE_INFO *ArmCoreInfoTable;
EFI_STATUS Status; EFI_STATUS Status;
CHAR8 Buffer[100]; CHAR8 Buffer[100];
UINTN CharCount; UINTN CharCount;
UINTN StacksSize; UINTN StacksSize;
FIRMWARE_SEC_PERFORMANCE Performance; FIRMWARE_SEC_PERFORMANCE Performance;
// If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP) // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
ASSERT (IS_XIP() || ASSERT (
((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) && IS_XIP () ||
((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd))); ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd))
);
// Initialize the architecture specific bits // Initialize the architecture specific bits
ArchInitialize (); ArchInitialize ();
// Initialize the Serial Port // Initialize the Serial Port
SerialPortInitialize (); SerialPortInitialize ();
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r", CharCount = AsciiSPrint (
(CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__); Buffer,
SerialPortWrite ((UINT8 *) Buffer, CharCount); sizeof (Buffer),
"UEFI firmware (version %s built at %a on %a)\n\r",
(CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
__TIME__,
__DATE__
);
SerialPortWrite ((UINT8 *)Buffer, CharCount);
// Initialize the Debug Agent for Source Level Debugging // Initialize the Debug Agent for Source Level Debugging
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL); InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
@ -89,11 +97,11 @@ PrePiMain (
// Declare the PI/UEFI memory region // Declare the PI/UEFI memory region
HobList = HobConstructor ( HobList = HobConstructor (
(VOID*)UefiMemoryBase, (VOID *)UefiMemoryBase,
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize), FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
(VOID*)UefiMemoryBase, (VOID *)UefiMemoryBase,
(VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks (VOID *)StacksBase // The top of the UEFI Memory is reserved for the stacks
); );
PrePeiSetHobList (HobList); PrePeiSetHobList (HobList);
// Initialize MMU and Memory HOBs (Resource Descriptor HOBs) // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
@ -107,22 +115,23 @@ PrePiMain (
} else { } else {
StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize); StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
} }
BuildStackHob (StacksBase, StacksSize); BuildStackHob (StacksBase, StacksSize);
//TODO: Call CpuPei as a library // TODO: Call CpuPei as a library
BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize)); BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
if (ArmIsMpCore ()) { if (ArmIsMpCore ()) {
// Only MP Core platform need to produce gArmMpCoreInfoPpiGuid // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi); Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
// On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid) // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Build the MP Core Info Table // Build the MP Core Info Table
ArmCoreCount = 0; ArmCoreCount = 0;
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable); Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) { if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {
// Build MPCore Info HOB // Build MPCore Info HOB
BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount); BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
} }
@ -158,12 +167,12 @@ PrePiMain (
VOID VOID
CEntryPoint ( CEntryPoint (
IN UINTN MpId, IN UINTN MpId,
IN UINTN UefiMemoryBase, IN UINTN UefiMemoryBase,
IN UINTN StacksBase IN UINTN StacksBase
) )
{ {
UINT64 StartTimeStamp; UINT64 StartTimeStamp;
// Initialize the platform specific controllers // Initialize the platform specific controllers
ArmPlatformInitialize (MpId); ArmPlatformInitialize (MpId);
@ -185,9 +194,9 @@ CEntryPoint (
ArmEnableInstructionCache (); ArmEnableInstructionCache ();
// Define the Global Variable region when we are not running in XIP // Define the Global Variable region when we are not running in XIP
if (!IS_XIP()) { if (!IS_XIP ()) {
if (ArmPlatformIsPrimaryCore (MpId)) { if (ArmPlatformIsPrimaryCore (MpId)) {
if (ArmIsMpCore()) { if (ArmIsMpCore ()) {
// Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT) // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
ArmCallSEV (); ArmCallSEV ();
} }
@ -199,9 +208,10 @@ CEntryPoint (
// If not primary Jump to Secondary Main // If not primary Jump to Secondary Main
if (ArmPlatformIsPrimaryCore (MpId)) { if (ArmPlatformIsPrimaryCore (MpId)) {
InvalidateDataCacheRange (
InvalidateDataCacheRange ((VOID *)UefiMemoryBase, (VOID *)UefiMemoryBase,
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)); FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
);
// Goto primary Main. // Goto primary Main.
PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp); PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);

20
ArmPlatformPkg/PrePi/PrePi.h
View File

@ -21,7 +21,7 @@
#include <Library/SerialPortLib.h> #include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h> #include <Library/ArmPlatformLib.h>
extern UINT64 mSystemMemoryEnd; extern UINT64 mSystemMemoryEnd;
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
@ -31,16 +31,16 @@ TimerConstructor (
VOID VOID
PrePiMain ( PrePiMain (
IN UINTN UefiMemoryBase, IN UINTN UefiMemoryBase,
IN UINTN StacksBase, IN UINTN StacksBase,
IN UINT64 StartTimeStamp IN UINT64 StartTimeStamp
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MemoryPeim ( MemoryPeim (
IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
IN UINT64 UefiMemorySize IN UINT64 UefiMemorySize
); );
EFI_STATUS EFI_STATUS
@ -51,14 +51,14 @@ PlatformPeim (
VOID VOID
PrimaryMain ( PrimaryMain (
IN UINTN UefiMemoryBase, IN UINTN UefiMemoryBase,
IN UINTN StacksBase, IN UINTN StacksBase,
IN UINT64 StartTimeStamp IN UINT64 StartTimeStamp
); );
VOID VOID
SecondaryMain ( SecondaryMain (
IN UINTN MpId IN UINTN MpId
); );
// Either implemented by PrePiLib or by MemoryInitPei // Either implemented by PrePiLib or by MemoryInitPei