UefiCpuPkg: Add PiSmmCpuDxeSmm module X64 files
Add module that initializes a CPU for the SMM environment and installs the first level SMI handler. This module along with the SMM IPL and SMM Core provide the services required for DXE_SMM_DRIVERS to register hardware and software SMI handlers. CPU specific features are abstracted through the SmmCpuFeaturesLib Platform specific features are abstracted through the SmmCpuPlatformHookLib Several PCDs are added to enable/disable features and configure settings for the PiSmmCpuDxeSmm module [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18647 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
mdkinney
217
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
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217
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# SmiEntry.S
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#
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# Abstract:
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#
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# Code template of the SMI handler for a particular processor
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(gcSmiHandlerTemplate)
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ASM_GLOBAL ASM_PFX(gcSmiHandlerSize)
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ASM_GLOBAL ASM_PFX(gSmiCr3)
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ASM_GLOBAL ASM_PFX(gSmiStack)
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ASM_GLOBAL ASM_PFX(gSmbase)
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ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug))
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ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
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#
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# Constants relating to PROCESSOR_SMM_DESCRIPTOR
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#
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.equ DSC_OFFSET, 0xfb00
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.equ DSC_GDTPTR, 0x30
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.equ DSC_GDTSIZ, 0x38
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.equ DSC_CS, 14
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.equ DSC_DS, 16
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.equ DSC_SS, 18
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.equ DSC_OTHERSEG, 20
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#
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# Constants relating to CPU State Save Area
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#
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.equ SSM_DR6, 0xffd0
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.equ SSM_DR7, 0xffc8
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.equ PROTECT_MODE_CS, 0x08
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.equ PROTECT_MODE_DS, 0x20
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.equ LONG_MODE_CS, 0x38
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.equ TSS_SEGMENT, 0x40
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.equ GDT_SIZE, 0x50
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.text
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ASM_PFX(gcSmiHandlerTemplate):
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_SmiEntryPoint:
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#
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# The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
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# bit addressing mode. And that coincidence has been used in the following
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# "64-bit like" 16-bit code. Be aware that once RDI is referenced as a
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# base address register, it is actually BX that is referenced.
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#
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.byte 0xbb # mov bx, imm16
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.word _GdtDesc - _SmiEntryPoint + 0x8000
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#
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# fix GDT descriptor
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#
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.byte 0x2e,0xa1 # mov ax, cs:[offset16]
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.word DSC_OFFSET + DSC_GDTSIZ
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.byte 0x48 # dec ax
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.byte 0x2e
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movl %eax, (%rdi) # mov cs:[bx], ax
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.byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
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.word DSC_OFFSET + DSC_GDTPTR
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.byte 0x2e
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movw %ax, 2(%rdi)
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.byte 0x66,0x2e
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lgdt (%rdi)
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#
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# Patch ProtectedMode Segment
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#
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.byte 0xb8
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.word PROTECT_MODE_CS
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.byte 0x2e
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movl %eax, -2(%rdi)
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#
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# Patch ProtectedMode entry
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#
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.byte 0x66, 0xbf # mov edi, SMBASE
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ASM_PFX(gSmbase): .space 4
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lea ((ProtectedMode - _SmiEntryPoint) + 0x8000)(%edi), %ax
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.byte 0x2e
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movw %ax, -6(%rdi)
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#
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# Switch into ProtectedMode
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#
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movq %cr0, %rbx
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.byte 0x66
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andl $0x9ffafff3, %ebx
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.byte 0x66
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orl $0x00000023, %ebx
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movq %rbx, %cr0
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.byte 0x66, 0xea
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.space 6
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_GdtDesc: .space 6
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ProtectedMode:
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movw $PROTECT_MODE_DS, %ax
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movl %eax, %ds
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movl %eax, %es
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movl %eax, %fs
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movl %eax, %gs
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movl %eax, %ss
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.byte 0xbc # mov esp, imm32
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ASM_PFX(gSmiStack): .space 4
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jmp ProtFlatMode
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ProtFlatMode:
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.byte 0xb8
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ASM_PFX(gSmiCr3): .space 4
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movq %rax, %cr3
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movl $0x668,%eax # as cr4.PGE is not set here, refresh cr3
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movq %rax, %cr4 # in PreModifyMtrrs() to flush TLB.
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# Load TSS
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subl $8, %esp # reserve room in stack
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sgdt (%rsp)
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movl 2(%rsp), %eax # eax = GDT base
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addl $8, %esp
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movl %eax, %edx
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addl $GDT_SIZE, %edx
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movb %dl, (TSS_SEGMENT + 2)(%rax)
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movb %dh, (TSS_SEGMENT + 3)(%rax)
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.byte 0xc1, 0xea, 0x10 # shr edx, 16
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movb %dl, (TSS_SEGMENT + 4)(%rax)
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movb %dh, (TSS_SEGMENT + 7)(%rax)
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movl %eax, %edx
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movb $0x89, %dl
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movb %dl, (TSS_SEGMENT + 5)(%rax) # clear busy flag
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movl $TSS_SEGMENT, %eax
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ltr %ax
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#
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# Switch to LongMode
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#
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pushq $LONG_MODE_CS # push cs hardcore here
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call Base # push return address for retf later
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Base:
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addl $(LongMode - Base), (%rsp) # offset for far retf, seg is the 1st arg
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movl $0xc0000080, %ecx
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rdmsr
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orb $1,%ah
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wrmsr
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movq %cr0, %rbx
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btsl $31, %ebx
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movq %rbx, %cr0
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retf
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LongMode: # long mode (64-bit code) starts here
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movabsq $ASM_PFX(gSmiHandlerIdtr), %rax
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lidt (%rax)
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lea (DSC_OFFSET)(%rdi), %ebx
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movw DSC_DS(%rbx), %ax
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movl %eax,%ds
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movw DSC_OTHERSEG(%rbx), %ax
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movl %eax,%es
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movl %eax,%fs
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movl %eax,%gs
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movw DSC_SS(%rbx), %ax
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movl %eax,%ss
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# jmp _SmiHandler ; instruction is not needed
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_SmiHandler:
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movabsq $ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug)), %rax
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cmpb $0, (%rax)
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jz L1
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.byte 0x48, 0x8b, 0x0d # mov rcx, [rip + disp32]
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.long SSM_DR6 - (. + 4 - _SmiEntryPoint + 0x8000)
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.byte 0x48, 0x8b, 0x15 # mov rdx, [rip + disp32]
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.long SSM_DR7 - (. + 4 - _SmiEntryPoint + 0x8000)
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movq %rcx, %dr6
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movq %rdx, %dr7
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L1:
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movabsq $ASM_PFX(SmiRendezvous), %rax
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movq (%rsp), %rcx
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# Save FP registers
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subq $0x208, %rsp
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.byte 0x48 # FXSAVE64
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fxsave (%rsp)
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addq $-0x20, %rsp
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call *%rax
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addq $0x20, %rsp
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#
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# Restore FP registers
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#
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.byte 0x48 # FXRSTOR64
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fxrstor (%rsp)
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movabsq $ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug)), %rax
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cmpb $0, (%rax)
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jz L2
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movq %dr7, %rdx
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movq %dr6, %rcx
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.byte 0x48, 0x89, 0x15 # mov [rip + disp32], rdx
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.long SSM_DR7 - (. + 4 - _SmiEntryPoint + 0x8000)
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.byte 0x48, 0x89, 0x0d # mov [rip + disp32], rcx
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.long SSM_DR6 - (. + 4 - _SmiEntryPoint + 0x8000)
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L2:
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rsm
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ASM_PFX(gcSmiHandlerSize): .word . - _SmiEntryPoint
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