UefiCpuPkg: Add PiSmmCpuDxeSmm module X64 files
Add module that initializes a CPU for the SMM environment and installs the first level SMI handler. This module along with the SMM IPL and SMM Core provide the services required for DXE_SMM_DRIVERS to register hardware and software SMI handlers. CPU specific features are abstracted through the SmmCpuFeaturesLib Platform specific features are abstracted through the SmmCpuPlatformHookLib Several PCDs are added to enable/disable features and configure settings for the PiSmmCpuDxeSmm module [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18647 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
mdkinney
610
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S
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610
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S
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@@ -0,0 +1,610 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# SmiException.S
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#
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# Abstract:
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#
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# Exception handlers used in SM mode
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(SmiPFHandler)
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ASM_GLOBAL ASM_PFX(gSmiMtrrs)
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ASM_GLOBAL ASM_PFX(gcSmiIdtr)
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ASM_GLOBAL ASM_PFX(gcSmiGdtr)
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ASM_GLOBAL ASM_PFX(gcPsd)
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.data
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NullSeg: .quad 0 # reserved by architecture
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CodeSeg32:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x9b
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.byte 0xcf # LimitHigh
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.byte 0 # BaseHigh
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ProtModeCodeSeg32:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x9b
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.byte 0xcf # LimitHigh
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.byte 0 # BaseHigh
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ProtModeSsSeg32:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x93
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.byte 0xcf # LimitHigh
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.byte 0 # BaseHigh
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DataSeg32:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x93
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.byte 0xcf # LimitHigh
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.byte 0 # BaseHigh
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CodeSeg16:
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.word -1
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.word 0
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.byte 0
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.byte 0x9b
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.byte 0x8f
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.byte 0
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DataSeg16:
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.word -1
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.word 0
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.byte 0
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.byte 0x93
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.byte 0x8f
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.byte 0
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CodeSeg64:
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.word -1 # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x9b
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.byte 0xaf # LimitHigh
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.byte 0 # BaseHigh
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# TSS Segment for X64 specially
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TssSeg:
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.word TSS_DESC_SIZE # LimitLow
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.word 0 # BaseLow
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.byte 0 # BaseMid
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.byte 0x89
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.byte 0xDB # LimitHigh
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.byte 0 # BaseHigh
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.long 0 # BaseUpper
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.long 0 # Reserved
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.equ GDT_SIZE, .- NullSeg
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TssDescriptor:
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.space 104, 0
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.equ TSS_DESC_SIZE, .- TssDescriptor
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#
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# This structure serves as a template for all processors.
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#
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ASM_PFX(gcPsd):
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.ascii "PSDSIG "
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.word PSD_SIZE
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.word 2
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.word 1 << 2
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.word CODE_SEL
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.word DATA_SEL
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.word DATA_SEL
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.word DATA_SEL
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.word 0
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.quad 0
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.quad 0
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.quad 0 # fixed in InitializeMpServiceData()
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.quad NullSeg
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.long GDT_SIZE
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.long 0
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.space 24, 0
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.quad ASM_PFX(gSmiMtrrs)
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.equ PSD_SIZE, . - ASM_PFX(gcPsd)
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#
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# CODE & DATA segments for SMM runtime
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#
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.equ CODE_SEL, CodeSeg64 - NullSeg
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.equ DATA_SEL, DataSeg32 - NullSeg
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.equ CODE32_SEL, CodeSeg32 - NullSeg
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ASM_PFX(gcSmiGdtr):
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.word GDT_SIZE - 1
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.quad NullSeg
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ASM_PFX(gcSmiIdtr):
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.word IDT_SIZE - 1
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.quad _SmiIDT
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#
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# Here is the IDT. There are 32 (not 255) entries in it since only processor
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# generated exceptions will be handled.
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#
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_SmiIDT:
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# The following segment repeats 32 times:
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# No. 1
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 2
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 3
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 4
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 5
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 6
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 7
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 8
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 9
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 10
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 11
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 12
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 13
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 14
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 15
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 16
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 17
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 18
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 19
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 20
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 21
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 22
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 23
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 24
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 25
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 26
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 27
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 28
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 29
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 30
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 31
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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# No. 32
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.word 0 # Offset 0:15
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.word CODE_SEL
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.byte 0 # Unused
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.byte 0x8e # Interrupt Gate, Present
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.word 0 # Offset 16:31
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.quad 0 # Offset 32:63
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_SmiIDTEnd:
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.equ IDT_SIZE, (_SmiIDTEnd - _SmiIDT)
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.text
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#------------------------------------------------------------------------------
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# _SmiExceptionEntryPoints is the collection of exception entry points followed
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# by a common exception handler.
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#
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# Stack frame would be as follows as specified in IA32 manuals:
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# +---------------------+ <-- 16-byte aligned ensured by processor
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# + Old SS +
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# +---------------------+
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# + Old RSP +
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# +---------------------+
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# + RFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + RIP +
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# +---------------------+
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# + Error Code +
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# +---------------------+
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# + Vector Number +
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# +---------------------+
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# + RBP +
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# +---------------------+ <-- RBP, 16-byte aligned
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#
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# RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(PageFaultIdtHandlerSmmProfile)
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ASM_PFX(PageFaultIdtHandlerSmmProfile):
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pushq $0x0e # Page Fault
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.byte 0x40, 0xf6, 0xc4, 0x08 #test spl, 8
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jnz L1
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pushq (%rsp)
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movq $0, 8(%rsp)
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L1:
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pushq %rbp
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movq %rsp, %rbp
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#
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# Since here the stack pointer is 16-byte aligned, so
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# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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# is 16-byte aligned
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#
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## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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## UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %r11
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pushq %r10
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pushq %r9
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pushq %r8
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pushq %rax
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pushq %rcx
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pushq %rdx
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pushq %rbx
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pushq 48(%rbp) # RSP
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pushq (%rbp) # RBP
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pushq %rsi
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pushq %rdi
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## UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzwq 56(%rbp), %rax
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pushq %rax # for ss
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movzwq 32(%rbp), %rax
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pushq %rax # for cs
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movq %ds, %rax
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pushq %rax
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movq %es, %rax
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pushq %rax
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movq %fs, %rax
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pushq %rax
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movq %gs, %rax
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pushq %rax
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## UINT64 Rip;
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pushq 24(%rbp)
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## UINT64 Gdtr[2], Idtr[2];
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subq $16, %rsp
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sidt (%rsp)
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subq $16, %rsp
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sgdt (%rsp)
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## UINT64 Ldtr, Tr;
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xorq %rax, %rax
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strw %ax
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pushq %rax
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sldtw %ax
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pushq %rax
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## UINT64 RFlags;
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pushq 40(%rbp)
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## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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movq %cr8, %rax
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pushq %rax
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movq %cr4, %rax
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orq $0x208, %rax
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movq %rax, %cr4
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pushq %rax
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movq %cr3, %rax
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pushq %rax
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movq %cr2, %rax
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pushq %rax
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xorq %rax, %rax
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pushq %rax
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movq %cr0, %rax
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||||
pushq %rax
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||||
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||||
## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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movq %dr7, %rax
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pushq %rax
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movq %dr6, %rax
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||||
pushq %rax
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||||
movq %dr3, %rax
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pushq %rax
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movq %dr2, %rax
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pushq %rax
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movq %dr1, %rax
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pushq %rax
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||||
movq %dr0, %rax
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pushq %rax
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||||
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## FX_SAVE_STATE_X64 FxSaveState;
|
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|
||||
subq $512, %rsp
|
||||
movq %rsp, %rdi
|
||||
.byte 0xf, 0xae, 0x7 # fxsave [rdi]
|
||||
|
||||
# UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
|
||||
cld
|
||||
|
||||
## UINT32 ExceptionData;
|
||||
pushq 16(%rbp)
|
||||
|
||||
## call into exception handler
|
||||
movq 8(%rbp), %rcx
|
||||
movabsq $ASM_PFX(SmiPFHandler), %rax
|
||||
|
||||
## Prepare parameter and call
|
||||
movq %rsp, %rdx
|
||||
#
|
||||
# Per X64 calling convention, allocate maximum parameter stack space
|
||||
# and make sure RSP is 16-byte aligned
|
||||
#
|
||||
subq $4 * 8 + 8, %rsp
|
||||
call *%rax
|
||||
addq $4 * 8 + 8, %rsp
|
||||
jmp L5
|
||||
|
||||
L5:
|
||||
## UINT64 ExceptionData;
|
||||
addq $8, %rsp
|
||||
|
||||
## FX_SAVE_STATE_X64 FxSaveState;
|
||||
|
||||
movq %rsp, %rsi
|
||||
.byte 0xf, 0xae, 0xe # fxrstor [rsi]
|
||||
addq $512, %rsp
|
||||
|
||||
## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
## Skip restoration of DRx registers to support debuggers
|
||||
## that set breakpoints in interrupt/exception context
|
||||
addq $8 * 6, %rsp
|
||||
|
||||
## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
popq %rax
|
||||
movq %rax, %cr0
|
||||
addq $8, %rsp # not for Cr1
|
||||
popq %rax
|
||||
movq %rax, %cr2
|
||||
popq %rax
|
||||
movq %rax, %cr3
|
||||
popq %rax
|
||||
movq %rax, %cr4
|
||||
popq %rax
|
||||
movq %rax, %cr8
|
||||
|
||||
## UINT64 RFlags;
|
||||
popq 40(%rbp)
|
||||
|
||||
## UINT64 Ldtr, Tr;
|
||||
## UINT64 Gdtr[2], Idtr[2];
|
||||
## Best not let anyone mess with these particular registers...
|
||||
addq $48, %rsp
|
||||
|
||||
## UINT64 Rip;
|
||||
popq 24(%rbp)
|
||||
|
||||
## UINT64 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
popq %rax
|
||||
# mov gs, rax ; not for gs
|
||||
popq %rax
|
||||
# mov fs, rax ; not for fs
|
||||
# (X64 will not use fs and gs, so we do not restore it)
|
||||
popq %rax
|
||||
movq %rax, %es
|
||||
popq %rax
|
||||
movq %rax, %ds
|
||||
popq 32(%rbp) # for cs
|
||||
popq 56(%rbp) # for ss
|
||||
|
||||
## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
## UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
popq %rdi
|
||||
popq %rsi
|
||||
addq $8, %rsp # not for rbp
|
||||
popq 48(%rbp) # for rsp
|
||||
popq %rbx
|
||||
popq %rdx
|
||||
popq %rcx
|
||||
popq %rax
|
||||
popq %r8
|
||||
popq %r9
|
||||
popq %r10
|
||||
popq %r11
|
||||
popq %r12
|
||||
popq %r13
|
||||
popq %r14
|
||||
popq %r15
|
||||
|
||||
movq %rbp, %rsp
|
||||
|
||||
# Enable TF bit after page fault handler runs
|
||||
btsl $8, 40(%rsp) #RFLAGS
|
||||
|
||||
popq %rbp
|
||||
addq $16, %rsp # skip INT# & ErrCode
|
||||
iretq
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InitializeIDTSmmStackGuard)
|
||||
ASM_PFX(InitializeIDTSmmStackGuard):
|
||||
# If SMM Stack Guard feature is enabled, set the IST field of
|
||||
# the interrupt gate for Page Fault Exception to be 1
|
||||
#
|
||||
movabsq $_SmiIDT + 14 * 16, %rax
|
||||
movb $1, 4(%rax)
|
||||
ret
|
||||
Reference in New Issue
Block a user