UefiCpuPkg: Add PiSmmCpuDxeSmm module X64 files
Add module that initializes a CPU for the SMM environment and installs the first level SMI handler. This module along with the SMM IPL and SMM Core provide the services required for DXE_SMM_DRIVERS to register hardware and software SMI handlers. CPU specific features are abstracted through the SmmCpuFeaturesLib Platform specific features are abstracted through the SmmCpuPlatformHookLib Several PCDs are added to enable/disable features and configure settings for the PiSmmCpuDxeSmm module [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18647 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
mdkinney
413
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm
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413
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiException.asm
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;
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; Abstract:
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;
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; Exception handlers used in SM mode
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;
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;-------------------------------------------------------------------------------
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EXTERNDEF SmiPFHandler:PROC
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EXTERNDEF gSmiMtrrs:QWORD
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EXTERNDEF gcSmiIdtr:FWORD
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EXTERNDEF gcSmiGdtr:FWORD
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EXTERNDEF gcPsd:BYTE
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.const
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NullSeg DQ 0 ; reserved by architecture
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CodeSeg32 LABEL QWORD
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 9bh
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DB 0cfh ; LimitHigh
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DB 0 ; BaseHigh
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ProtModeCodeSeg32 LABEL QWORD
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 9bh
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DB 0cfh ; LimitHigh
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DB 0 ; BaseHigh
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ProtModeSsSeg32 LABEL QWORD
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 93h
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DB 0cfh ; LimitHigh
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DB 0 ; BaseHigh
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DataSeg32 LABEL QWORD
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 93h
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DB 0cfh ; LimitHigh
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DB 0 ; BaseHigh
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CodeSeg16 LABEL QWORD
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DW -1
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DW 0
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DB 0
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DB 9bh
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DB 8fh
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DB 0
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DataSeg16 LABEL QWORD
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DW -1
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DW 0
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DB 0
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DB 93h
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DB 8fh
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DB 0
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CodeSeg64 LABEL QWORD
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 9bh
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DB 0afh ; LimitHigh
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DB 0 ; BaseHigh
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; TSS Segment for X64 specially
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TssSeg LABEL QWORD
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DW TSS_DESC_SIZE ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 89h
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DB 080h ; LimitHigh
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DB 0 ; BaseHigh
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DD 0 ; BaseUpper
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DD 0 ; Reserved
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GDT_SIZE = $ - offset NullSeg
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; Create TSS Descriptor just after GDT
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TssDescriptor LABEL BYTE
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DD 0 ; Reserved
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DQ 0 ; RSP0
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DQ 0 ; RSP1
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DQ 0 ; RSP2
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DD 0 ; Reserved
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DD 0 ; Reserved
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DQ 0 ; IST1
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DQ 0 ; IST2
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DQ 0 ; IST3
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DQ 0 ; IST4
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DQ 0 ; IST5
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DQ 0 ; IST6
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DQ 0 ; IST7
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DD 0 ; Reserved
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DD 0 ; Reserved
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DW 0 ; Reserved
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DW 0 ; I/O Map Base Address
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TSS_DESC_SIZE = $ - offset TssDescriptor
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;
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; This structure serves as a template for all processors.
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;
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gcPsd LABEL BYTE
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DB 'PSDSIG '
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DW PSD_SIZE
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DW 2
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DW 1 SHL 2
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DW CODE_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW 0
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DQ 0
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DQ 0
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DQ 0 ; fixed in InitializeMpServiceData()
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DQ offset NullSeg
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DD GDT_SIZE
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DD 0
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DB 24 dup (0)
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DQ offset gSmiMtrrs
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PSD_SIZE = $ - offset gcPsd
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;
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; CODE & DATA segments for SMM runtime
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;
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CODE_SEL = offset CodeSeg64 - offset NullSeg
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DATA_SEL = offset DataSeg32 - offset NullSeg
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CODE32_SEL = offset CodeSeg32 - offset NullSeg
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gcSmiGdtr LABEL FWORD
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DW GDT_SIZE - 1
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DQ offset NullSeg
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gcSmiIdtr LABEL FWORD
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DW IDT_SIZE - 1
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DQ offset _SmiIDT
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.data
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;
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; Here is the IDT. There are 32 (not 255) entries in it since only processor
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; generated exceptions will be handled.
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;
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_SmiIDT:
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REPEAT 32
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DW 0 ; Offset 0:15
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DW CODE_SEL ; Segment selector
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DB 0 ; Unused
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DB 8eh ; Interrupt Gate, Present
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DW 0 ; Offset 16:31
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DQ 0 ; Offset 32:63
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ENDM
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_SmiIDTEnd:
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IDT_SIZE = (offset _SmiIDTEnd - offset _SmiIDT)
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.code
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;------------------------------------------------------------------------------
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; _SmiExceptionEntryPoints is the collection of exception entry points followed
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; by a common exception handler.
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;
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; Stack frame would be as follows as specified in IA32 manuals:
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;
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; +---------------------+ <-- 16-byte aligned ensured by processor
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; + Old SS +
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; +---------------------+
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; + Old RSP +
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; +---------------------+
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; + RFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + RIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + Vector Number +
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; +---------------------+
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; + RBP +
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; +---------------------+ <-- RBP, 16-byte aligned
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;
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; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
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;------------------------------------------------------------------------------
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PageFaultIdtHandlerSmmProfile PROC
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push 0eh ; Page Fault
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test spl, 8 ; odd multiple of 8 => ErrCode present
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jnz @F
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push [rsp] ; duplicate INT# if no ErrCode
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mov qword ptr [rsp + 8], 0
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@@:
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push rbp
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mov rbp, rsp
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;
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; Since here the stack pointer is 16-byte aligned, so
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; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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; is 16-byte aligned
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;
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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push r15
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push r14
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push r13
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push r12
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push r11
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push r10
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push r9
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push r8
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push rax
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push rcx
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push rdx
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push rbx
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push qword ptr [rbp + 48] ; RSP
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push qword ptr [rbp] ; RBP
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push rsi
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push rdi
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzx rax, word ptr [rbp + 56]
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push rax ; for ss
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movzx rax, word ptr [rbp + 32]
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push rax ; for cs
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mov rax, ds
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push rax
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mov rax, es
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push rax
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mov rax, fs
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push rax
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mov rax, gs
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push rax
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;; UINT64 Rip;
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push qword ptr [rbp + 24]
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;; UINT64 Gdtr[2], Idtr[2];
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sub rsp, 16
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sidt fword ptr [rsp]
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sub rsp, 16
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sgdt fword ptr [rsp]
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;; UINT64 Ldtr, Tr;
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xor rax, rax
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str ax
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push rax
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sldt ax
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push rax
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;; UINT64 RFlags;
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push qword ptr [rbp + 40]
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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mov rax, cr8
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push rax
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mov rax, cr4
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or rax, 208h
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mov cr4, rax
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push rax
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mov rax, cr3
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push rax
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mov rax, cr2
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push rax
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xor rax, rax
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push rax
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mov rax, cr0
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push rax
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov rax, dr7
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push rax
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mov rax, dr6
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push rax
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mov rax, dr3
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push rax
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mov rax, dr2
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push rax
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mov rax, dr1
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push rax
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mov rax, dr0
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push rax
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;; FX_SAVE_STATE_X64 FxSaveState;
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sub rsp, 512
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mov rdi, rsp
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db 0fh, 0aeh, 00000111y ;fxsave [rdi]
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; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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cld
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;; UINT32 ExceptionData;
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push qword ptr [rbp + 16]
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;; call into exception handler
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mov rcx, [rbp + 8]
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mov rax, SmiPFHandler
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;; Prepare parameter and call
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mov rdx, rsp
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;
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; Per X64 calling convention, allocate maximum parameter stack space
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; and make sure RSP is 16-byte aligned
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;
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sub rsp, 4 * 8 + 8
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call rax
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add rsp, 4 * 8 + 8
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jmp @F
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@@:
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;; UINT64 ExceptionData;
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add rsp, 8
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;; FX_SAVE_STATE_X64 FxSaveState;
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mov rsi, rsp
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db 0fh, 0aeh, 00001110y ; fxrstor [rsi]
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add rsp, 512
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; Skip restoration of DRx registers to support debuggers
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;; that set breakpoints in interrupt/exception context
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add rsp, 8 * 6
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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pop rax
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mov cr0, rax
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add rsp, 8 ; not for Cr1
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pop rax
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mov cr2, rax
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pop rax
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mov cr3, rax
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pop rax
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mov cr4, rax
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pop rax
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mov cr8, rax
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;; UINT64 RFlags;
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pop qword ptr [rbp + 40]
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;; UINT64 Ldtr, Tr;
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;; UINT64 Gdtr[2], Idtr[2];
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;; Best not let anyone mess with these particular registers...
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add rsp, 48
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;; UINT64 Rip;
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pop qword ptr [rbp + 24]
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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pop rax
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; mov gs, rax ; not for gs
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pop rax
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; mov fs, rax ; not for fs
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; (X64 will not use fs and gs, so we do not restore it)
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pop rax
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mov es, rax
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pop rax
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mov ds, rax
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pop qword ptr [rbp + 32] ; for cs
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pop qword ptr [rbp + 56] ; for ss
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pop rdi
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pop rsi
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add rsp, 8 ; not for rbp
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pop qword ptr [rbp + 48] ; for rsp
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pop rbx
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pop rdx
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pop rcx
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pop rax
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pop r8
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pop r9
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pop r10
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pop r11
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pop r12
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pop r13
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pop r14
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pop r15
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mov rsp, rbp
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; Enable TF bit after page fault handler runs
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bts dword ptr [rsp + 40], 8 ;RFLAGS
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pop rbp
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add rsp, 16 ; skip INT# & ErrCode
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iretq
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PageFaultIdtHandlerSmmProfile ENDP
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InitializeIDTSmmStackGuard PROC
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;
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; If SMM Stack Guard feature is enabled, set the IST field of
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; the interrupt gate for Page Fault Exception to be 1
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;
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lea rax, _SmiIDT + 14 * 16
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mov byte ptr [rax + 4], 1
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ret
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InitializeIDTSmmStackGuard ENDP
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END
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