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ArmPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the ArmPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:53:50 -08:00
committed by mergify[bot]
parent 7c2a6033c1
commit 429309e0c6
142 changed files with 6020 additions and 5216 deletions
Download Patch File Download Diff File Expand all files Collapse all files

83
ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c
View File

@@ -11,8 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
VOID
EFIAPI
IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
);
VOID
@@ -26,14 +26,13 @@ ExitBootServicesEvent (
EFI_HANDLE gHardwareInterruptHandle = NULL;
// Notifications
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// Maximum Number of Interrupts
UINTN mGicNumInterrupts = 0;
UINTN mGicNumInterrupts = 0;
HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
/**
Calculate GICD_ICFGRn base address and corresponding bit
field Int_config[1] of the GIC distributor register.
@@ -47,21 +46,21 @@ HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
**/
EFI_STATUS
GicGetDistributorIcfgBaseAndBit (
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress,
OUT UINTN *Config1Bit
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress,
OUT UINTN *Config1Bit
)
{
UINTN RegIndex;
UINTN Field;
UINTN RegIndex;
UINTN Field;
if (Source >= mGicNumInterrupts) {
ASSERT(Source < mGicNumInterrupts);
ASSERT (Source < mGicNumInterrupts);
return EFI_UNSUPPORTED;
}
RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant
Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant
Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
*RegAddress = PcdGet64 (PcdGicDistributorBase)
+ ARM_GIC_ICDICFR
+ (ARM_GIC_ICDICFR_BYTES * RegIndex);
@@ -71,8 +70,6 @@ GicGetDistributorIcfgBaseAndBit (
return EFI_SUCCESS;
}
/**
Register Handler for the specified interrupt source.
@@ -87,13 +84,13 @@ GicGetDistributorIcfgBaseAndBit (
EFI_STATUS
EFIAPI
RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -108,25 +105,25 @@ RegisterInterruptSource (
gRegisteredInterruptHandlers[Source] = Handler;
// If the interrupt handler is unregistered then disable the interrupt
if (NULL == Handler){
if (NULL == Handler) {
return This->DisableInterruptSource (This, Source);
} else {
return This->EnableInterruptSource (This, Source);
}
}
STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
STATIC
VOID
EFIAPI
CpuArchEventProtocolNotify (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_STATUS Status;
// Get the CPU protocol that this driver requires.
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
@@ -137,17 +134,28 @@ CpuArchEventProtocolNotify (
// Unregister the default exception handler.
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__, Status));
DEBUG ((
DEBUG_ERROR,
"%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__,
Status
));
return;
}
// Register to receive interrupts
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ,
Context);
Status = Cpu->RegisterInterruptHandler (
Cpu,
ARM_ARCH_EXCEPTION_IRQ,
Context
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__, Status));
DEBUG ((
DEBUG_ERROR,
"%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__,
Status
));
}
gBS->CloseEvent (Event);
@@ -157,13 +165,13 @@ EFI_STATUS
InstallAndRegisterInterruptService (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent
)
{
EFI_STATUS Status;
CONST UINTN RihArraySize =
(sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
EFI_STATUS Status;
CONST UINTN RihArraySize =
(sizeof (HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
// Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize);
@@ -191,7 +199,8 @@ InstallAndRegisterInterruptService (
TPL_CALLBACK,
CpuArchEventProtocolNotify,
InterruptHandler,
&mCpuArchProtocolNotifyEventRegistration);
&mCpuArchProtocolNotifyEventRegistration
);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (

8
ArmPkg/Drivers/ArmGic/ArmGicDxe.c
View File

@@ -32,12 +32,12 @@ Abstract:
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
ARM_GIC_ARCH_REVISION Revision;
EFI_STATUS Status;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();

27
ArmPkg/Drivers/ArmGic/ArmGicDxe.h
View File

@@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Protocol/HardwareInterrupt.h>
#include <Protocol/HardwareInterrupt2.h>
extern UINTN mGicNumInterrupts;
extern UINTN mGicNumInterrupts;
extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers;
// Common API
@@ -29,33 +29,32 @@ EFI_STATUS
InstallAndRegisterInterruptService (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent
);
EFI_STATUS
EFIAPI
RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
);
// GicV2 API
EFI_STATUS
GicV2DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
);
// GicV3 API
EFI_STATUS
GicV3DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
);
// Shared code
/**
@@ -71,9 +70,9 @@ GicV3DxeInitialize (
**/
EFI_STATUS
GicGetDistributorIcfgBaseAndBit (
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress,
OUT UINTN *Config1Bit
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress,
OUT UINTN *Config1Bit
);
#endif // ARM_GIC_DXE_H_

154
ArmPkg/Drivers/ArmGic/ArmGicLib.c
View File

@@ -24,13 +24,13 @@
+ ARM_GICR_SGI_VLPI_FRAME_SIZE \
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
#define ISENABLER_ADDRESS(base,offset) ((base) + \
#define ISENABLER_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
#define ICENABLER_ADDRESS(base,offset) ((base) + \
#define ICENABLER_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
#define IPRIORITY_ADDRESS(base,offset) ((base) + \
#define IPRIORITY_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
/**
@@ -57,15 +57,15 @@ SourceIsSpi (
STATIC
UINTN
GicGetCpuRedistributorBase (
IN UINTN GicRedistributorBase,
IN ARM_GIC_ARCH_REVISION Revision
IN UINTN GicRedistributorBase,
IN ARM_GIC_ARCH_REVISION Revision
)
{
UINTN MpId;
UINTN CpuAffinity;
UINTN Affinity;
UINTN GicCpuRedistributorBase;
UINT64 TypeRegister;
UINTN MpId;
UINTN CpuAffinity;
UINTN Affinity;
UINTN GicCpuRedistributorBase;
UINT64 TypeRegister;
MpId = ArmReadMpidr ();
// Define CPU affinity as:
@@ -83,7 +83,7 @@ GicGetCpuRedistributorBase (
do {
TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
if (Affinity == CpuAffinity) {
return GicCpuRedistributorBase;
}
@@ -107,7 +107,7 @@ GicGetCpuRedistributorBase (
UINTN
EFIAPI
ArmGicGetInterfaceIdentification (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
// Read the GIC Identification Register
@@ -117,10 +117,10 @@ ArmGicGetInterfaceIdentification (
UINTN
EFIAPI
ArmGicGetMaxNumInterrupts (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
)
{
UINTN ItLines;
UINTN ItLines;
ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
@@ -133,10 +133,10 @@ ArmGicGetMaxNumInterrupts (
VOID
EFIAPI
ArmGicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList,
IN INTN SgiId
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList,
IN INTN SgiId
)
{
MmioWrite32 (
@@ -162,12 +162,12 @@ ArmGicSendSgiTo (
UINTN
EFIAPI
ArmGicAcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase,
OUT UINTN *InterruptId
IN UINTN GicInterruptInterfaceBase,
OUT UINTN *InterruptId
)
{
UINTN Value;
ARM_GIC_ARCH_REVISION Revision;
UINTN Value;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@@ -193,11 +193,11 @@ ArmGicAcknowledgeInterrupt (
VOID
EFIAPI
ArmGicEndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
)
{
ARM_GIC_ARCH_REVISION Revision;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@@ -212,25 +212,26 @@ ArmGicEndOfInterrupt (
VOID
EFIAPI
ArmGicSetInterruptPriority (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source,
IN UINTN Priority
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source,
IN UINTN Priority
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
// Calculate register offset and bit position
RegOffset = Source / 4;
RegShift = (Source % 4) * 8;
RegShift = (Source % 4) * 8;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) {
SourceIsSpi (Source))
{
MmioAndThenOr32 (
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),
@@ -256,24 +257,25 @@ ArmGicSetInterruptPriority (
VOID
EFIAPI
ArmGicEnableInterrupt (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) {
SourceIsSpi (Source))
{
// Write set-enable register
MmioWrite32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
@@ -291,7 +293,7 @@ ArmGicEnableInterrupt (
// Write set-enable register
MmioWrite32 (
ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
1 << RegShift
);
}
@@ -300,24 +302,25 @@ ArmGicEnableInterrupt (
VOID
EFIAPI
ArmGicDisableInterrupt (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) {
SourceIsSpi (Source))
{
// Write clear-enable register
MmioWrite32 (
GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
@@ -325,16 +328,16 @@ ArmGicDisableInterrupt (
);
} else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase,
Revision
);
GicRedistributorBase,
Revision
);
if (GicCpuRedistributorBase == 0) {
return;
}
// Write clear-enable register
MmioWrite32 (
ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
1 << RegShift
);
}
@@ -343,29 +346,30 @@ ArmGicDisableInterrupt (
BOOLEAN
EFIAPI
ArmGicIsInterruptEnabled (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 Interrupts;
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 Interrupts;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) {
SourceIsSpi (Source))
{
Interrupts = ((MmioRead32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
)
& (1 << RegShift)) != 0);
& (1 << RegShift)) != 0);
} else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase,
@@ -377,7 +381,7 @@ ArmGicIsInterruptEnabled (
// Read set-enable register
Interrupts = MmioRead32 (
ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)
ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)
);
}
@@ -387,7 +391,7 @@ ArmGicIsInterruptEnabled (
VOID
EFIAPI
ArmGicDisableDistributor (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
)
{
// Disable Gic Distributor
@@ -397,10 +401,10 @@ ArmGicDisableDistributor (
VOID
EFIAPI
ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
ARM_GIC_ARCH_REVISION Revision;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@@ -415,10 +419,10 @@ ArmGicEnableInterruptInterface (
VOID
EFIAPI
ArmGicDisableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
ARM_GIC_ARCH_REVISION Revision;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {

4
ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c
View File

@@ -13,10 +13,10 @@
VOID
EFIAPI
ArmGicEnableDistributor (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
)
{
ARM_GIC_ARCH_REVISION Revision;
ARM_GIC_ARCH_REVISION Revision;
/*
* Enable GIC distributor in Non-Secure world.

118
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
View File

@@ -22,11 +22,11 @@ Abstract:
#define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
STATIC UINT32 mGicInterruptInterfaceBase;
STATIC UINT32 mGicDistributorBase;
STATIC UINT32 mGicInterruptInterfaceBase;
STATIC UINT32 mGicDistributorBase;
/**
Enable interrupt source Source.
@@ -42,12 +42,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV2EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -70,12 +70,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV2DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -99,13 +99,13 @@ STATIC
EFI_STATUS
EFIAPI
GicV2GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -129,12 +129,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV2EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -158,8 +158,8 @@ STATIC
VOID
EFIAPI
GicV2IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 GicInterrupt;
@@ -185,7 +185,7 @@ GicV2IrqInterruptHandler (
}
// The protocol instance produced by this driver
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
RegisterInterruptSource,
GicV2EnableInterruptSource,
GicV2DisableInterruptSource,
@@ -208,28 +208,28 @@ EFI_STATUS
EFIAPI
GicV2GetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
)
{
UINTN RegAddress;
UINTN Config1Bit;
EFI_STATUS Status;
UINTN RegAddress;
UINTN Config1Bit;
EFI_STATUS Status;
Status = GicGetDistributorIcfgBaseAndBit (
Source,
&RegAddress,
&Config1Bit
);
Source,
&RegAddress,
&Config1Bit
);
if (EFI_ERROR (Status)) {
return Status;
}
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
} else {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
}
return EFI_SUCCESS;
@@ -254,18 +254,22 @@ GicV2SetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
)
{
UINTN RegAddress;
UINTN Config1Bit;
UINT32 Value;
EFI_STATUS Status;
BOOLEAN SourceEnabled;
UINTN RegAddress;
UINTN Config1Bit;
UINT32 Value;
EFI_STATUS Status;
BOOLEAN SourceEnabled;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
TriggerType));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
{
DEBUG ((
DEBUG_ERROR,
"Invalid interrupt trigger type: %d\n", \
TriggerType
));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
Status = GicGetDistributorIcfgBaseAndBit (
@@ -279,7 +283,7 @@ GicV2SetTriggerType (
}
Status = GicV2GetInterruptSourceState (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source,
&SourceEnabled
);
@@ -296,7 +300,7 @@ GicV2SetTriggerType (
// otherwise GIC behavior is UNPREDICTABLE.
if (SourceEnabled) {
GicV2DisableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source
);
}
@@ -310,7 +314,7 @@ GicV2SetTriggerType (
// Restore interrupt state
if (SourceEnabled) {
GicV2EnableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source
);
}
@@ -318,7 +322,7 @@ GicV2SetTriggerType (
return EFI_SUCCESS;
}
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,
(HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,
@@ -345,8 +349,8 @@ GicV2ExitBootServicesEvent (
IN VOID *Context
)
{
UINTN Index;
UINT32 GicInterrupt;
UINTN Index;
UINT32 GicInterrupt;
// Disable all the interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
@@ -382,30 +386,30 @@ GicV2ExitBootServicesEvent (
**/
EFI_STATUS
GicV2DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
UINT32 CpuTarget;
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
UINT32 CpuTarget;
// Make sure the Interrupt Controller Protocol is not already installed in
// the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);
mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
// Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),

6
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c
View File

@@ -12,7 +12,7 @@
UINTN
EFIAPI
ArmGicV2AcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase
IN UINTN GicInterruptInterfaceBase
)
{
// Read the Interrupt Acknowledge Register
@@ -22,8 +22,8 @@ ArmGicV2AcknowledgeInterrupt (
VOID
EFIAPI
ArmGicV2EndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
)
{
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);

5
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c
View File

@@ -10,11 +10,10 @@
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
VOID
EFIAPI
ArmGicV2EnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
/*
@@ -27,7 +26,7 @@ ArmGicV2EnableInterruptInterface (
VOID
EFIAPI
ArmGicV2DisableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
// Disable Gic Interface

106
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
View File

@@ -12,11 +12,11 @@
#define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
STATIC UINTN mGicDistributorBase;
STATIC UINTN mGicRedistributorsBase;
STATIC UINTN mGicDistributorBase;
STATIC UINTN mGicRedistributorsBase;
/**
Enable interrupt source Source.
@@ -32,12 +32,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV3EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -60,12 +60,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV3DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -89,13 +89,13 @@ STATIC
EFI_STATUS
EFIAPI
GicV3GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -123,12 +123,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV3EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT(FALSE);
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -152,8 +152,8 @@ STATIC
VOID
EFIAPI
GicV3IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 GicInterrupt;
@@ -179,7 +179,7 @@ GicV3IrqInterruptHandler (
}
// The protocol instance produced by this driver
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
RegisterInterruptSource,
GicV3EnableInterruptSource,
GicV3DisableInterruptSource,
@@ -206,9 +206,9 @@ GicV3GetTriggerType (
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
)
{
UINTN RegAddress;
UINTN Config1Bit;
EFI_STATUS Status;
UINTN RegAddress;
UINTN Config1Bit;
EFI_STATUS Status;
Status = GicGetDistributorIcfgBaseAndBit (
Source,
@@ -221,9 +221,9 @@ GicV3GetTriggerType (
}
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
} else {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
}
return EFI_SUCCESS;
@@ -248,18 +248,22 @@ GicV3SetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
)
{
UINTN RegAddress;
UINTN Config1Bit;
UINT32 Value;
EFI_STATUS Status;
BOOLEAN SourceEnabled;
UINTN RegAddress;
UINTN Config1Bit;
UINT32 Value;
EFI_STATUS Status;
BOOLEAN SourceEnabled;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
TriggerType));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
{
DEBUG ((
DEBUG_ERROR,
"Invalid interrupt trigger type: %d\n", \
TriggerType
));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
Status = GicGetDistributorIcfgBaseAndBit (
@@ -273,7 +277,7 @@ GicV3SetTriggerType (
}
Status = GicV3GetInterruptSourceState (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source,
&SourceEnabled
);
@@ -290,7 +294,7 @@ GicV3SetTriggerType (
// otherwise GIC behavior is UNPREDICTABLE.
if (SourceEnabled) {
GicV3DisableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source
);
}
@@ -303,7 +307,7 @@ GicV3SetTriggerType (
// Restore interrupt state
if (SourceEnabled) {
GicV3EnableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source
);
}
@@ -311,7 +315,7 @@ GicV3SetTriggerType (
return EFI_SUCCESS;
}
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,
(HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,
@@ -337,7 +341,7 @@ GicV3ExitBootServicesEvent (
IN VOID *Context
)
{
UINTN Index;
UINTN Index;
// Acknowledge all pending interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
@@ -364,14 +368,14 @@ GicV3ExitBootServicesEvent (
**/
EFI_STATUS
GicV3DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT64 CpuTarget;
UINT64 MpId;
EFI_STATUS Status;
UINTN Index;
UINT64 CpuTarget;
UINT64 MpId;
// Make sure the Interrupt Controller Protocol is not already installed in
// the system.
@@ -424,14 +428,14 @@ GicV3DxeInitialize (
}
}
} else {
MpId = ArmReadMpidr ();
MpId = ArmReadMpidr ();
CpuTarget = MpId &
(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
if ((MmioRead32 (
mGicDistributorBase + ARM_GIC_ICDDCR
) & ARM_GIC_ICDDCR_DS) != 0) {
) & ARM_GIC_ICDDCR_DS) != 0)
{
// If the Disable Security (DS) control bit is set, we are dealing with a
// GIC that has only one security state. In this case, let's assume we are
// executing in non-secure state (which is appropriate for DXE modules)