ArmPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
7c2a6033c1
commit
429309e0c6
@@ -24,13 +24,13 @@
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+ ARM_GICR_SGI_VLPI_FRAME_SIZE \
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+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
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#define ISENABLER_ADDRESS(base,offset) ((base) + \
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#define ISENABLER_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
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#define ICENABLER_ADDRESS(base,offset) ((base) + \
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#define ICENABLER_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
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#define IPRIORITY_ADDRESS(base,offset) ((base) + \
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#define IPRIORITY_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
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/**
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@@ -57,15 +57,15 @@ SourceIsSpi (
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STATIC
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UINTN
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GicGetCpuRedistributorBase (
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IN UINTN GicRedistributorBase,
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IN ARM_GIC_ARCH_REVISION Revision
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IN UINTN GicRedistributorBase,
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IN ARM_GIC_ARCH_REVISION Revision
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)
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{
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UINTN MpId;
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UINTN CpuAffinity;
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UINTN Affinity;
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UINTN GicCpuRedistributorBase;
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UINT64 TypeRegister;
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UINTN MpId;
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UINTN CpuAffinity;
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UINTN Affinity;
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UINTN GicCpuRedistributorBase;
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UINT64 TypeRegister;
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MpId = ArmReadMpidr ();
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// Define CPU affinity as:
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@@ -83,7 +83,7 @@ GicGetCpuRedistributorBase (
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do {
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TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
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Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
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Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
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if (Affinity == CpuAffinity) {
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return GicCpuRedistributorBase;
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}
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@@ -107,7 +107,7 @@ GicGetCpuRedistributorBase (
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UINTN
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EFIAPI
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ArmGicGetInterfaceIdentification (
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IN INTN GicInterruptInterfaceBase
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IN INTN GicInterruptInterfaceBase
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)
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{
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// Read the GIC Identification Register
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@@ -117,10 +117,10 @@ ArmGicGetInterfaceIdentification (
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UINTN
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EFIAPI
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ArmGicGetMaxNumInterrupts (
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IN INTN GicDistributorBase
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IN INTN GicDistributorBase
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)
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{
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UINTN ItLines;
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UINTN ItLines;
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ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
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@@ -133,10 +133,10 @@ ArmGicGetMaxNumInterrupts (
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VOID
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EFIAPI
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ArmGicSendSgiTo (
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList,
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IN INTN SgiId
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList,
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IN INTN SgiId
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)
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{
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MmioWrite32 (
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@@ -162,12 +162,12 @@ ArmGicSendSgiTo (
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UINTN
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EFIAPI
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ArmGicAcknowledgeInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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OUT UINTN *InterruptId
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IN UINTN GicInterruptInterfaceBase,
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OUT UINTN *InterruptId
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)
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{
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UINTN Value;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN Value;
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ARM_GIC_ARCH_REVISION Revision;
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Revision = ArmGicGetSupportedArchRevision ();
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if (Revision == ARM_GIC_ARCH_REVISION_2) {
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@@ -193,11 +193,11 @@ ArmGicAcknowledgeInterrupt (
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VOID
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EFIAPI
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ArmGicEndOfInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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IN UINTN Source
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IN UINTN GicInterruptInterfaceBase,
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IN UINTN Source
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)
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{
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ARM_GIC_ARCH_REVISION Revision;
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ARM_GIC_ARCH_REVISION Revision;
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Revision = ArmGicGetSupportedArchRevision ();
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if (Revision == ARM_GIC_ARCH_REVISION_2) {
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@@ -212,25 +212,26 @@ ArmGicEndOfInterrupt (
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VOID
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EFIAPI
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ArmGicSetInterruptPriority (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source,
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IN UINTN Priority
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source,
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IN UINTN Priority
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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// Calculate register offset and bit position
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RegOffset = Source / 4;
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RegShift = (Source % 4) * 8;
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RegShift = (Source % 4) * 8;
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
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SourceIsSpi (Source)) {
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SourceIsSpi (Source))
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{
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MmioAndThenOr32 (
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GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
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~(0xff << RegShift),
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@@ -256,24 +257,25 @@ ArmGicSetInterruptPriority (
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VOID
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EFIAPI
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ArmGicEnableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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RegShift = Source % 32;
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
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SourceIsSpi (Source)) {
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SourceIsSpi (Source))
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{
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// Write set-enable register
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
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@@ -291,7 +293,7 @@ ArmGicEnableInterrupt (
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// Write set-enable register
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MmioWrite32 (
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ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
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ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
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1 << RegShift
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);
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}
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@@ -300,24 +302,25 @@ ArmGicEnableInterrupt (
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VOID
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EFIAPI
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ArmGicDisableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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RegShift = Source % 32;
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
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SourceIsSpi (Source)) {
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SourceIsSpi (Source))
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{
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// Write clear-enable register
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
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@@ -325,16 +328,16 @@ ArmGicDisableInterrupt (
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);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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Revision
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);
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GicRedistributorBase,
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Revision
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);
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if (GicCpuRedistributorBase == 0) {
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return;
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}
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// Write clear-enable register
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MmioWrite32 (
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ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
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ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
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1 << RegShift
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);
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}
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@@ -343,29 +346,30 @@ ArmGicDisableInterrupt (
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BOOLEAN
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EFIAPI
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ArmGicIsInterruptEnabled (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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UINT32 Interrupts;
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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UINT32 Interrupts;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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RegShift = Source % 32;
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
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SourceIsSpi (Source)) {
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SourceIsSpi (Source))
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{
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Interrupts = ((MmioRead32 (
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GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
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)
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& (1 << RegShift)) != 0);
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& (1 << RegShift)) != 0);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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@@ -377,7 +381,7 @@ ArmGicIsInterruptEnabled (
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// Read set-enable register
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Interrupts = MmioRead32 (
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ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)
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ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)
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);
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}
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@@ -387,7 +391,7 @@ ArmGicIsInterruptEnabled (
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VOID
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EFIAPI
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ArmGicDisableDistributor (
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IN INTN GicDistributorBase
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IN INTN GicDistributorBase
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)
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{
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// Disable Gic Distributor
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@@ -397,10 +401,10 @@ ArmGicDisableDistributor (
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VOID
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EFIAPI
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ArmGicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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IN INTN GicInterruptInterfaceBase
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)
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{
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ARM_GIC_ARCH_REVISION Revision;
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ARM_GIC_ARCH_REVISION Revision;
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Revision = ArmGicGetSupportedArchRevision ();
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if (Revision == ARM_GIC_ARCH_REVISION_2) {
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@@ -415,10 +419,10 @@ ArmGicEnableInterruptInterface (
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VOID
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EFIAPI
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ArmGicDisableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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IN INTN GicInterruptInterfaceBase
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)
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{
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ARM_GIC_ARCH_REVISION Revision;
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ARM_GIC_ARCH_REVISION Revision;
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Revision = ArmGicGetSupportedArchRevision ();
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if (Revision == ARM_GIC_ARCH_REVISION_2) {
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