ArmPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
7c2a6033c1
commit
429309e0c6
@@ -12,11 +12,11 @@
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#define ARM_GIC_DEFAULT_PRIORITY 0x80
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
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extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
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extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
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STATIC UINTN mGicDistributorBase;
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STATIC UINTN mGicRedistributorsBase;
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STATIC UINTN mGicDistributorBase;
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STATIC UINTN mGicRedistributorsBase;
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/**
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Enable interrupt source Source.
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@@ -32,12 +32,12 @@ STATIC
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EFI_STATUS
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EFIAPI
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GicV3EnableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source >= mGicNumInterrupts) {
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ASSERT(FALSE);
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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@@ -60,12 +60,12 @@ STATIC
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EFI_STATUS
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EFIAPI
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GicV3DisableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source >= mGicNumInterrupts) {
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ASSERT(FALSE);
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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@@ -89,13 +89,13 @@ STATIC
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EFI_STATUS
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EFIAPI
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GicV3GetInterruptSourceState (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN BOOLEAN *InterruptState
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN BOOLEAN *InterruptState
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)
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{
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if (Source >= mGicNumInterrupts) {
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ASSERT(FALSE);
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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@@ -123,12 +123,12 @@ STATIC
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EFI_STATUS
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EFIAPI
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GicV3EndOfInterrupt (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source >= mGicNumInterrupts) {
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ASSERT(FALSE);
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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@@ -152,8 +152,8 @@ STATIC
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VOID
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EFIAPI
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GicV3IrqInterruptHandler (
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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UINT32 GicInterrupt;
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@@ -179,7 +179,7 @@ GicV3IrqInterruptHandler (
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}
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// The protocol instance produced by this driver
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EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
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EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
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RegisterInterruptSource,
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GicV3EnableInterruptSource,
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GicV3DisableInterruptSource,
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@@ -206,9 +206,9 @@ GicV3GetTriggerType (
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OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
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)
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{
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UINTN RegAddress;
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UINTN Config1Bit;
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EFI_STATUS Status;
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UINTN RegAddress;
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UINTN Config1Bit;
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EFI_STATUS Status;
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Status = GicGetDistributorIcfgBaseAndBit (
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Source,
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@@ -221,9 +221,9 @@ GicV3GetTriggerType (
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}
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if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
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*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
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*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
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} else {
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*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
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*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
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}
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return EFI_SUCCESS;
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@@ -248,18 +248,22 @@ GicV3SetTriggerType (
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IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
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)
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{
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UINTN RegAddress;
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UINTN Config1Bit;
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UINT32 Value;
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EFI_STATUS Status;
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BOOLEAN SourceEnabled;
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UINTN RegAddress;
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UINTN Config1Bit;
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UINT32 Value;
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EFI_STATUS Status;
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BOOLEAN SourceEnabled;
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if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
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&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
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DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
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TriggerType));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
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&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
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{
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DEBUG ((
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DEBUG_ERROR,
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"Invalid interrupt trigger type: %d\n", \
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TriggerType
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));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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Status = GicGetDistributorIcfgBaseAndBit (
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@@ -273,7 +277,7 @@ GicV3SetTriggerType (
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}
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Status = GicV3GetInterruptSourceState (
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(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
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(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
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Source,
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&SourceEnabled
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);
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@@ -290,7 +294,7 @@ GicV3SetTriggerType (
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// otherwise GIC behavior is UNPREDICTABLE.
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if (SourceEnabled) {
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GicV3DisableInterruptSource (
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(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
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(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
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Source
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);
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}
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@@ -303,7 +307,7 @@ GicV3SetTriggerType (
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// Restore interrupt state
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if (SourceEnabled) {
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GicV3EnableInterruptSource (
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(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
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(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
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Source
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);
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}
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@@ -311,7 +315,7 @@ GicV3SetTriggerType (
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return EFI_SUCCESS;
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}
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EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
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EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
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(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
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(HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,
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(HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,
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@@ -337,7 +341,7 @@ GicV3ExitBootServicesEvent (
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IN VOID *Context
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)
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{
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UINTN Index;
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UINTN Index;
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// Acknowledge all pending interrupts
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for (Index = 0; Index < mGicNumInterrupts; Index++) {
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@@ -364,14 +368,14 @@ GicV3ExitBootServicesEvent (
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**/
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EFI_STATUS
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GicV3DxeInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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UINT64 CpuTarget;
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UINT64 MpId;
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EFI_STATUS Status;
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UINTN Index;
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UINT64 CpuTarget;
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UINT64 MpId;
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// Make sure the Interrupt Controller Protocol is not already installed in
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// the system.
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@@ -424,14 +428,14 @@ GicV3DxeInitialize (
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}
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}
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} else {
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MpId = ArmReadMpidr ();
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MpId = ArmReadMpidr ();
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CpuTarget = MpId &
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(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
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(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
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if ((MmioRead32 (
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mGicDistributorBase + ARM_GIC_ICDDCR
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) & ARM_GIC_ICDDCR_DS) != 0) {
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) & ARM_GIC_ICDDCR_DS) != 0)
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{
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// If the Disable Security (DS) control bit is set, we are dealing with a
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// GIC that has only one security state. In this case, let's assume we are
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// executing in non-secure state (which is appropriate for DXE modules)
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