ArmPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
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mergify[bot]
mergify[bot]
parent
7c2a6033c1
commit
429309e0c6
@@ -13,22 +13,21 @@
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// The ARM Architecture Reference Manual for ARMv8-A defines up
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// to 7 levels of cache, L1 through L7.
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#define MAX_ARM_CACHE_LEVEL 7
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#define MAX_ARM_CACHE_LEVEL 7
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/// Defines the structure of the CSSELR (Cache Size Selection) register
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typedef union {
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struct {
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UINT32 InD :1; ///< Instruction not Data bit
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UINT32 Level :3; ///< Cache level (zero based)
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UINT32 TnD :1; ///< Allocation not Data bit
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UINT32 Reserved :27; ///< Reserved, RES0
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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UINT32 InD : 1; ///< Instruction not Data bit
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UINT32 Level : 3; ///< Cache level (zero based)
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UINT32 TnD : 1; ///< Allocation not Data bit
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UINT32 Reserved : 27; ///< Reserved, RES0
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CSSELR_DATA;
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/// The cache type values for the InD field of the CSSELR register
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typedef enum
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{
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typedef enum {
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/// Select the data or unified cache
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CsselrCacheTypeDataOrUnified = 0,
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/// Select the instruction cache
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@@ -39,35 +38,35 @@ typedef enum
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/// Defines the structure of the CCSIDR (Current Cache Size ID) register
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typedef union {
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struct {
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UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
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UINT64 Associativity :10; ///< Associativity - 1
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UINT64 NumSets :15; ///< Number of sets in the cache -1
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UINT64 Unknown :4; ///< Reserved, UNKNOWN
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UINT64 Reserved :32; ///< Reserved, RES0
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UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
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UINT64 Associativity : 10; ///< Associativity - 1
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UINT64 NumSets : 15; ///< Number of sets in the cache -1
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UINT64 Unknown : 4; ///< Reserved, UNKNOWN
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UINT64 Reserved : 32; ///< Reserved, RES0
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} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
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struct {
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UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
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UINT64 Associativity :21; ///< Associativity - 1
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UINT64 Reserved1 :8; ///< Reserved, RES0
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UINT64 NumSets :24; ///< Number of sets in the cache -1
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UINT64 Reserved2 :8; ///< Reserved, RES0
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UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
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UINT64 Associativity : 21; ///< Associativity - 1
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UINT64 Reserved1 : 8; ///< Reserved, RES0
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UINT64 NumSets : 24; ///< Number of sets in the cache -1
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UINT64 Reserved2 : 8; ///< Reserved, RES0
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} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
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struct {
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UINT64 LineSize : 3;
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UINT64 Associativity : 21;
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UINT64 Reserved : 8;
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UINT64 Unallocated : 32;
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UINT64 LineSize : 3;
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UINT64 Associativity : 21;
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UINT64 Reserved : 8;
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UINT64 Unallocated : 32;
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} BitsCcidxAA32;
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UINT64 Data; ///< The entire 64-bit value
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UINT64 Data; ///< The entire 64-bit value
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} CCSIDR_DATA;
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/// Defines the structure of the AARCH32 CCSIDR2 register.
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typedef union {
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struct {
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UINT32 NumSets :24; ///< Number of sets in the cache - 1
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UINT32 Reserved :8; ///< Reserved, RES0
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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UINT32 NumSets : 24; ///< Number of sets in the cache - 1
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UINT32 Reserved : 8; ///< Reserved, RES0
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CCSIDR2_DATA;
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/** Defines the structure of the CLIDR (Cache Level ID) register.
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@@ -77,19 +76,19 @@ typedef union {
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**/
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typedef union {
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struct {
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UINT32 Ctype1 : 3; ///< Level 1 cache type
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UINT32 Ctype2 : 3; ///< Level 2 cache type
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UINT32 Ctype3 : 3; ///< Level 3 cache type
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UINT32 Ctype4 : 3; ///< Level 4 cache type
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UINT32 Ctype5 : 3; ///< Level 5 cache type
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UINT32 Ctype6 : 3; ///< Level 6 cache type
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UINT32 Ctype7 : 3; ///< Level 7 cache type
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UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
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UINT32 LoC : 3; ///< Level of Coherency
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UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
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UINT32 Icb : 3; ///< Inner Cache Boundary
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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UINT32 Ctype1 : 3; ///< Level 1 cache type
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UINT32 Ctype2 : 3; ///< Level 2 cache type
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UINT32 Ctype3 : 3; ///< Level 3 cache type
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UINT32 Ctype4 : 3; ///< Level 4 cache type
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UINT32 Ctype5 : 3; ///< Level 5 cache type
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UINT32 Ctype6 : 3; ///< Level 6 cache type
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UINT32 Ctype7 : 3; ///< Level 7 cache type
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UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
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UINT32 LoC : 3; ///< Level of Coherency
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UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
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UINT32 Icb : 3; ///< Inner Cache Boundary
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CLIDR_DATA;
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/// The cache types reported in the CLIDR register.
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@@ -107,6 +106,6 @@ typedef enum {
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ClidrCacheTypeMax
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} CLIDR_CACHE_TYPE;
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#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
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#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
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#endif /* ARM_CACHE_H_ */
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@@ -16,34 +16,34 @@
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#ifndef ARM_FFA_SVC_H_
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#define ARM_FFA_SVC_H_
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#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
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#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
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/* Generic IDs when using AArch32 or AArch64 execution state */
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#ifdef MDE_CPU_AARCH64
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
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#endif
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#ifdef MDE_CPU_ARM
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
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#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
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#endif
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#define SPM_MAJOR_VERSION_FFA 1
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#define SPM_MINOR_VERSION_FFA 0
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#define SPM_MAJOR_VERSION_FFA 1
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#define SPM_MINOR_VERSION_FFA 0
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#define ARM_FFA_SPM_RET_SUCCESS 0
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#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
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#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
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#define ARM_FFA_SPM_RET_NO_MEMORY -3
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#define ARM_FFA_SPM_RET_BUSY -4
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#define ARM_FFA_SPM_RET_INTERRUPTED -5
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#define ARM_FFA_SPM_RET_DENIED -6
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#define ARM_FFA_SPM_RET_RETRY -7
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#define ARM_FFA_SPM_RET_ABORTED -8
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#define ARM_FFA_SPM_RET_SUCCESS 0
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#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
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#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
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#define ARM_FFA_SPM_RET_NO_MEMORY -3
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#define ARM_FFA_SPM_RET_BUSY -4
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#define ARM_FFA_SPM_RET_INTERRUPTED -5
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#define ARM_FFA_SPM_RET_DENIED -6
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#define ARM_FFA_SPM_RET_RETRY -7
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#define ARM_FFA_SPM_RET_ABORTED -8
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// For now, the destination id to be used in the FF-A calls
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// is being hard-coded. Subsequently, support will be added
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@@ -51,6 +51,6 @@
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// This is the endpoint id used by the optee os's implementation
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// of the spmc.
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// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
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#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
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#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
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#endif // ARM_FFA_SVC_H_
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@@ -14,49 +14,49 @@
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* delegated events and request the Secure partition manager to perform
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* privileged operations on its behalf.
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*/
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#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
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#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
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#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
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#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
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#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
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#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
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#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
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#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
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#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
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#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
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#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
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#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
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#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
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#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
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/* Generic IDs when using AArch32 or AArch64 execution state */
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#ifdef MDE_CPU_AARCH64
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#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
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#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
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#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
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#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
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#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
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#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
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#endif
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#ifdef MDE_CPU_ARM
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#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
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#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
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#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
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#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
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#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
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#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
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#endif
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#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
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#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
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#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
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#define SET_MEM_ATTR_DATA_PERM_RW 1
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#define SET_MEM_ATTR_DATA_PERM_RO 3
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#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
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#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
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#define SET_MEM_ATTR_DATA_PERM_RW 1
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#define SET_MEM_ATTR_DATA_PERM_RO 3
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#define SET_MEM_ATTR_CODE_PERM_MASK 0x1
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#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
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#define SET_MEM_ATTR_CODE_PERM_X 0
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#define SET_MEM_ATTR_CODE_PERM_XN 1
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#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
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#define SET_MEM_ATTR_CODE_PERM_X 0
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#define SET_MEM_ATTR_CODE_PERM_XN 1
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#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \
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((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
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(( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
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/* MM SVC Return error codes */
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#define ARM_SVC_SPM_RET_SUCCESS 0
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#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
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#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
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#define ARM_SVC_SPM_RET_DENIED -3
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#define ARM_SVC_SPM_RET_NO_MEMORY -5
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#define ARM_SVC_SPM_RET_SUCCESS 0
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#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
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#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
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#define ARM_SVC_SPM_RET_DENIED -3
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#define ARM_SVC_SPM_RET_NO_MEMORY -5
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#define SPM_MAJOR_VERSION 0
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#define SPM_MINOR_VERSION 1
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#define SPM_MAJOR_VERSION 0
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#define SPM_MINOR_VERSION 1
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#endif // ARM_MM_SVC_H_
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@@ -17,64 +17,64 @@
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* SMC function IDs for Standard Service queries
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*/
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#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
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#define ARM_SMC_ID_STD_UID 0x8400ff01
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#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
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#define ARM_SMC_ID_STD_UID 0x8400ff01
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/* 0x8400ff02 is reserved */
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#define ARM_SMC_ID_STD_REVISION 0x8400ff03
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#define ARM_SMC_ID_STD_REVISION 0x8400ff03
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/*
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* The 'Standard Service Call UID' is supposed to return the Standard
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* Service UUID. This is a 128-bit value.
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*/
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#define ARM_SMC_STD_UUID0 0x108d905b
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#define ARM_SMC_STD_UUID1 0x47e8f863
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#define ARM_SMC_STD_UUID2 0xfbc02dae
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#define ARM_SMC_STD_UUID3 0xe2f64156
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#define ARM_SMC_STD_UUID0 0x108d905b
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#define ARM_SMC_STD_UUID1 0x47e8f863
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#define ARM_SMC_STD_UUID2 0xfbc02dae
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#define ARM_SMC_STD_UUID3 0xe2f64156
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/*
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* ARM Standard Service Calls revision numbers
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* The current revision is: 0.1
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*/
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#define ARM_SMC_STD_REVISION_MAJOR 0x0
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#define ARM_SMC_STD_REVISION_MINOR 0x1
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#define ARM_SMC_STD_REVISION_MAJOR 0x0
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#define ARM_SMC_STD_REVISION_MINOR 0x1
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/*
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* Management Mode (MM) calls cover a subset of the Standard Service Call range.
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* The list below is not exhaustive.
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*/
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#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
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#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
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#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
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#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
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// Request service from secure standalone MM environment
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#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
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#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
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#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
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#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
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/* Generic ID when using AArch32 or AArch64 execution state */
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#ifdef MDE_CPU_AARCH64
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#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
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#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
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#endif
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#ifdef MDE_CPU_ARM
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#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
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#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
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#endif
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/* MM return error codes */
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#define ARM_SMC_MM_RET_SUCCESS 0
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#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
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#define ARM_SMC_MM_RET_INVALID_PARAMS -2
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#define ARM_SMC_MM_RET_DENIED -3
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#define ARM_SMC_MM_RET_NO_MEMORY -4
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#define ARM_SMC_MM_RET_SUCCESS 0
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#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
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#define ARM_SMC_MM_RET_INVALID_PARAMS -2
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#define ARM_SMC_MM_RET_DENIED -3
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#define ARM_SMC_MM_RET_NO_MEMORY -4
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// ARM Architecture Calls
|
||||
#define SMCCC_VERSION 0x80000000
|
||||
#define SMCCC_ARCH_FEATURES 0x80000001
|
||||
#define SMCCC_ARCH_SOC_ID 0x80000002
|
||||
#define SMCCC_ARCH_WORKAROUND_1 0x80008000
|
||||
#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
|
||||
#define SMCCC_VERSION 0x80000000
|
||||
#define SMCCC_ARCH_FEATURES 0x80000001
|
||||
#define SMCCC_ARCH_SOC_ID 0x80000002
|
||||
#define SMCCC_ARCH_WORKAROUND_1 0x80008000
|
||||
#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
|
||||
|
||||
#define SMC_ARCH_CALL_SUCCESS 0
|
||||
#define SMC_ARCH_CALL_NOT_SUPPORTED -1
|
||||
#define SMC_ARCH_CALL_NOT_REQUIRED -2
|
||||
#define SMC_ARCH_CALL_INVALID_PARAMETER -3
|
||||
#define SMC_ARCH_CALL_NOT_SUPPORTED -1
|
||||
#define SMC_ARCH_CALL_NOT_REQUIRED -2
|
||||
#define SMC_ARCH_CALL_INVALID_PARAMETER -3
|
||||
|
||||
/*
|
||||
* Power State Coordination Interface (PSCI) calls cover a subset of the
|
||||
@@ -101,15 +101,15 @@
|
||||
((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
|
||||
|
||||
/* PSCI return error codes */
|
||||
#define ARM_SMC_PSCI_RET_SUCCESS 0
|
||||
#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
|
||||
#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
|
||||
#define ARM_SMC_PSCI_RET_DENIED -3
|
||||
#define ARM_SMC_PSCI_RET_ALREADY_ON -4
|
||||
#define ARM_SMC_PSCI_RET_ON_PENDING -5
|
||||
#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
|
||||
#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
|
||||
#define ARM_SMC_PSCI_RET_DISABLED -8
|
||||
#define ARM_SMC_PSCI_RET_SUCCESS 0
|
||||
#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
|
||||
#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
|
||||
#define ARM_SMC_PSCI_RET_DENIED -3
|
||||
#define ARM_SMC_PSCI_RET_ALREADY_ON -4
|
||||
#define ARM_SMC_PSCI_RET_ON_PENDING -5
|
||||
#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
|
||||
#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
|
||||
#define ARM_SMC_PSCI_RET_DISABLED -8
|
||||
|
||||
#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
|
||||
((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
|
||||
@@ -120,10 +120,10 @@
|
||||
#define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)
|
||||
#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)
|
||||
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
|
||||
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0
|
||||
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1
|
||||
@@ -132,9 +132,9 @@
|
||||
/*
|
||||
* SMC function IDs for Trusted OS Service queries
|
||||
*/
|
||||
#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
|
||||
#define ARM_SMC_ID_TOS_UID 0xbf00ff01
|
||||
#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
|
||||
#define ARM_SMC_ID_TOS_UID 0xbf00ff01
|
||||
/* 0xbf00ff02 is reserved */
|
||||
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
|
||||
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
|
||||
|
||||
#endif // ARM_STD_SMC_H_
|
||||
|
||||
Reference in New Issue
Block a user