sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ArmPkg: Apply uncrustify changes

Browse Source 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the ArmPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:53:50 -08:00
committed by mergify[bot]
parent 7c2a6033c1
commit 429309e0c6
142 changed files with 6020 additions and 5216 deletions
Download Patch File Download Diff File Expand all files Collapse all files

143
ArmPkg/Include/Library/ArmLib.h
View File

@@ -15,13 +15,13 @@
#ifdef MDE_CPU_ARM
#include <Chipset/ArmV7.h>
#elif defined(MDE_CPU_AARCH64)
#elif defined (MDE_CPU_AARCH64)
#include <Chipset/AArch64.h>
#else
#error "Unknown chipset."
#error "Unknown chipset."
#endif
#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
EFI_MEMORY_WT | EFI_MEMORY_WB | \
EFI_MEMORY_UCE)
@@ -50,17 +50,21 @@ typedef enum {
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
} ARM_MEMORY_REGION_ATTRIBUTES;
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
typedef struct {
EFI_PHYSICAL_ADDRESS PhysicalBase;
EFI_VIRTUAL_ADDRESS VirtualBase;
UINT64 Length;
ARM_MEMORY_REGION_ATTRIBUTES Attributes;
EFI_PHYSICAL_ADDRESS PhysicalBase;
EFI_VIRTUAL_ADDRESS VirtualBase;
UINT64 Length;
ARM_MEMORY_REGION_ATTRIBUTES Attributes;
} ARM_MEMORY_REGION_DESCRIPTOR;
typedef VOID (*CACHE_OPERATION)(VOID);
typedef VOID (*LINE_OPERATION)(UINTN);
typedef VOID (*CACHE_OPERATION)(
VOID
);
typedef VOID (*LINE_OPERATION)(
UINTN
);
//
// ARM Processor Mode
@@ -80,34 +84,34 @@ typedef enum {
//
// ARM Cpu IDs
//
#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
//
// ARM MP Core IDs
//
#define ARM_CORE_AFF0 0xFF
#define ARM_CORE_AFF1 (0xFF << 8)
#define ARM_CORE_AFF2 (0xFF << 16)
#define ARM_CORE_AFF3 (0xFFULL << 32)
#define ARM_CORE_AFF0 0xFF
#define ARM_CORE_AFF1 (0xFF << 8)
#define ARM_CORE_AFF2 (0xFF << 16)
#define ARM_CORE_AFF3 (0xFFULL << 32)
#define ARM_CORE_MASK ARM_CORE_AFF0
#define ARM_CLUSTER_MASK ARM_CORE_AFF1
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
#define ARM_CORE_MASK ARM_CORE_AFF0
#define ARM_CLUSTER_MASK ARM_CORE_AFF1
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
/** Reads the CCSIDR register for the specified cache.
@@ -118,7 +122,7 @@ typedef enum {
**/
UINTN
ReadCCSIDR (
IN UINT32 CSSELR
IN UINT32 CSSELR
);
/** Reads the CCSIDR2 for the specified cache.
@@ -129,7 +133,7 @@ ReadCCSIDR (
**/
UINT32
ReadCCSIDR2 (
IN UINT32 CSSELR
IN UINT32 CSSELR
);
/** Reads the Cache Level ID (CLIDR) register.
@@ -183,7 +187,6 @@ ArmInvalidateDataCache (
VOID
);
VOID
EFIAPI
ArmCleanInvalidateDataCache (
@@ -205,31 +208,31 @@ ArmInvalidateInstructionCache (
VOID
EFIAPI
ArmInvalidateDataCacheEntryByMVA (
IN UINTN Address
IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryToPoUByMVA (
IN UINTN Address
IN UINTN Address
);
VOID
EFIAPI
ArmInvalidateInstructionCacheEntryToPoUByMVA (
IN UINTN Address
IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryByMVA (
IN UINTN Address
);
IN UINTN Address
);
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (
IN UINTN Address
IN UINTN Address
);
VOID
@@ -352,8 +355,8 @@ ArmInvalidateTlb (
VOID
EFIAPI
ArmUpdateTranslationTableEntry (
IN VOID *TranslationTableEntry,
IN VOID *Mva
IN VOID *TranslationTableEntry,
IN VOID *Mva
);
VOID
@@ -371,7 +374,7 @@ ArmSetTTBR0 (
VOID
EFIAPI
ArmSetTTBCR (
IN UINT32 Bits
IN UINT32 Bits
);
VOID *
@@ -431,7 +434,7 @@ ArmInstructionSynchronizationBarrier (
VOID
EFIAPI
ArmWriteVBar (
IN UINTN VectorBase
IN UINTN VectorBase
);
UINTN
@@ -443,7 +446,7 @@ ArmReadVBar (
VOID
EFIAPI
ArmWriteAuxCr (
IN UINT32 Bit
IN UINT32 Bit
);
UINT32
@@ -455,13 +458,13 @@ ArmReadAuxCr (
VOID
EFIAPI
ArmSetAuxCrBit (
IN UINT32 Bits
IN UINT32 Bits
);
VOID
EFIAPI
ArmUnsetAuxCrBit (
IN UINT32 Bits
IN UINT32 Bits
);
VOID
@@ -504,7 +507,7 @@ ArmReadCpacr (
VOID
EFIAPI
ArmWriteCpacr (
IN UINT32 Access
IN UINT32 Access
);
VOID
@@ -534,7 +537,7 @@ ArmReadScr (
VOID
EFIAPI
ArmWriteScr (
IN UINT32 Value
IN UINT32 Value
);
UINT32
@@ -546,7 +549,7 @@ ArmReadMVBar (
VOID
EFIAPI
ArmWriteMVBar (
IN UINT32 VectorMonitorBase
IN UINT32 VectorMonitorBase
);
UINT32
@@ -558,7 +561,7 @@ ArmReadSctlr (
VOID
EFIAPI
ArmWriteSctlr (
IN UINT32 Value
IN UINT32 Value
);
UINTN
@@ -570,10 +573,9 @@ ArmReadHVBar (
VOID
EFIAPI
ArmWriteHVBar (
IN UINTN HypModeVectorBase
IN UINTN HypModeVectorBase
);
//
// Helper functions for accessing CPU ACTLR
//
@@ -587,28 +589,28 @@ ArmReadCpuActlr (
VOID
EFIAPI
ArmWriteCpuActlr (
IN UINTN Val
IN UINTN Val
);
VOID
EFIAPI
ArmSetCpuActlrBit (
IN UINTN Bits
IN UINTN Bits
);
VOID
EFIAPI
ArmUnsetCpuActlrBit (
IN UINTN Bits
IN UINTN Bits
);
//
// Accessors for the architected generic timer registers
//
#define ARM_ARCH_TIMER_ENABLE (1 << 0)
#define ARM_ARCH_TIMER_IMASK (1 << 1)
#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
#define ARM_ARCH_TIMER_ENABLE (1 << 0)
#define ARM_ARCH_TIMER_IMASK (1 << 1)
#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
UINTN
EFIAPI
@@ -619,7 +621,7 @@ ArmReadCntFrq (
VOID
EFIAPI
ArmWriteCntFrq (
UINTN FreqInHz
UINTN FreqInHz
);
UINT64
@@ -637,7 +639,7 @@ ArmReadCntkCtl (
VOID
EFIAPI
ArmWriteCntkCtl (
UINTN Val
UINTN Val
);
UINTN
@@ -649,7 +651,7 @@ ArmReadCntpTval (
VOID
EFIAPI
ArmWriteCntpTval (
UINTN Val
UINTN Val
);
UINTN
@@ -661,7 +663,7 @@ ArmReadCntpCtl (
VOID
EFIAPI
ArmWriteCntpCtl (
UINTN Val
UINTN Val
);
UINTN
@@ -673,7 +675,7 @@ ArmReadCntvTval (
VOID
EFIAPI
ArmWriteCntvTval (
UINTN Val
UINTN Val
);
UINTN
@@ -685,7 +687,7 @@ ArmReadCntvCtl (
VOID
EFIAPI
ArmWriteCntvCtl (
UINTN Val
UINTN Val
);
UINT64
@@ -703,7 +705,7 @@ ArmReadCntpCval (
VOID
EFIAPI
ArmWriteCntpCval (
UINT64 Val
UINT64 Val
);
UINT64
@@ -715,7 +717,7 @@ ArmReadCntvCval (
VOID
EFIAPI
ArmWriteCntvCval (
UINT64 Val
UINT64 Val
);
UINT64
@@ -727,7 +729,7 @@ ArmReadCntvOff (
VOID
EFIAPI
ArmWriteCntvOff (
UINT64 Val
UINT64 Val
);
UINTN
@@ -736,7 +738,6 @@ ArmGetPhysicalAddressBits (
VOID
);
///
/// ID Register Helper functions
///
@@ -768,6 +769,7 @@ ArmHasCcidx (
///
/// AArch32-only ID Register Helper functions
///
/**
Check whether the CPU supports the Security extensions
@@ -779,6 +781,7 @@ EFIAPI
ArmHasSecurityExtensions (
VOID
);
#endif // MDE_CPU_ARM
#endif // ARM_LIB_H_