sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ArmPkg: Apply uncrustify changes

Browse Source 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the ArmPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:53:50 -08:00
committed by mergify[bot]
parent 7c2a6033c1
commit 429309e0c6
142 changed files with 6020 additions and 5216 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c
View File

@ -12,21 +12,23 @@
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
#include <Protocol/Cpu.h> #include <Protocol/Cpu.h>
STATIC EFI_CPU_ARCH_PROTOCOL *mCpu; STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
ArmCrashDumpDxeInitialize ( ArmCrashDumpDxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu); Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR (Status);
return mCpu->RegisterInterruptHandler (mCpu, return mCpu->RegisterInterruptHandler (
EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, mCpu,
&DefaultExceptionHandler); EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,
&DefaultExceptionHandler
);
} }

83
ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c
View File

@ -11,8 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
VOID VOID
EFIAPI EFIAPI
IrqInterruptHandler ( IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
); );
VOID VOID
@ -26,14 +26,13 @@ ExitBootServicesEvent (
EFI_HANDLE gHardwareInterruptHandle = NULL; EFI_HANDLE gHardwareInterruptHandle = NULL;
// Notifications // Notifications
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// Maximum Number of Interrupts // Maximum Number of Interrupts
UINTN mGicNumInterrupts = 0; UINTN mGicNumInterrupts = 0;
HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL; HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
/** /**
Calculate GICD_ICFGRn base address and corresponding bit Calculate GICD_ICFGRn base address and corresponding bit
field Int_config[1] of the GIC distributor register. field Int_config[1] of the GIC distributor register.
@ -47,21 +46,21 @@ HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
**/ **/
EFI_STATUS EFI_STATUS
GicGetDistributorIcfgBaseAndBit ( GicGetDistributorIcfgBaseAndBit (
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress, OUT UINTN *RegAddress,
OUT UINTN *Config1Bit OUT UINTN *Config1Bit
) )
{ {
UINTN RegIndex; UINTN RegIndex;
UINTN Field; UINTN Field;
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(Source < mGicNumInterrupts); ASSERT (Source < mGicNumInterrupts);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant
Field = Source % ARM_GIC_ICDICFR_F_STRIDE; Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
*RegAddress = PcdGet64 (PcdGicDistributorBase) *RegAddress = PcdGet64 (PcdGicDistributorBase)
+ ARM_GIC_ICDICFR + ARM_GIC_ICDICFR
+ (ARM_GIC_ICDICFR_BYTES * RegIndex); + (ARM_GIC_ICDICFR_BYTES * RegIndex);
@ -71,8 +70,6 @@ GicGetDistributorIcfgBaseAndBit (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Register Handler for the specified interrupt source. Register Handler for the specified interrupt source.
@ -87,13 +84,13 @@ GicGetDistributorIcfgBaseAndBit (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
RegisterInterruptSource ( RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler IN HARDWARE_INTERRUPT_HANDLER Handler
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -108,25 +105,25 @@ RegisterInterruptSource (
gRegisteredInterruptHandlers[Source] = Handler; gRegisteredInterruptHandlers[Source] = Handler;
// If the interrupt handler is unregistered then disable the interrupt // If the interrupt handler is unregistered then disable the interrupt
if (NULL == Handler){ if (NULL == Handler) {
return This->DisableInterruptSource (This, Source); return This->DisableInterruptSource (This, Source);
} else { } else {
return This->EnableInterruptSource (This, Source); return This->EnableInterruptSource (This, Source);
} }
} }
STATIC VOID *mCpuArchProtocolNotifyEventRegistration; STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
STATIC STATIC
VOID VOID
EFIAPI EFIAPI
CpuArchEventProtocolNotify ( CpuArchEventProtocolNotify (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
EFI_CPU_ARCH_PROTOCOL *Cpu; EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_STATUS Status; EFI_STATUS Status;
// Get the CPU protocol that this driver requires. // Get the CPU protocol that this driver requires.
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
@ -137,17 +134,28 @@ CpuArchEventProtocolNotify (
// Unregister the default exception handler. // Unregister the default exception handler.
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL); Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n", DEBUG ((
__FUNCTION__, Status)); DEBUG_ERROR,
"%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__,
Status
));
return; return;
} }
// Register to receive interrupts // Register to receive interrupts
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, Status = Cpu->RegisterInterruptHandler (
Context); Cpu,
ARM_ARCH_EXCEPTION_IRQ,
Context
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n", DEBUG ((
__FUNCTION__, Status)); DEBUG_ERROR,
"%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__,
Status
));
} }
gBS->CloseEvent (Event); gBS->CloseEvent (Event);
@ -157,13 +165,13 @@ EFI_STATUS
InstallAndRegisterInterruptService ( InstallAndRegisterInterruptService (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol, IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent IN EFI_EVENT_NOTIFY ExitBootServicesEvent
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
CONST UINTN RihArraySize = CONST UINTN RihArraySize =
(sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts); (sizeof (HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
// Initialize the array for the Interrupt Handlers // Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize); gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize);
@ -191,7 +199,8 @@ InstallAndRegisterInterruptService (
TPL_CALLBACK, TPL_CALLBACK,
CpuArchEventProtocolNotify, CpuArchEventProtocolNotify,
InterruptHandler, InterruptHandler,
&mCpuArchProtocolNotifyEventRegistration); &mCpuArchProtocolNotifyEventRegistration
);
// Register for an ExitBootServicesEvent // Register for an ExitBootServicesEvent
Status = gBS->CreateEvent ( Status = gBS->CreateEvent (

8
ArmPkg/Drivers/ArmGic/ArmGicDxe.c
View File

@ -32,12 +32,12 @@ Abstract:
**/ **/
EFI_STATUS EFI_STATUS
InterruptDxeInitialize ( InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();

27
ArmPkg/Drivers/ArmGic/ArmGicDxe.h
View File

@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Protocol/HardwareInterrupt.h> #include <Protocol/HardwareInterrupt.h>
#include <Protocol/HardwareInterrupt2.h> #include <Protocol/HardwareInterrupt2.h>
extern UINTN mGicNumInterrupts; extern UINTN mGicNumInterrupts;
extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers; extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers;
// Common API // Common API
@ -29,33 +29,32 @@ EFI_STATUS
InstallAndRegisterInterruptService ( InstallAndRegisterInterruptService (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol, IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent IN EFI_EVENT_NOTIFY ExitBootServicesEvent
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
RegisterInterruptSource ( RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler IN HARDWARE_INTERRUPT_HANDLER Handler
); );
// GicV2 API // GicV2 API
EFI_STATUS EFI_STATUS
GicV2DxeInitialize ( GicV2DxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
); );
// GicV3 API // GicV3 API
EFI_STATUS EFI_STATUS
GicV3DxeInitialize ( GicV3DxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
); );
// Shared code // Shared code
/** /**
@ -71,9 +70,9 @@ GicV3DxeInitialize (
**/ **/
EFI_STATUS EFI_STATUS
GicGetDistributorIcfgBaseAndBit ( GicGetDistributorIcfgBaseAndBit (
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress, OUT UINTN *RegAddress,
OUT UINTN *Config1Bit OUT UINTN *Config1Bit
); );
#endif // ARM_GIC_DXE_H_ #endif // ARM_GIC_DXE_H_

154
ArmPkg/Drivers/ArmGic/ArmGicLib.c
View File

@ -24,13 +24,13 @@
+ ARM_GICR_SGI_VLPI_FRAME_SIZE \ + ARM_GICR_SGI_VLPI_FRAME_SIZE \
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE) + ARM_GICR_SGI_RESERVED_FRAME_SIZE)
#define ISENABLER_ADDRESS(base,offset) ((base) + \ #define ISENABLER_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset)) ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
#define ICENABLER_ADDRESS(base,offset) ((base) + \ #define ICENABLER_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset)) ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
#define IPRIORITY_ADDRESS(base,offset) ((base) + \ #define IPRIORITY_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset)) ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
/** /**
@ -57,15 +57,15 @@ SourceIsSpi (
STATIC STATIC
UINTN UINTN
GicGetCpuRedistributorBase ( GicGetCpuRedistributorBase (
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN ARM_GIC_ARCH_REVISION Revision IN ARM_GIC_ARCH_REVISION Revision
) )
{ {
UINTN MpId; UINTN MpId;
UINTN CpuAffinity; UINTN CpuAffinity;
UINTN Affinity; UINTN Affinity;
UINTN GicCpuRedistributorBase; UINTN GicCpuRedistributorBase;
UINT64 TypeRegister; UINT64 TypeRegister;
MpId = ArmReadMpidr (); MpId = ArmReadMpidr ();
// Define CPU affinity as: // Define CPU affinity as:
@ -83,7 +83,7 @@ GicGetCpuRedistributorBase (
do { do {
TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER); TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister); Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
if (Affinity == CpuAffinity) { if (Affinity == CpuAffinity) {
return GicCpuRedistributorBase; return GicCpuRedistributorBase;
} }
@ -107,7 +107,7 @@ GicGetCpuRedistributorBase (
UINTN UINTN
EFIAPI EFIAPI
ArmGicGetInterfaceIdentification ( ArmGicGetInterfaceIdentification (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
// Read the GIC Identification Register // Read the GIC Identification Register
@ -117,10 +117,10 @@ ArmGicGetInterfaceIdentification (
UINTN UINTN
EFIAPI EFIAPI
ArmGicGetMaxNumInterrupts ( ArmGicGetMaxNumInterrupts (
IN INTN GicDistributorBase IN INTN GicDistributorBase
) )
{ {
UINTN ItLines; UINTN ItLines;
ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F; ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
@ -133,10 +133,10 @@ ArmGicGetMaxNumInterrupts (
VOID VOID
EFIAPI EFIAPI
ArmGicSendSgiTo ( ArmGicSendSgiTo (
IN INTN GicDistributorBase, IN INTN GicDistributorBase,
IN INTN TargetListFilter, IN INTN TargetListFilter,
IN INTN CPUTargetList, IN INTN CPUTargetList,
IN INTN SgiId IN INTN SgiId
) )
{ {
MmioWrite32 ( MmioWrite32 (
@ -162,12 +162,12 @@ ArmGicSendSgiTo (
UINTN UINTN
EFIAPI EFIAPI
ArmGicAcknowledgeInterrupt ( ArmGicAcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase, IN UINTN GicInterruptInterfaceBase,
OUT UINTN *InterruptId OUT UINTN *InterruptId
) )
{ {
UINTN Value; UINTN Value;
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) { if (Revision == ARM_GIC_ARCH_REVISION_2) {
@ -193,11 +193,11 @@ ArmGicAcknowledgeInterrupt (
VOID VOID
EFIAPI EFIAPI
ArmGicEndOfInterrupt ( ArmGicEndOfInterrupt (
IN UINTN GicInterruptInterfaceBase, IN UINTN GicInterruptInterfaceBase,
IN UINTN Source IN UINTN Source
) )
{ {
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) { if (Revision == ARM_GIC_ARCH_REVISION_2) {
@ -212,25 +212,26 @@ ArmGicEndOfInterrupt (
VOID VOID
EFIAPI EFIAPI
ArmGicSetInterruptPriority ( ArmGicSetInterruptPriority (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN UINTN Source, IN UINTN Source,
IN UINTN Priority IN UINTN Priority
) )
{ {
UINT32 RegOffset; UINT32 RegOffset;
UINTN RegShift; UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase; UINTN GicCpuRedistributorBase;
// Calculate register offset and bit position // Calculate register offset and bit position
RegOffset = Source / 4; RegOffset = Source / 4;
RegShift = (Source % 4) * 8; RegShift = (Source % 4) * 8;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) || if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) { SourceIsSpi (Source))
{
MmioAndThenOr32 ( MmioAndThenOr32 (
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift), ~(0xff << RegShift),
@ -256,24 +257,25 @@ ArmGicSetInterruptPriority (
VOID VOID
EFIAPI EFIAPI
ArmGicEnableInterrupt ( ArmGicEnableInterrupt (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN UINTN Source IN UINTN Source
) )
{ {
UINT32 RegOffset; UINT32 RegOffset;
UINTN RegShift; UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase; UINTN GicCpuRedistributorBase;
// Calculate enable register offset and bit position // Calculate enable register offset and bit position
RegOffset = Source / 32; RegOffset = Source / 32;
RegShift = Source % 32; RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) || if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) { SourceIsSpi (Source))
{
// Write set-enable register // Write set-enable register
MmioWrite32 ( MmioWrite32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
@ -291,7 +293,7 @@ ArmGicEnableInterrupt (
// Write set-enable register // Write set-enable register
MmioWrite32 ( MmioWrite32 (
ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset), ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
1 << RegShift 1 << RegShift
); );
} }
@ -300,24 +302,25 @@ ArmGicEnableInterrupt (
VOID VOID
EFIAPI EFIAPI
ArmGicDisableInterrupt ( ArmGicDisableInterrupt (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN UINTN Source IN UINTN Source
) )
{ {
UINT32 RegOffset; UINT32 RegOffset;
UINTN RegShift; UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase; UINTN GicCpuRedistributorBase;
// Calculate enable register offset and bit position // Calculate enable register offset and bit position
RegOffset = Source / 32; RegOffset = Source / 32;
RegShift = Source % 32; RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) || if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) { SourceIsSpi (Source))
{
// Write clear-enable register // Write clear-enable register
MmioWrite32 ( MmioWrite32 (
GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
@ -325,16 +328,16 @@ ArmGicDisableInterrupt (
); );
} else { } else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase ( GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase, GicRedistributorBase,
Revision Revision
); );
if (GicCpuRedistributorBase == 0) { if (GicCpuRedistributorBase == 0) {
return; return;
} }
// Write clear-enable register // Write clear-enable register
MmioWrite32 ( MmioWrite32 (
ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset), ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
1 << RegShift 1 << RegShift
); );
} }
@ -343,29 +346,30 @@ ArmGicDisableInterrupt (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
ArmGicIsInterruptEnabled ( ArmGicIsInterruptEnabled (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN UINTN Source IN UINTN Source
) )
{ {
UINT32 RegOffset; UINT32 RegOffset;
UINTN RegShift; UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase; UINTN GicCpuRedistributorBase;
UINT32 Interrupts; UINT32 Interrupts;
// Calculate enable register offset and bit position // Calculate enable register offset and bit position
RegOffset = Source / 32; RegOffset = Source / 32;
RegShift = Source % 32; RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) || if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) { SourceIsSpi (Source))
{
Interrupts = ((MmioRead32 ( Interrupts = ((MmioRead32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset) GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
) )
& (1 << RegShift)) != 0); & (1 << RegShift)) != 0);
} else { } else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase ( GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase, GicRedistributorBase,
@ -377,7 +381,7 @@ ArmGicIsInterruptEnabled (
// Read set-enable register // Read set-enable register
Interrupts = MmioRead32 ( Interrupts = MmioRead32 (
ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset) ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)
); );
} }
@ -387,7 +391,7 @@ ArmGicIsInterruptEnabled (
VOID VOID
EFIAPI EFIAPI
ArmGicDisableDistributor ( ArmGicDisableDistributor (
IN INTN GicDistributorBase IN INTN GicDistributorBase
) )
{ {
// Disable Gic Distributor // Disable Gic Distributor
@ -397,10 +401,10 @@ ArmGicDisableDistributor (
VOID VOID
EFIAPI EFIAPI
ArmGicEnableInterruptInterface ( ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) { if (Revision == ARM_GIC_ARCH_REVISION_2) {
@ -415,10 +419,10 @@ ArmGicEnableInterruptInterface (
VOID VOID
EFIAPI EFIAPI
ArmGicDisableInterruptInterface ( ArmGicDisableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision (); Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) { if (Revision == ARM_GIC_ARCH_REVISION_2) {

4
ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c
View File

@ -13,10 +13,10 @@
VOID VOID
EFIAPI EFIAPI
ArmGicEnableDistributor ( ArmGicEnableDistributor (
IN INTN GicDistributorBase IN INTN GicDistributorBase
) )
{ {
ARM_GIC_ARCH_REVISION Revision; ARM_GIC_ARCH_REVISION Revision;
/* /*
* Enable GIC distributor in Non-Secure world. * Enable GIC distributor in Non-Secure world.

118
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
View File

@ -22,11 +22,11 @@ Abstract:
#define ARM_GIC_DEFAULT_PRIORITY 0x80 #define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol; extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol; extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
STATIC UINT32 mGicInterruptInterfaceBase; STATIC UINT32 mGicInterruptInterfaceBase;
STATIC UINT32 mGicDistributorBase; STATIC UINT32 mGicDistributorBase;
/** /**
Enable interrupt source Source. Enable interrupt source Source.
@ -42,12 +42,12 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GicV2EnableInterruptSource ( GicV2EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source IN HARDWARE_INTERRUPT_SOURCE Source
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -70,12 +70,12 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GicV2DisableInterruptSource ( GicV2DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source IN HARDWARE_INTERRUPT_SOURCE Source
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -99,13 +99,13 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GicV2GetInterruptSourceState ( GicV2GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState IN BOOLEAN *InterruptState
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -129,12 +129,12 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GicV2EndOfInterrupt ( GicV2EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source IN HARDWARE_INTERRUPT_SOURCE Source
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -158,8 +158,8 @@ STATIC
VOID VOID
EFIAPI EFIAPI
GicV2IrqInterruptHandler ( GicV2IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
UINT32 GicInterrupt; UINT32 GicInterrupt;
@ -185,7 +185,7 @@ GicV2IrqInterruptHandler (
} }
// The protocol instance produced by this driver // The protocol instance produced by this driver
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = { EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
RegisterInterruptSource, RegisterInterruptSource,
GicV2EnableInterruptSource, GicV2EnableInterruptSource,
GicV2DisableInterruptSource, GicV2DisableInterruptSource,
@ -208,28 +208,28 @@ EFI_STATUS
EFIAPI EFIAPI
GicV2GetTriggerType ( GicV2GetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
) )
{ {
UINTN RegAddress; UINTN RegAddress;
UINTN Config1Bit; UINTN Config1Bit;
EFI_STATUS Status; EFI_STATUS Status;
Status = GicGetDistributorIcfgBaseAndBit ( Status = GicGetDistributorIcfgBaseAndBit (
Source, Source,
&RegAddress, &RegAddress,
&Config1Bit &Config1Bit
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) { if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH; *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
} else { } else {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING; *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
@ -254,18 +254,22 @@ GicV2SetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
) )
{ {
UINTN RegAddress; UINTN RegAddress;
UINTN Config1Bit; UINTN Config1Bit;
UINT32 Value; UINT32 Value;
EFI_STATUS Status; EFI_STATUS Status;
BOOLEAN SourceEnabled; BOOLEAN SourceEnabled;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING) if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) { && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \ {
TriggerType)); DEBUG ((
ASSERT (FALSE); DEBUG_ERROR,
return EFI_UNSUPPORTED; "Invalid interrupt trigger type: %d\n", \
TriggerType
));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
} }
Status = GicGetDistributorIcfgBaseAndBit ( Status = GicGetDistributorIcfgBaseAndBit (
@ -279,7 +283,7 @@ GicV2SetTriggerType (
} }
Status = GicV2GetInterruptSourceState ( Status = GicV2GetInterruptSourceState (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source, Source,
&SourceEnabled &SourceEnabled
); );
@ -296,7 +300,7 @@ GicV2SetTriggerType (
// otherwise GIC behavior is UNPREDICTABLE. // otherwise GIC behavior is UNPREDICTABLE.
if (SourceEnabled) { if (SourceEnabled) {
GicV2DisableInterruptSource ( GicV2DisableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source Source
); );
} }
@ -310,7 +314,7 @@ GicV2SetTriggerType (
// Restore interrupt state // Restore interrupt state
if (SourceEnabled) { if (SourceEnabled) {
GicV2EnableInterruptSource ( GicV2EnableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source Source
); );
} }
@ -318,7 +322,7 @@ GicV2SetTriggerType (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = { EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource, (HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,
(HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource, (HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,
@ -345,8 +349,8 @@ GicV2ExitBootServicesEvent (
IN VOID *Context IN VOID *Context
) )
{ {
UINTN Index; UINTN Index;
UINT32 GicInterrupt; UINT32 GicInterrupt;
// Disable all the interrupts // Disable all the interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) { for (Index = 0; Index < mGicNumInterrupts; Index++) {
@ -382,30 +386,30 @@ GicV2ExitBootServicesEvent (
**/ **/
EFI_STATUS EFI_STATUS
GicV2DxeInitialize ( GicV2DxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
UINT32 RegOffset; UINT32 RegOffset;
UINTN RegShift; UINTN RegShift;
UINT32 CpuTarget; UINT32 CpuTarget;
// Make sure the Interrupt Controller Protocol is not already installed in // Make sure the Interrupt Controller Protocol is not already installed in
// the system. // the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid); ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase); mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);
mGicDistributorBase = PcdGet64 (PcdGicDistributorBase); mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase); mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
for (Index = 0; Index < mGicNumInterrupts; Index++) { for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index); GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
// Set Priority // Set Priority
RegOffset = Index / 4; RegOffset = Index / 4;
RegShift = (Index % 4) * 8; RegShift = (Index % 4) * 8;
MmioAndThenOr32 ( MmioAndThenOr32 (
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift), ~(0xff << RegShift),

6
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c
View File

@ -12,7 +12,7 @@
UINTN UINTN
EFIAPI EFIAPI
ArmGicV2AcknowledgeInterrupt ( ArmGicV2AcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase IN UINTN GicInterruptInterfaceBase
) )
{ {
// Read the Interrupt Acknowledge Register // Read the Interrupt Acknowledge Register
@ -22,8 +22,8 @@ ArmGicV2AcknowledgeInterrupt (
VOID VOID
EFIAPI EFIAPI
ArmGicV2EndOfInterrupt ( ArmGicV2EndOfInterrupt (
IN UINTN GicInterruptInterfaceBase, IN UINTN GicInterruptInterfaceBase,
IN UINTN Source IN UINTN Source
) )
{ {
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source); MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);

5
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c
View File

@ -10,11 +10,10 @@
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Library/ArmGicLib.h> #include <Library/ArmGicLib.h>
VOID VOID
EFIAPI EFIAPI
ArmGicV2EnableInterruptInterface ( ArmGicV2EnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
/* /*
@ -27,7 +26,7 @@ ArmGicV2EnableInterruptInterface (
VOID VOID
EFIAPI EFIAPI
ArmGicV2DisableInterruptInterface ( ArmGicV2DisableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
// Disable Gic Interface // Disable Gic Interface

106
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
View File

@ -12,11 +12,11 @@
#define ARM_GIC_DEFAULT_PRIORITY 0x80 #define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol; extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol; extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
STATIC UINTN mGicDistributorBase; STATIC UINTN mGicDistributorBase;
STATIC UINTN mGicRedistributorsBase; STATIC UINTN mGicRedistributorsBase;
/** /**
Enable interrupt source Source. Enable interrupt source Source.
@ -32,12 +32,12 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GicV3EnableInterruptSource ( GicV3EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source IN HARDWARE_INTERRUPT_SOURCE Source
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -60,12 +60,12 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GicV3DisableInterruptSource ( GicV3DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source IN HARDWARE_INTERRUPT_SOURCE Source
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -89,13 +89,13 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GicV3GetInterruptSourceState ( GicV3GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState IN BOOLEAN *InterruptState
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -123,12 +123,12 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GicV3EndOfInterrupt ( GicV3EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source IN HARDWARE_INTERRUPT_SOURCE Source
) )
{ {
if (Source >= mGicNumInterrupts) { if (Source >= mGicNumInterrupts) {
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -152,8 +152,8 @@ STATIC
VOID VOID
EFIAPI EFIAPI
GicV3IrqInterruptHandler ( GicV3IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
UINT32 GicInterrupt; UINT32 GicInterrupt;
@ -179,7 +179,7 @@ GicV3IrqInterruptHandler (
} }
// The protocol instance produced by this driver // The protocol instance produced by this driver
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = { EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
RegisterInterruptSource, RegisterInterruptSource,
GicV3EnableInterruptSource, GicV3EnableInterruptSource,
GicV3DisableInterruptSource, GicV3DisableInterruptSource,
@ -206,9 +206,9 @@ GicV3GetTriggerType (
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
) )
{ {
UINTN RegAddress; UINTN RegAddress;
UINTN Config1Bit; UINTN Config1Bit;
EFI_STATUS Status; EFI_STATUS Status;
Status = GicGetDistributorIcfgBaseAndBit ( Status = GicGetDistributorIcfgBaseAndBit (
Source, Source,
@ -221,9 +221,9 @@ GicV3GetTriggerType (
} }
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) { if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH; *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
} else { } else {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING; *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
@ -248,18 +248,22 @@ GicV3SetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
) )
{ {
UINTN RegAddress; UINTN RegAddress;
UINTN Config1Bit; UINTN Config1Bit;
UINT32 Value; UINT32 Value;
EFI_STATUS Status; EFI_STATUS Status;
BOOLEAN SourceEnabled; BOOLEAN SourceEnabled;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING) if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) { && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \ {
TriggerType)); DEBUG ((
ASSERT (FALSE); DEBUG_ERROR,
return EFI_UNSUPPORTED; "Invalid interrupt trigger type: %d\n", \
TriggerType
));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
} }
Status = GicGetDistributorIcfgBaseAndBit ( Status = GicGetDistributorIcfgBaseAndBit (
@ -273,7 +277,7 @@ GicV3SetTriggerType (
} }
Status = GicV3GetInterruptSourceState ( Status = GicV3GetInterruptSourceState (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source, Source,
&SourceEnabled &SourceEnabled
); );
@ -290,7 +294,7 @@ GicV3SetTriggerType (
// otherwise GIC behavior is UNPREDICTABLE. // otherwise GIC behavior is UNPREDICTABLE.
if (SourceEnabled) { if (SourceEnabled) {
GicV3DisableInterruptSource ( GicV3DisableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source Source
); );
} }
@ -303,7 +307,7 @@ GicV3SetTriggerType (
// Restore interrupt state // Restore interrupt state
if (SourceEnabled) { if (SourceEnabled) {
GicV3EnableInterruptSource ( GicV3EnableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source Source
); );
} }
@ -311,7 +315,7 @@ GicV3SetTriggerType (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = { EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource, (HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,
(HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource, (HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,
@ -337,7 +341,7 @@ GicV3ExitBootServicesEvent (
IN VOID *Context IN VOID *Context
) )
{ {
UINTN Index; UINTN Index;
// Acknowledge all pending interrupts // Acknowledge all pending interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) { for (Index = 0; Index < mGicNumInterrupts; Index++) {
@ -364,14 +368,14 @@ GicV3ExitBootServicesEvent (
**/ **/
EFI_STATUS EFI_STATUS
GicV3DxeInitialize ( GicV3DxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
UINT64 CpuTarget; UINT64 CpuTarget;
UINT64 MpId; UINT64 MpId;
// Make sure the Interrupt Controller Protocol is not already installed in // Make sure the Interrupt Controller Protocol is not already installed in
// the system. // the system.
@ -424,14 +428,14 @@ GicV3DxeInitialize (
} }
} }
} else { } else {
MpId = ArmReadMpidr (); MpId = ArmReadMpidr ();
CpuTarget = MpId & CpuTarget = MpId &
(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3); (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
if ((MmioRead32 ( if ((MmioRead32 (
mGicDistributorBase + ARM_GIC_ICDDCR mGicDistributorBase + ARM_GIC_ICDDCR
) & ARM_GIC_ICDDCR_DS) != 0) { ) & ARM_GIC_ICDDCR_DS) != 0)
{
// If the Disable Security (DS) control bit is set, we are dealing with a // If the Disable Security (DS) control bit is set, we are dealing with a
// GIC that has only one security state. In this case, let's assume we are // GIC that has only one security state. In this case, let's assume we are
// executing in non-secure state (which is appropriate for DXE modules) // executing in non-secure state (which is appropriate for DXE modules)

45
ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c
View File

@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
#define MAX_IO_PORT_ADDRESS 0xFFFF #define MAX_IO_PORT_ADDRESS 0xFFFF
// //
// Handle for the CPU I/O 2 Protocol // Handle for the CPU I/O 2 Protocol
@ -28,7 +28,7 @@ STATIC EFI_HANDLE mHandle = NULL;
// //
// Lookup table for increment values based on transfer widths // Lookup table for increment values based on transfer widths
// //
STATIC CONST UINT8 mInStride[] = { STATIC CONST UINT8 mInStride[] = {
1, // EfiCpuIoWidthUint8 1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16 2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32 4, // EfiCpuIoWidthUint32
@ -46,7 +46,7 @@ STATIC CONST UINT8 mInStride[] = {
// //
// Lookup table for increment values based on transfer widths // Lookup table for increment values based on transfer widths
// //
STATIC CONST UINT8 mOutStride[] = { STATIC CONST UINT8 mOutStride[] = {
1, // EfiCpuIoWidthUint8 1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16 2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32 4, // EfiCpuIoWidthUint32
@ -117,14 +117,14 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access, // For FIFO type, the target address won't increase during the access,
// so treat Count as 1 // so treat Count as 1
// //
if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) { if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
Count = 1; Count = 1;
} }
// //
// Check to see if Width is in the valid range for I/O Port operations // Check to see if Width is in the valid range for I/O Port operations
// //
Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) { if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -161,6 +161,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) { if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -240,9 +241,9 @@ CpuMemoryServiceRead (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) { if (OperationWidth == EfiCpuIoWidthUint8) {
*Uint8Buffer = MmioRead8 ((UINTN)Address); *Uint8Buffer = MmioRead8 ((UINTN)Address);
@ -254,6 +255,7 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -321,9 +323,9 @@ CpuMemoryServiceWrite (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) { if (OperationWidth == EfiCpuIoWidthUint8) {
MmioWrite8 ((UINTN)Address, *Uint8Buffer); MmioWrite8 ((UINTN)Address, *Uint8Buffer);
@ -335,6 +337,7 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -404,9 +407,9 @@ CpuIoServiceRead (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) { if (OperationWidth == EfiCpuIoWidthUint8) {
@ -490,9 +493,9 @@ CpuIoServiceWrite (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) { if (OperationWidth == EfiCpuIoWidthUint8) {
@ -510,7 +513,7 @@ CpuIoServiceWrite (
// //
// CPU I/O 2 Protocol instance // CPU I/O 2 Protocol instance
// //
STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = { STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
{ {
CpuMemoryServiceRead, CpuMemoryServiceRead,
CpuMemoryServiceWrite CpuMemoryServiceWrite
@ -521,7 +524,6 @@ STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
} }
}; };
/** /**
The user Entry Point for module CpuIo2Dxe. The user code starts with this function. The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
@ -539,12 +541,13 @@ ArmPciCpuIo2Initialize (
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&mHandle, &mHandle,
&gEfiCpuIo2ProtocolGuid, &mCpuIo2, &gEfiCpuIo2ProtocolGuid,
&mCpuIo2,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

6
ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h
View File

@ -14,7 +14,7 @@
// Return values of BASE_DISCOVER_LIST_PROTOCOLS command. // Return values of BASE_DISCOVER_LIST_PROTOCOLS command.
typedef struct { typedef struct {
UINT32 NumProtocols; UINT32 NumProtocols;
// Array of four protocols in each element // Array of four protocols in each element
// Total elements = 1 + (NumProtocols-1)/4 // Total elements = 1 + (NumProtocols-1)/4
@ -22,7 +22,7 @@ typedef struct {
// NOTE: Since EDK2 does not allow flexible array member [] we declare // NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable // here array of 1 element length. However below is used as a variable
// length array. // length array.
UINT8 Protocols[1]; UINT8 Protocols[1];
} BASE_DISCOVER_LIST; } BASE_DISCOVER_LIST;
/** Initialize Base protocol and install protocol on a given handle. /** Initialize Base protocol and install protocol on a given handle.
@ -34,7 +34,7 @@ typedef struct {
**/ **/
EFI_STATUS EFI_STATUS
ScmiBaseProtocolInit ( ScmiBaseProtocolInit (
IN OUT EFI_HANDLE* Handle IN OUT EFI_HANDLE *Handle
); );
#endif /* ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ */ #endif /* ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ */

41
ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h
View File

@ -16,57 +16,56 @@
// Clock rate in two 32bit words. // Clock rate in two 32bit words.
typedef struct { typedef struct {
UINT32 Low; UINT32 Low;
UINT32 High; UINT32 High;
} CLOCK_RATE_DWORD; } CLOCK_RATE_DWORD;
// Format of the returned rate array. Linear or Non-linear,.RatesFlag Bit[12] // Format of the returned rate array. Linear or Non-linear,.RatesFlag Bit[12]
#define RATE_FORMAT_SHIFT 12 #define RATE_FORMAT_SHIFT 12
#define RATE_FORMAT_MASK 0x0001 #define RATE_FORMAT_MASK 0x0001
#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \ #define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \
& RATE_FORMAT_MASK) & RATE_FORMAT_MASK)
// Number of remaining rates after a call to the SCP, RatesFlag Bits[31:16] // Number of remaining rates after a call to the SCP, RatesFlag Bits[31:16]
#define NUM_REMAIN_RATES_SHIFT 16 #define NUM_REMAIN_RATES_SHIFT 16
#define NUM_REMAIN_RATES(RatesFlags) ((RatesFlags >> NUM_REMAIN_RATES_SHIFT)) #define NUM_REMAIN_RATES(RatesFlags) ((RatesFlags >> NUM_REMAIN_RATES_SHIFT))
// Number of rates that are returned by a call.to the SCP, RatesFlag Bits[11:0] // Number of rates that are returned by a call.to the SCP, RatesFlag Bits[11:0]
#define NUM_RATES_MASK 0x0FFF #define NUM_RATES_MASK 0x0FFF
#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK) #define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK)
// Return values for the CLOCK_DESCRIBER_RATE command. // Return values for the CLOCK_DESCRIBER_RATE command.
typedef struct { typedef struct {
UINT32 NumRatesFlags; UINT32 NumRatesFlags;
// NOTE: Since EDK2 does not allow flexible array member [] we declare // NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable // here array of 1 element length. However below is used as a variable
// length array. // length array.
CLOCK_RATE_DWORD Rates[1]; CLOCK_RATE_DWORD Rates[1];
} CLOCK_DESCRIBE_RATES; } CLOCK_DESCRIBE_RATES;
#define CLOCK_SET_DEFAULT_FLAGS 0 #define CLOCK_SET_DEFAULT_FLAGS 0
// Message parameters for CLOCK_RATE_SET command. // Message parameters for CLOCK_RATE_SET command.
typedef struct { typedef struct {
UINT32 Flags; UINT32 Flags;
UINT32 ClockId; UINT32 ClockId;
CLOCK_RATE_DWORD Rate; CLOCK_RATE_DWORD Rate;
} CLOCK_RATE_SET_ATTRIBUTES; } CLOCK_RATE_SET_ATTRIBUTES;
// Message parameters for CLOCK_CONFIG_SET command. // Message parameters for CLOCK_CONFIG_SET command.
typedef struct { typedef struct {
UINT32 ClockId; UINT32 ClockId;
UINT32 Attributes; UINT32 Attributes;
} CLOCK_CONFIG_SET_ATTRIBUTES; } CLOCK_CONFIG_SET_ATTRIBUTES;
// if ClockAttr Bit[0] is set then clock device is enabled. // if ClockAttr Bit[0] is set then clock device is enabled.
#define CLOCK_ENABLE_MASK 0x1 #define CLOCK_ENABLE_MASK 0x1
#define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) == 1) #define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) == 1)
typedef struct { typedef struct {
UINT32 Attributes; UINT32 Attributes;
UINT8 ClockName[SCMI_MAX_STR_LEN]; UINT8 ClockName[SCMI_MAX_STR_LEN];
} CLOCK_ATTRIBUTES; } CLOCK_ATTRIBUTES;
#pragma pack() #pragma pack()
@ -79,7 +78,7 @@ typedef struct {
**/ **/
EFI_STATUS EFI_STATUS
ScmiClockProtocolInit ( ScmiClockProtocolInit (
IN EFI_HANDLE *Handle IN EFI_HANDLE *Handle
); );
#endif /* ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ */ #endif /* ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ */

12
ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h
View File

@ -15,23 +15,23 @@
#include <Protocol/ArmScmiPerformanceProtocol.h> #include <Protocol/ArmScmiPerformanceProtocol.h>
// Number of performance levels returned by a call to the SCP, Lvls Bits[11:0] // Number of performance levels returned by a call to the SCP, Lvls Bits[11:0]
#define NUM_PERF_LEVELS_MASK 0x0FFF #define NUM_PERF_LEVELS_MASK 0x0FFF
#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK) #define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK)
// Number of performance levels remaining after a call to the SCP, Lvls Bits[31:16] // Number of performance levels remaining after a call to the SCP, Lvls Bits[31:16]
#define NUM_REMAIN_PERF_LEVELS_SHIFT 16 #define NUM_REMAIN_PERF_LEVELS_SHIFT 16
#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT) #define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
/** Return values for ScmiMessageIdPerformanceDescribeLevels command. /** Return values for ScmiMessageIdPerformanceDescribeLevels command.
SCMI Spec section 4.5.2.5 SCMI Spec section 4.5.2.5
**/ **/
typedef struct { typedef struct {
UINT32 NumLevels; UINT32 NumLevels;
// NOTE: Since EDK2 does not allow flexible array member [] we declare // NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable // here array of 1 element length. However below is used as a variable
// length array. // length array.
SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels
} PERF_DESCRIBE_LEVELS; } PERF_DESCRIBE_LEVELS;
/** Initialize performance management protocol and install on a given Handle. /** Initialize performance management protocol and install on a given Handle.
@ -43,7 +43,7 @@ typedef struct {
**/ **/
EFI_STATUS EFI_STATUS
ScmiPerformanceProtocolInit ( ScmiPerformanceProtocolInit (
IN EFI_HANDLE* Handle IN EFI_HANDLE *Handle
); );
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ */ #endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ */

18
ArmPkg/Drivers/ArmScmiDxe/Scmi.c
View File

@ -29,7 +29,7 @@
**/ **/
EFI_STATUS EFI_STATUS
ScmiCommandGetPayload ( ScmiCommandGetPayload (
OUT UINT32** Payload OUT UINT32 **Payload
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -76,7 +76,7 @@ EFI_STATUS
ScmiCommandExecute ( ScmiCommandExecute (
IN SCMI_COMMAND *Command, IN SCMI_COMMAND *Command,
IN OUT UINT32 *PayloadLength, IN OUT UINT32 *PayloadLength,
OUT UINT32 **ReturnValues OPTIONAL OUT UINT32 **ReturnValues OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -121,10 +121,12 @@ ScmiCommandExecute (
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel); Response = (SCMI_MESSAGE_RESPONSE *)MtlGetChannelPayload (Channel);
if (Response->Status != ScmiSuccess) { if (Response->Status != ScmiSuccess) {
DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n", DEBUG ((
DEBUG_ERROR,
"SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
Command->ProtocolId, Command->ProtocolId,
Command->MessageId, Command->MessageId,
Response->Status Response->Status
@ -163,7 +165,7 @@ ScmiProtocolDiscoveryCommon (
SCMI_COMMAND Command; SCMI_COMMAND Command;
UINT32 PayloadLength; UINT32 PayloadLength;
PayloadLength = 0; PayloadLength = 0;
Command.ProtocolId = ProtocolId; Command.ProtocolId = ProtocolId;
Command.MessageId = MessageId; Command.MessageId = MessageId;
@ -190,13 +192,13 @@ ScmiGetProtocolVersion (
OUT UINT32 *Version OUT UINT32 *Version
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 *ProtocolVersion; UINT32 *ProtocolVersion;
Status = ScmiProtocolDiscoveryCommon ( Status = ScmiProtocolDiscoveryCommon (
ProtocolId, ProtocolId,
ScmiMessageIdProtocolVersion, ScmiMessageIdProtocolVersion,
(UINT32**)&ProtocolVersion (UINT32 **)&ProtocolVersion
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;

11
ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c
View File

@ -106,9 +106,9 @@ BaseDiscoverVendorDetails (
} }
AsciiStrCpyS ( AsciiStrCpyS (
(CHAR8*)VendorIdentifier, (CHAR8 *)VendorIdentifier,
SCMI_MAX_STR_LEN, SCMI_MAX_STR_LEN,
(CONST CHAR8*)ReturnValues (CONST CHAR8 *)ReturnValues
); );
return EFI_SUCCESS; return EFI_SUCCESS;
@ -256,7 +256,6 @@ BaseDiscoverListProtocols (
Skip = 0; Skip = 0;
while (Skip < TotalProtocols) { while (Skip < TotalProtocols) {
*MessageParams = Skip; *MessageParams = Skip;
// Note PayloadLength is a IN/OUT parameter. // Note PayloadLength is a IN/OUT parameter.
@ -265,7 +264,7 @@ BaseDiscoverListProtocols (
Status = ScmiCommandExecute ( Status = ScmiCommandExecute (
&Cmd, &Cmd,
&PayloadLength, &PayloadLength,
(UINT32**)&DiscoverList (UINT32 **)&DiscoverList
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
@ -282,7 +281,7 @@ BaseDiscoverListProtocols (
} }
// Instance of the SCMI Base protocol. // Instance of the SCMI Base protocol.
STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = { STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {
BaseGetVersion, BaseGetVersion,
BaseGetTotalProtocols, BaseGetTotalProtocols,
BaseDiscoverVendor, BaseDiscoverVendor,
@ -300,7 +299,7 @@ STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {
**/ **/
EFI_STATUS EFI_STATUS
ScmiBaseProtocolInit ( ScmiBaseProtocolInit (
IN OUT EFI_HANDLE* Handle IN OUT EFI_HANDLE *Handle
) )
{ {
return gBS->InstallMultipleProtocolInterfaces ( return gBS->InstallMultipleProtocolInterfaces (

122
ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c
View File

@ -28,11 +28,11 @@
STATIC STATIC
UINT64 UINT64
ConvertTo64Bit ( ConvertTo64Bit (
IN UINT32 Low, IN UINT32 Low,
IN UINT32 High IN UINT32 High
) )
{ {
return (Low | ((UINT64)High << 32)); return (Low | ((UINT64)High << 32));
} }
/** Return version of the clock management protocol supported by SCP firmware. /** Return version of the clock management protocol supported by SCP firmware.
@ -74,7 +74,7 @@ ClockGetTotalClocks (
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 *ReturnValues; UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues); Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -108,12 +108,12 @@ ClockGetClockAttributes (
OUT CHAR8 *ClockAsciiName OUT CHAR8 *ClockAsciiName
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 *MessageParams; UINT32 *MessageParams;
CLOCK_ATTRIBUTES *ClockAttributes; CLOCK_ATTRIBUTES *ClockAttributes;
SCMI_COMMAND Cmd; SCMI_COMMAND Cmd;
UINT32 PayloadLength; UINT32 PayloadLength;
Status = ScmiCommandGetPayload (&MessageParams); Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -130,18 +130,19 @@ ClockGetClockAttributes (
Status = ScmiCommandExecute ( Status = ScmiCommandExecute (
&Cmd, &Cmd,
&PayloadLength, &PayloadLength,
(UINT32**)&ClockAttributes (UINT32 **)&ClockAttributes
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// TRUE if bit 0 of ClockAttributes->Attributes is set.
// TRUE if bit 0 of ClockAttributes->Attributes is set.
*Enabled = CLOCK_ENABLED (ClockAttributes->Attributes); *Enabled = CLOCK_ENABLED (ClockAttributes->Attributes);
AsciiStrCpyS ( AsciiStrCpyS (
ClockAsciiName, ClockAsciiName,
SCMI_MAX_STR_LEN, SCMI_MAX_STR_LEN,
(CONST CHAR8*)ClockAttributes->ClockName (CONST CHAR8 *)ClockAttributes->ClockName
); );
return EFI_SUCCESS; return EFI_SUCCESS;
@ -174,29 +175,29 @@ STATIC
EFI_STATUS EFI_STATUS
ClockDescribeRates ( ClockDescribeRates (
IN SCMI_CLOCK_PROTOCOL *This, IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format, OUT SCMI_CLOCK_RATE_FORMAT *Format,
OUT UINT32 *TotalRates, OUT UINT32 *TotalRates,
IN OUT UINT32 *RateArraySize, IN OUT UINT32 *RateArraySize,
OUT SCMI_CLOCK_RATE *RateArray OUT SCMI_CLOCK_RATE *RateArray
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 PayloadLength; UINT32 PayloadLength;
SCMI_COMMAND Cmd; SCMI_COMMAND Cmd;
UINT32 *MessageParams; UINT32 *MessageParams;
CLOCK_DESCRIBE_RATES *DescribeRates; CLOCK_DESCRIBE_RATES *DescribeRates;
CLOCK_RATE_DWORD *Rate; CLOCK_RATE_DWORD *Rate;
UINT32 RequiredArraySize; UINT32 RequiredArraySize;
UINT32 RateIndex; UINT32 RateIndex;
UINT32 RateNo; UINT32 RateNo;
UINT32 RateOffset; UINT32 RateOffset;
*TotalRates = 0; *TotalRates = 0;
RequiredArraySize = 0; RequiredArraySize = 0;
RateIndex = 0; RateIndex = 0;
Status = ScmiCommandGetPayload (&MessageParams); Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -206,20 +207,19 @@ ClockDescribeRates (
Cmd.ProtocolId = ScmiProtocolIdClock; Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockDescribeRates; Cmd.MessageId = ScmiMessageIdClockDescribeRates;
*MessageParams++ = ClockId; *MessageParams++ = ClockId;
do { do {
*MessageParams = RateIndex; *MessageParams = RateIndex;
// Set Payload length, note PayloadLength is a IN/OUT parameter. // Set Payload length, note PayloadLength is a IN/OUT parameter.
PayloadLength = sizeof (ClockId) + sizeof (RateIndex); PayloadLength = sizeof (ClockId) + sizeof (RateIndex);
// Execute and wait for response on a SCMI channel. // Execute and wait for response on a SCMI channel.
Status = ScmiCommandExecute ( Status = ScmiCommandExecute (
&Cmd, &Cmd,
&PayloadLength, &PayloadLength,
(UINT32**)&DescribeRates (UINT32 **)&DescribeRates
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
@ -237,10 +237,10 @@ ClockDescribeRates (
+ NUM_REMAIN_RATES (DescribeRates->NumRatesFlags); + NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
if (*Format == ScmiClockRateFormatDiscrete) { if (*Format == ScmiClockRateFormatDiscrete) {
RequiredArraySize = (*TotalRates) * sizeof (UINT64); RequiredArraySize = (*TotalRates) * sizeof (UINT64);
} else { } else {
// We need to return triplet of 64 bit value for each rate // We need to return triplet of 64 bit value for each rate
RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64); RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64);
} }
if (RequiredArraySize > (*RateArraySize)) { if (RequiredArraySize > (*RateArraySize)) {
@ -262,7 +262,7 @@ ClockDescribeRates (
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) { for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
// Linear clock rates from minimum to maximum in steps // Linear clock rates from minimum to maximum in steps
// Minimum clock rate. // Minimum clock rate.
Rate = &DescribeRates->Rates[RateOffset++]; Rate = &DescribeRates->Rates[RateOffset++];
RateArray[RateIndex].ContinuousRate.Min = RateArray[RateIndex].ContinuousRate.Min =
ConvertTo64Bit (Rate->Low, Rate->High); ConvertTo64Bit (Rate->Low, Rate->High);
@ -304,13 +304,13 @@ ClockRateGet (
OUT UINT64 *Rate OUT UINT64 *Rate
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 *MessageParams; UINT32 *MessageParams;
CLOCK_RATE_DWORD *ClockRate; CLOCK_RATE_DWORD *ClockRate;
SCMI_COMMAND Cmd; SCMI_COMMAND Cmd;
UINT32 PayloadLength; UINT32 PayloadLength;
Status = ScmiCommandGetPayload (&MessageParams); Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -318,10 +318,10 @@ ClockRateGet (
} }
// Fill arguments for clock protocol command. // Fill arguments for clock protocol command.
*MessageParams = ClockId; *MessageParams = ClockId;
Cmd.ProtocolId = ScmiProtocolIdClock; Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockRateGet; Cmd.MessageId = ScmiMessageIdClockRateGet;
PayloadLength = sizeof (ClockId); PayloadLength = sizeof (ClockId);
@ -329,7 +329,7 @@ ClockRateGet (
Status = ScmiCommandExecute ( Status = ScmiCommandExecute (
&Cmd, &Cmd,
&PayloadLength, &PayloadLength,
(UINT32**)&ClockRate (UINT32 **)&ClockRate
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
@ -358,21 +358,21 @@ ClockRateSet (
IN UINT64 Rate IN UINT64 Rate
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes; CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes;
SCMI_COMMAND Cmd; SCMI_COMMAND Cmd;
UINT32 PayloadLength; UINT32 PayloadLength;
Status = ScmiCommandGetPayload ((UINT32**)&ClockRateSetAttributes); Status = ScmiCommandGetPayload ((UINT32 **)&ClockRateSetAttributes);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// Fill arguments for clock protocol command. // Fill arguments for clock protocol command.
ClockRateSetAttributes->ClockId = ClockId; ClockRateSetAttributes->ClockId = ClockId;
ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS; ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS;
ClockRateSetAttributes->Rate.Low = (UINT32)Rate; ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32); ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
Cmd.ProtocolId = ScmiProtocolIdClock; Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockRateSet; Cmd.MessageId = ScmiMessageIdClockRateSet;
@ -402,17 +402,17 @@ ClockRateSet (
STATIC STATIC
EFI_STATUS EFI_STATUS
ClockEnable ( ClockEnable (
IN SCMI_CLOCK2_PROTOCOL *This, IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
IN BOOLEAN Enable IN BOOLEAN Enable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes; CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes;
SCMI_COMMAND Cmd; SCMI_COMMAND Cmd;
UINT32 PayloadLength; UINT32 PayloadLength;
Status = ScmiCommandGetPayload ((UINT32**)&ClockConfigSetAttributes); Status = ScmiCommandGetPayload ((UINT32 **)&ClockConfigSetAttributes);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
@ -437,17 +437,17 @@ ClockEnable (
} }
// Instance of the SCMI clock management protocol. // Instance of the SCMI clock management protocol.
STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = { STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = {
ClockGetVersion, ClockGetVersion,
ClockGetTotalClocks, ClockGetTotalClocks,
ClockGetClockAttributes, ClockGetClockAttributes,
ClockDescribeRates, ClockDescribeRates,
ClockRateGet, ClockRateGet,
ClockRateSet ClockRateSet
}; };
// Instance of the SCMI clock management protocol. // Instance of the SCMI clock management protocol.
STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = { STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
(SCMI_CLOCK2_GET_VERSION)ClockGetVersion, (SCMI_CLOCK2_GET_VERSION)ClockGetVersion,
(SCMI_CLOCK2_GET_TOTAL_CLOCKS)ClockGetTotalClocks, (SCMI_CLOCK2_GET_TOTAL_CLOCKS)ClockGetTotalClocks,
(SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)ClockGetClockAttributes, (SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)ClockGetClockAttributes,
@ -456,7 +456,7 @@ STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
(SCMI_CLOCK2_RATE_SET)ClockRateSet, (SCMI_CLOCK2_RATE_SET)ClockRateSet,
SCMI_CLOCK2_PROTOCOL_VERSION, SCMI_CLOCK2_PROTOCOL_VERSION,
ClockEnable ClockEnable
}; };
/** Initialize clock management protocol and install protocol on a given handle. /** Initialize clock management protocol and install protocol on a given handle.
@ -466,7 +466,7 @@ STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
**/ **/
EFI_STATUS EFI_STATUS
ScmiClockProtocolInit ( ScmiClockProtocolInit (
IN EFI_HANDLE* Handle IN EFI_HANDLE *Handle
) )
{ {
return gBS->InstallMultipleProtocolInterfaces ( return gBS->InstallMultipleProtocolInterfaces (

23
ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c
View File

@ -23,10 +23,10 @@
#include "ScmiDxe.h" #include "ScmiDxe.h"
#include "ScmiPrivate.h" #include "ScmiPrivate.h"
STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = { STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
{ ScmiProtocolIdBase, ScmiBaseProtocolInit }, { ScmiProtocolIdBase, ScmiBaseProtocolInit },
{ ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit }, { ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit },
{ ScmiProtocolIdClock, ScmiClockProtocolInit } { ScmiProtocolIdClock, ScmiClockProtocolInit }
}; };
/** ARM SCMI driver entry point function. /** ARM SCMI driver entry point function.
@ -47,8 +47,8 @@ STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
ArmScmiDxeEntryPoint ( ArmScmiDxeEntryPoint (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -72,7 +72,7 @@ ArmScmiDxeEntryPoint (
Status = gBS->LocateProtocol ( Status = gBS->LocateProtocol (
&gArmScmiBaseProtocolGuid, &gArmScmiBaseProtocolGuid,
NULL, NULL,
(VOID**)&BaseProtocol (VOID **)&BaseProtocol
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
ASSERT (FALSE); ASSERT (FALSE);
@ -88,7 +88,8 @@ ArmScmiDxeEntryPoint (
// Accept any version between SCMI v1.0 and SCMI v2.0 // Accept any version between SCMI v1.0 and SCMI v2.0
if ((Version < BASE_PROTOCOL_VERSION_V1) || if ((Version < BASE_PROTOCOL_VERSION_V1) ||
(Version > BASE_PROTOCOL_VERSION_V2)) { (Version > BASE_PROTOCOL_VERSION_V2))
{
ASSERT (FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -96,7 +97,7 @@ ArmScmiDxeEntryPoint (
// Apart from Base protocol, SCMI may implement various other protocols, // Apart from Base protocol, SCMI may implement various other protocols,
// query total protocols implemented by the SCP firmware. // query total protocols implemented by the SCP firmware.
NumProtocols = 0; NumProtocols = 0;
Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols); Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
ASSERT (FALSE); ASSERT (FALSE);
return Status; return Status;
@ -109,7 +110,7 @@ ArmScmiDxeEntryPoint (
Status = gBS->AllocatePool ( Status = gBS->AllocatePool (
EfiBootServicesData, EfiBootServicesData,
SupportedListSize, SupportedListSize,
(VOID**)&SupportedList (VOID **)&SupportedList
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
ASSERT (FALSE); ASSERT (FALSE);
@ -130,7 +131,8 @@ ArmScmiDxeEntryPoint (
// Install supported protocol on ImageHandle. // Install supported protocol on ImageHandle.
for (ProtocolIndex = 1; ProtocolIndex < ARRAY_SIZE (Protocols); for (ProtocolIndex = 1; ProtocolIndex < ARRAY_SIZE (Protocols);
ProtocolIndex++) { ProtocolIndex++)
{
for (Index = 0; Index < NumProtocols; Index++) { for (Index = 0; Index < NumProtocols; Index++) {
if (Protocols[ProtocolIndex].Id == SupportedList[Index]) { if (Protocols[ProtocolIndex].Id == SupportedList[Index]) {
Status = Protocols[ProtocolIndex].InitFn (&ImageHandle); Status = Protocols[ProtocolIndex].InitFn (&ImageHandle);
@ -138,6 +140,7 @@ ArmScmiDxeEntryPoint (
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return Status; return Status;
} }
break; break;
} }
} }

7
ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h
View File

@ -8,12 +8,13 @@
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
DEN0056A_System_Control_and_Management_Interface.pdf DEN0056A_System_Control_and_Management_Interface.pdf
**/ **/
#ifndef SCMI_DXE_H_ #ifndef SCMI_DXE_H_
#define SCMI_DXE_H_ #define SCMI_DXE_H_
#include "ScmiPrivate.h" #include "ScmiPrivate.h"
#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN #define MAX_VENDOR_LEN SCMI_MAX_STR_LEN
/** Pointer to protocol initialization function. /** Pointer to protocol initialization function.
@ -29,8 +30,8 @@ EFI_STATUS
); );
typedef struct { typedef struct {
SCMI_PROTOCOL_ID Id; // Protocol Id. SCMI_PROTOCOL_ID Id; // Protocol Id.
SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function. SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function.
} SCMI_PROTOCOL_ENTRY; } SCMI_PROTOCOL_ENTRY;
#endif /* SCMI_DXE_H_ */ #endif /* SCMI_DXE_H_ */

60
ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c
View File

@ -51,12 +51,12 @@ PerformanceGetVersion (
STATIC STATIC
EFI_STATUS EFI_STATUS
PerformanceGetAttributes ( PerformanceGetAttributes (
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32* ReturnValues; UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes ( Status = ScmiGetProtocolAttributes (
ScmiProtocolIdPerformance, ScmiProtocolIdPerformance,
@ -90,7 +90,7 @@ STATIC
EFI_STATUS EFI_STATUS
PerformanceDomainAttributes ( PerformanceDomainAttributes (
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
) )
{ {
@ -160,21 +160,21 @@ PerformanceDescribeLevels (
EFI_STATUS Status; EFI_STATUS Status;
UINT32 PayloadLength; UINT32 PayloadLength;
SCMI_COMMAND Cmd; SCMI_COMMAND Cmd;
UINT32* MessageParams; UINT32 *MessageParams;
UINT32 LevelIndex; UINT32 LevelIndex;
UINT32 RequiredSize; UINT32 RequiredSize;
UINT32 LevelNo; UINT32 LevelNo;
UINT32 ReturnNumLevels; UINT32 ReturnNumLevels;
UINT32 ReturnRemainNumLevels; UINT32 ReturnRemainNumLevels;
PERF_DESCRIBE_LEVELS *Levels; PERF_DESCRIBE_LEVELS *Levels;
Status = ScmiCommandGetPayload (&MessageParams); Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
LevelIndex = 0; LevelIndex = 0;
RequiredSize = 0; RequiredSize = 0;
*MessageParams++ = DomainId; *MessageParams++ = DomainId;
@ -183,7 +183,6 @@ PerformanceDescribeLevels (
Cmd.MessageId = ScmiMessageIdPerformanceDescribeLevels; Cmd.MessageId = ScmiMessageIdPerformanceDescribeLevels;
do { do {
*MessageParams = LevelIndex; *MessageParams = LevelIndex;
// Note, PayloadLength is an IN/OUT parameter. // Note, PayloadLength is an IN/OUT parameter.
@ -192,13 +191,13 @@ PerformanceDescribeLevels (
Status = ScmiCommandExecute ( Status = ScmiCommandExecute (
&Cmd, &Cmd,
&PayloadLength, &PayloadLength,
(UINT32**)&Levels (UINT32 **)&Levels
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels); ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels);
ReturnRemainNumLevels = NUM_REMAIN_PERF_LEVELS (Levels->NumLevels); ReturnRemainNumLevels = NUM_REMAIN_PERF_LEVELS (Levels->NumLevels);
if (RequiredSize == 0) { if (RequiredSize == 0) {
@ -213,13 +212,12 @@ PerformanceDescribeLevels (
} }
for (LevelNo = 0; LevelNo < ReturnNumLevels; LevelNo++) { for (LevelNo = 0; LevelNo < ReturnNumLevels; LevelNo++) {
CopyMem ( CopyMem (
&LevelArray[LevelIndex++], &LevelArray[LevelIndex++],
&Levels->PerfLevel[LevelNo], &Levels->PerfLevel[LevelNo],
sizeof (SCMI_PERFORMANCE_LEVEL) sizeof (SCMI_PERFORMANCE_LEVEL)
); );
} }
} while (ReturnRemainNumLevels != 0); } while (ReturnRemainNumLevels != 0);
*LevelArraySize = RequiredSize; *LevelArraySize = RequiredSize;
@ -239,9 +237,9 @@ PerformanceDescribeLevels (
**/ **/
EFI_STATUS EFI_STATUS
PerformanceLimitsSet ( PerformanceLimitsSet (
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
IN SCMI_PERFORMANCE_LIMITS *Limits IN SCMI_PERFORMANCE_LIMITS *Limits
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -285,9 +283,9 @@ PerformanceLimitsSet (
**/ **/
EFI_STATUS EFI_STATUS
PerformanceLimitsGet ( PerformanceLimitsGet (
SCMI_PERFORMANCE_PROTOCOL *This, SCMI_PERFORMANCE_PROTOCOL *This,
UINT32 DomainId, UINT32 DomainId,
SCMI_PERFORMANCE_LIMITS *Limits SCMI_PERFORMANCE_LIMITS *Limits
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -312,7 +310,7 @@ PerformanceLimitsGet (
Status = ScmiCommandExecute ( Status = ScmiCommandExecute (
&Cmd, &Cmd,
&PayloadLength, &PayloadLength,
(UINT32**)&ReturnValues (UINT32 **)&ReturnValues
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
@ -336,9 +334,9 @@ PerformanceLimitsGet (
**/ **/
EFI_STATUS EFI_STATUS
PerformanceLevelSet ( PerformanceLevelSet (
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
IN UINT32 Level IN UINT32 Level
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -381,9 +379,9 @@ PerformanceLevelSet (
**/ **/
EFI_STATUS EFI_STATUS
PerformanceLevelGet ( PerformanceLevelGet (
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
OUT UINT32 *Level OUT UINT32 *Level
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -419,7 +417,7 @@ PerformanceLevelGet (
} }
// Instance of the SCMI performance management protocol. // Instance of the SCMI performance management protocol.
STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = { STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {
PerformanceGetVersion, PerformanceGetVersion,
PerformanceGetAttributes, PerformanceGetAttributes,
PerformanceDomainAttributes, PerformanceDomainAttributes,
@ -439,7 +437,7 @@ STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {
**/ **/
EFI_STATUS EFI_STATUS
ScmiPerformanceProtocolInit ( ScmiPerformanceProtocolInit (
IN EFI_HANDLE* Handle IN EFI_HANDLE *Handle
) )
{ {
return gBS->InstallMultipleProtocolInterfaces ( return gBS->InstallMultipleProtocolInterfaces (

19
ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h
View File

@ -8,6 +8,7 @@
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
DEN0056A_System_Control_and_Management_Interface.pdf DEN0056A_System_Control_and_Management_Interface.pdf
**/ **/
#ifndef SCMI_PRIVATE_H_ #ifndef SCMI_PRIVATE_H_
#define SCMI_PRIVATE_H_ #define SCMI_PRIVATE_H_
@ -52,21 +53,21 @@ typedef enum {
// Not defined in SCMI specification but will help to identify a message. // Not defined in SCMI specification but will help to identify a message.
typedef struct { typedef struct {
SCMI_PROTOCOL_ID ProtocolId; SCMI_PROTOCOL_ID ProtocolId;
UINT32 MessageId; UINT32 MessageId;
} SCMI_COMMAND; } SCMI_COMMAND;
#pragma pack(1) #pragma pack(1)
// Response to a SCMI command. // Response to a SCMI command.
typedef struct { typedef struct {
INT32 Status; INT32 Status;
UINT32 ReturnValues[]; UINT32 ReturnValues[];
} SCMI_MESSAGE_RESPONSE; } SCMI_MESSAGE_RESPONSE;
// Message header. MsgId[7:0], MsgType[9:8], ProtocolId[17:10] // Message header. MsgId[7:0], MsgType[9:8], ProtocolId[17:10]
#define MESSAGE_TYPE_SHIFT 8 #define MESSAGE_TYPE_SHIFT 8
#define PROTOCOL_ID_SHIFT 10 #define PROTOCOL_ID_SHIFT 10
#define SCMI_MESSAGE_HEADER(MsgId, MsgType, ProtocolId) ( \ #define SCMI_MESSAGE_HEADER(MsgId, MsgType, ProtocolId) ( \
MsgType << MESSAGE_TYPE_SHIFT | \ MsgType << MESSAGE_TYPE_SHIFT | \
ProtocolId << PROTOCOL_ID_SHIFT | \ ProtocolId << PROTOCOL_ID_SHIFT | \
@ -74,7 +75,7 @@ typedef struct {
) )
// SCMI message header. // SCMI message header.
typedef struct { typedef struct {
UINT32 MessageHeader; UINT32 MessageHeader;
} SCMI_MESSAGE_HEADER; } SCMI_MESSAGE_HEADER;
#pragma pack() #pragma pack()
@ -89,7 +90,7 @@ typedef struct {
**/ **/
EFI_STATUS EFI_STATUS
ScmiCommandGetPayload ( ScmiCommandGetPayload (
OUT UINT32** Payload OUT UINT32 **Payload
); );
/** Execute a SCMI command and receive a response. /** Execute a SCMI command and receive a response.
@ -115,7 +116,7 @@ EFI_STATUS
ScmiCommandExecute ( ScmiCommandExecute (
IN SCMI_COMMAND *Command, IN SCMI_COMMAND *Command,
IN OUT UINT32 *PayloadLength, IN OUT UINT32 *PayloadLength,
OUT UINT32 **ReturnValues OPTIONAL OUT UINT32 **ReturnValues OPTIONAL
); );
/** Return protocol version from SCP for a given protocol ID. /** Return protocol version from SCP for a given protocol ID.

291
ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c
View File

@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
#include "CpuDxe.h" #include "CpuDxe.h"
#define INVALID_ENTRY ((UINT32)~0) #define INVALID_ENTRY ((UINT32)~0)
#define MIN_T0SZ 16 #define MIN_T0SZ 16
#define BITS_PER_LEVEL 9 #define BITS_PER_LEVEL 9
@ -21,49 +21,52 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
STATIC STATIC
VOID VOID
GetRootTranslationTableInfo ( GetRootTranslationTableInfo (
IN UINTN T0SZ, IN UINTN T0SZ,
OUT UINTN *RootTableLevel, OUT UINTN *RootTableLevel,
OUT UINTN *RootTableEntryCount OUT UINTN *RootTableEntryCount
) )
{ {
*RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL; *RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
*RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL; *RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
} }
STATIC STATIC
UINT64 UINT64
PageAttributeToGcdAttribute ( PageAttributeToGcdAttribute (
IN UINT64 PageAttributes IN UINT64 PageAttributes
) )
{ {
UINT64 GcdAttributes; UINT64 GcdAttributes;
switch (PageAttributes & TT_ATTR_INDX_MASK) { switch (PageAttributes & TT_ATTR_INDX_MASK) {
case TT_ATTR_INDX_DEVICE_MEMORY: case TT_ATTR_INDX_DEVICE_MEMORY:
GcdAttributes = EFI_MEMORY_UC; GcdAttributes = EFI_MEMORY_UC;
break; break;
case TT_ATTR_INDX_MEMORY_NON_CACHEABLE: case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
GcdAttributes = EFI_MEMORY_WC; GcdAttributes = EFI_MEMORY_WC;
break; break;
case TT_ATTR_INDX_MEMORY_WRITE_THROUGH: case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
GcdAttributes = EFI_MEMORY_WT; GcdAttributes = EFI_MEMORY_WT;
break; break;
case TT_ATTR_INDX_MEMORY_WRITE_BACK: case TT_ATTR_INDX_MEMORY_WRITE_BACK:
GcdAttributes = EFI_MEMORY_WB; GcdAttributes = EFI_MEMORY_WB;
break; break;
default: default:
DEBUG ((DEBUG_ERROR, DEBUG ((
"PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", DEBUG_ERROR,
PageAttributes)); "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",
ASSERT (0); PageAttributes
// The Global Coherency Domain (GCD) value is defined as a bit set. ));
// Returning 0 means no attribute has been set. ASSERT (0);
GcdAttributes = 0; // The Global Coherency Domain (GCD) value is defined as a bit set.
// Returning 0 means no attribute has been set.
GcdAttributes = 0;
} }
// Determine protection attributes // Determine protection attributes
if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) ||
((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) { ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO))
{
// Read only cases map to write-protect // Read only cases map to write-protect
GcdAttributes |= EFI_MEMORY_RO; GcdAttributes |= EFI_MEMORY_RO;
} }
@ -80,19 +83,19 @@ STATIC
UINT64 UINT64
GetFirstPageAttribute ( GetFirstPageAttribute (
IN UINT64 *FirstLevelTableAddress, IN UINT64 *FirstLevelTableAddress,
IN UINTN TableLevel IN UINTN TableLevel
) )
{ {
UINT64 FirstEntry; UINT64 FirstEntry;
// Get the first entry of the table // Get the first entry of the table
FirstEntry = *FirstLevelTableAddress; FirstEntry = *FirstLevelTableAddress;
if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) { if ((TableLevel != 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
// Only valid for Levels 0, 1 and 2 // Only valid for Levels 0, 1 and 2
// Get the attribute of the subsequent table // Get the attribute of the subsequent table
return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1); return GetFirstPageAttribute ((UINT64 *)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);
} else if (((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) || } else if (((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) ||
((TableLevel == 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3))) ((TableLevel == 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3)))
{ {
@ -105,25 +108,25 @@ GetFirstPageAttribute (
STATIC STATIC
UINT64 UINT64
GetNextEntryAttribute ( GetNextEntryAttribute (
IN UINT64 *TableAddress, IN UINT64 *TableAddress,
IN UINTN EntryCount, IN UINTN EntryCount,
IN UINTN TableLevel, IN UINTN TableLevel,
IN UINT64 BaseAddress, IN UINT64 BaseAddress,
IN OUT UINT32 *PrevEntryAttribute, IN OUT UINT32 *PrevEntryAttribute,
IN OUT UINT64 *StartGcdRegion IN OUT UINT64 *StartGcdRegion
) )
{ {
UINTN Index; UINTN Index;
UINT64 Entry; UINT64 Entry;
UINT32 EntryAttribute; UINT32 EntryAttribute;
UINT32 EntryType; UINT32 EntryType;
EFI_STATUS Status; EFI_STATUS Status;
UINTN NumberOfDescriptors; UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
// Get the memory space map from GCD // Get the memory space map from GCD
MemorySpaceMap = NULL; MemorySpaceMap = NULL;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// We cannot get more than 3-level page table // We cannot get more than 3-level page table
@ -132,24 +135,28 @@ GetNextEntryAttribute (
// While the top level table might not contain TT_ENTRY_COUNT entries; // While the top level table might not contain TT_ENTRY_COUNT entries;
// the subsequent ones should be filled up // the subsequent ones should be filled up
for (Index = 0; Index < EntryCount; Index++) { for (Index = 0; Index < EntryCount; Index++) {
Entry = TableAddress[Index]; Entry = TableAddress[Index];
EntryType = Entry & TT_TYPE_MASK; EntryType = Entry & TT_TYPE_MASK;
EntryAttribute = Entry & TT_ATTR_INDX_MASK; EntryAttribute = Entry & TT_ATTR_INDX_MASK;
// If Entry is a Table Descriptor type entry then go through the sub-level table // If Entry is a Table Descriptor type entry then go through the sub-level table
if ((EntryType == TT_TYPE_BLOCK_ENTRY) || if ((EntryType == TT_TYPE_BLOCK_ENTRY) ||
((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) { ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3)))
{
if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) { if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) {
if (*PrevEntryAttribute != INVALID_ENTRY) { if (*PrevEntryAttribute != INVALID_ENTRY) {
// Update GCD with the last region // Update GCD with the last region
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, SetGcdMemorySpaceAttributes (
*StartGcdRegion, MemorySpaceMap,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion, NumberOfDescriptors,
PageAttributeToGcdAttribute (*PrevEntryAttribute)); *StartGcdRegion,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))) - *StartGcdRegion,
PageAttributeToGcdAttribute (*PrevEntryAttribute)
);
} }
// Start of the new region // Start of the new region
*StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel));
*PrevEntryAttribute = EntryAttribute; *PrevEntryAttribute = EntryAttribute;
} else { } else {
continue; continue;
@ -159,20 +166,27 @@ GetNextEntryAttribute (
ASSERT (TableLevel < 3); ASSERT (TableLevel < 3);
// Increase the level number and scan the sub-level table // Increase the level number and scan the sub-level table
GetNextEntryAttribute ((UINT64*)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), GetNextEntryAttribute (
TT_ENTRY_COUNT, TableLevel + 1, (UINT64 *)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE),
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))), TT_ENTRY_COUNT,
PrevEntryAttribute, StartGcdRegion); TableLevel + 1,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))),
PrevEntryAttribute,
StartGcdRegion
);
} else { } else {
if (*PrevEntryAttribute != INVALID_ENTRY) { if (*PrevEntryAttribute != INVALID_ENTRY) {
// Update GCD with the last region // Update GCD with the last region
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, SetGcdMemorySpaceAttributes (
*StartGcdRegion, MemorySpaceMap,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion, NumberOfDescriptors,
PageAttributeToGcdAttribute (*PrevEntryAttribute)); *StartGcdRegion,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))) - *StartGcdRegion,
PageAttributeToGcdAttribute (*PrevEntryAttribute)
);
// Start of the new region // Start of the new region
*StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel));
*PrevEntryAttribute = INVALID_ENTRY; *PrevEntryAttribute = INVALID_ENTRY;
} }
} }
@ -180,25 +194,25 @@ GetNextEntryAttribute (
FreePool (MemorySpaceMap); FreePool (MemorySpaceMap);
return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL(TableLevel)); return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL (TableLevel));
} }
EFI_STATUS EFI_STATUS
SyncCacheConfig ( SyncCacheConfig (
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 PageAttribute; UINT32 PageAttribute;
UINT64 *FirstLevelTableAddress; UINT64 *FirstLevelTableAddress;
UINTN TableLevel; UINTN TableLevel;
UINTN TableCount; UINTN TableCount;
UINTN NumberOfDescriptors; UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
UINTN Tcr; UINTN Tcr;
UINTN T0SZ; UINTN T0SZ;
UINT64 BaseAddressGcdRegion; UINT64 BaseAddressGcdRegion;
UINT64 EndAddressGcdRegion; UINT64 EndAddressGcdRegion;
// This code assumes MMU is enabled and filed with section translations // This code assumes MMU is enabled and filed with section translations
ASSERT (ArmMmuEnabled ()); ASSERT (ArmMmuEnabled ());
@ -207,7 +221,7 @@ SyncCacheConfig (
// Get the memory space map from GCD // Get the memory space map from GCD
// //
MemorySpaceMap = NULL; MemorySpaceMap = NULL;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
@ -217,7 +231,7 @@ SyncCacheConfig (
// with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead. // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
// Obtain page table base // Obtain page table base
FirstLevelTableAddress = (UINT64*)(ArmGetTTBR0BaseAddress ()); FirstLevelTableAddress = (UINT64 *)(ArmGetTTBR0BaseAddress ());
// Get Translation Control Register value // Get Translation Control Register value
Tcr = ArmGetTCR (); Tcr = ArmGetTCR ();
@ -232,17 +246,24 @@ SyncCacheConfig (
// We scan from the start of the memory map (ie: at the address 0x0) // We scan from the start of the memory map (ie: at the address 0x0)
BaseAddressGcdRegion = 0x0; BaseAddressGcdRegion = 0x0;
EndAddressGcdRegion = GetNextEntryAttribute (FirstLevelTableAddress, EndAddressGcdRegion = GetNextEntryAttribute (
TableCount, TableLevel, FirstLevelTableAddress,
BaseAddressGcdRegion, TableCount,
&PageAttribute, &BaseAddressGcdRegion); TableLevel,
BaseAddressGcdRegion,
&PageAttribute,
&BaseAddressGcdRegion
);
// Update GCD with the last region if valid // Update GCD with the last region if valid
if (PageAttribute != INVALID_ENTRY) { if (PageAttribute != INVALID_ENTRY) {
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, SetGcdMemorySpaceAttributes (
BaseAddressGcdRegion, MemorySpaceMap,
EndAddressGcdRegion - BaseAddressGcdRegion, NumberOfDescriptors,
PageAttributeToGcdAttribute (PageAttribute)); BaseAddressGcdRegion,
EndAddressGcdRegion - BaseAddressGcdRegion,
PageAttributeToGcdAttribute (PageAttribute)
);
} }
FreePool (MemorySpaceMap); FreePool (MemorySpaceMap);
@ -252,30 +273,31 @@ SyncCacheConfig (
UINT64 UINT64
EfiAttributeToArmAttribute ( EfiAttributeToArmAttribute (
IN UINT64 EfiAttributes IN UINT64 EfiAttributes
) )
{ {
UINT64 ArmAttributes; UINT64 ArmAttributes;
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {
case EFI_MEMORY_UC: case EFI_MEMORY_UC:
if (ArmReadCurrentEL () == AARCH64_EL2) { if (ArmReadCurrentEL () == AARCH64_EL2) {
ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK; ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
} else { } else {
ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK; ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
} }
break;
case EFI_MEMORY_WC: break;
ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; case EFI_MEMORY_WC:
break; ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
case EFI_MEMORY_WT: break;
ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; case EFI_MEMORY_WT:
break; ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
case EFI_MEMORY_WB: break;
ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; case EFI_MEMORY_WB:
break; ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
default: break;
ArmAttributes = TT_ATTR_INDX_MASK; default:
ArmAttributes = TT_ATTR_INDX_MASK;
} }
// Set the access flag to match the block attributes // Set the access flag to match the block attributes
@ -298,19 +320,19 @@ EfiAttributeToArmAttribute (
// And then the function will identify the size of the region that has the same page table attribute. // And then the function will identify the size of the region that has the same page table attribute.
EFI_STATUS EFI_STATUS
GetMemoryRegionRec ( GetMemoryRegionRec (
IN UINT64 *TranslationTable, IN UINT64 *TranslationTable,
IN UINTN TableLevel, IN UINTN TableLevel,
IN UINT64 *LastBlockEntry, IN UINT64 *LastBlockEntry,
IN OUT UINTN *BaseAddress, IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength, OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes OUT UINTN *RegionAttributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT64 *NextTranslationTable; UINT64 *NextTranslationTable;
UINT64 *BlockEntry; UINT64 *BlockEntry;
UINT64 BlockEntryType; UINT64 BlockEntryType;
UINT64 EntryType; UINT64 EntryType;
if (TableLevel != 3) { if (TableLevel != 3) {
BlockEntryType = TT_TYPE_BLOCK_ENTRY; BlockEntryType = TT_TYPE_BLOCK_ENTRY;
@ -319,22 +341,25 @@ GetMemoryRegionRec (
} }
// Find the block entry linked to the Base Address // Find the block entry linked to the Base Address
BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress); BlockEntry = (UINT64 *)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);
EntryType = *BlockEntry & TT_TYPE_MASK; EntryType = *BlockEntry & TT_TYPE_MASK;
if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) { if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) {
NextTranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE); NextTranslationTable = (UINT64 *)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
// The entry is a page table, so we go to the next level // The entry is a page table, so we go to the next level
Status = GetMemoryRegionRec ( Status = GetMemoryRegionRec (
NextTranslationTable, // Address of the next level page table NextTranslationTable, // Address of the next level page table
TableLevel + 1, // Next Page Table level TableLevel + 1, // Next Page Table level
(UINTN*)TT_LAST_BLOCK_ADDRESS(NextTranslationTable, TT_ENTRY_COUNT), (UINTN *)TT_LAST_BLOCK_ADDRESS (NextTranslationTable, TT_ENTRY_COUNT),
BaseAddress, RegionLength, RegionAttributes); BaseAddress,
RegionLength,
RegionAttributes
);
// In case of 'Success', it means the end of the block region has been found into the upper // In case of 'Success', it means the end of the block region has been found into the upper
// level translation table // level translation table
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -343,7 +368,7 @@ GetMemoryRegionRec (
} else if (EntryType == BlockEntryType) { } else if (EntryType == BlockEntryType) {
// We have found the BlockEntry attached to the address. We save its start address (the start // We have found the BlockEntry attached to the address. We save its start address (the start
// address might be before the 'BaseAddress') and attributes // address might be before the 'BaseAddress') and attributes
*BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1); *BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL (TableLevel) - 1);
*RegionLength = 0; *RegionLength = 0;
*RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK; *RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK;
} else { } else {
@ -353,11 +378,12 @@ GetMemoryRegionRec (
while (BlockEntry <= LastBlockEntry) { while (BlockEntry <= LastBlockEntry) {
if ((*BlockEntry & TT_ATTRIBUTES_MASK) == *RegionAttributes) { if ((*BlockEntry & TT_ATTRIBUTES_MASK) == *RegionAttributes) {
*RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL(TableLevel); *RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL (TableLevel);
} else { } else {
// In case we have found the end of the region we return success // In case we have found the end of the region we return success
return EFI_SUCCESS; return EFI_SUCCESS;
} }
BlockEntry++; BlockEntry++;
} }
@ -369,13 +395,13 @@ GetMemoryRegionRec (
EFI_STATUS EFI_STATUS
GetMemoryRegion ( GetMemoryRegion (
IN OUT UINTN *BaseAddress, IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength, OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes OUT UINTN *RegionAttributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT64 *TranslationTable; UINT64 *TranslationTable;
UINTN TableLevel; UINTN TableLevel;
UINTN EntryCount; UINTN EntryCount;
UINTN T0SZ; UINTN T0SZ;
@ -388,9 +414,14 @@ GetMemoryRegion (
// Get the Table info from T0SZ // Get the Table info from T0SZ
GetRootTranslationTableInfo (T0SZ, &TableLevel, &EntryCount); GetRootTranslationTableInfo (T0SZ, &TableLevel, &EntryCount);
Status = GetMemoryRegionRec (TranslationTable, TableLevel, Status = GetMemoryRegionRec (
(UINTN*)TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount), TranslationTable,
BaseAddress, RegionLength, RegionAttributes); TableLevel,
(UINTN *)TT_LAST_BLOCK_ADDRESS (TranslationTable, EntryCount),
BaseAddress,
RegionLength,
RegionAttributes
);
// If the region continues up to the end of the root table then GetMemoryRegionRec() // If the region continues up to the end of the root table then GetMemoryRegionRec()
// will return EFI_NOT_FOUND // will return EFI_NOT_FOUND

167
ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
View File

@ -22,7 +22,7 @@ SectionToGcdAttributes (
*GcdAttributes = 0; *GcdAttributes = 0;
// determine cacheability attributes // determine cacheability attributes
switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) { switch (SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED: case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:
*GcdAttributes |= EFI_MEMORY_UC; *GcdAttributes |= EFI_MEMORY_UC;
break; break;
@ -49,9 +49,9 @@ SectionToGcdAttributes (
} }
// determine protection attributes // determine protection attributes
switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { switch (SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
//*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP; // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
break; break;
case TT_DESCRIPTOR_SECTION_AP_RW_NO: case TT_DESCRIPTOR_SECTION_AP_RW_NO:
@ -86,7 +86,7 @@ PageToGcdAttributes (
*GcdAttributes = 0; *GcdAttributes = 0;
// determine cacheability attributes // determine cacheability attributes
switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) { switch (PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {
case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED: case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:
*GcdAttributes |= EFI_MEMORY_UC; *GcdAttributes |= EFI_MEMORY_UC;
break; break;
@ -113,9 +113,9 @@ PageToGcdAttributes (
} }
// determine protection attributes // determine protection attributes
switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { switch (PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write
//*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP; // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
break; break;
case TT_DESCRIPTOR_PAGE_AP_RW_NO: case TT_DESCRIPTOR_PAGE_AP_RW_NO:
@ -143,43 +143,43 @@ PageToGcdAttributes (
EFI_STATUS EFI_STATUS
SyncCacheConfigPage ( SyncCacheConfigPage (
IN UINT32 SectionIndex, IN UINT32 SectionIndex,
IN UINT32 FirstLevelDescriptor, IN UINT32 FirstLevelDescriptor,
IN UINTN NumberOfDescriptors, IN UINTN NumberOfDescriptors,
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase, IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,
IN OUT UINT64 *NextRegionLength, IN OUT UINT64 *NextRegionLength,
IN OUT UINT32 *NextSectionAttributes IN OUT UINT32 *NextSectionAttributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 i; UINT32 i;
volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable; volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
UINT32 NextPageAttributes; UINT32 NextPageAttributes;
UINT32 PageAttributes; UINT32 PageAttributes;
UINT32 BaseAddress; UINT32 BaseAddress;
UINT64 GcdAttributes; UINT64 GcdAttributes;
// Get the Base Address from FirstLevelDescriptor; // Get the Base Address from FirstLevelDescriptor;
BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT); BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
// Convert SectionAttributes into PageAttributes // Convert SectionAttributes into PageAttributes
NextPageAttributes = NextPageAttributes =
TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) | TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes, 0) |
TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes); TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes);
// obtain page table base // obtain page table base
SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) { for (i = 0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) { if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
// extract attributes (cacheability and permissions) // extract attributes (cacheability and permissions)
PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK); PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);
if (NextPageAttributes == 0) { if (NextPageAttributes == 0) {
// start on a new region // start on a new region
*NextRegionLength = 0; *NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = PageAttributes; NextPageAttributes = PageAttributes;
} else if (PageAttributes != NextPageAttributes) { } else if (PageAttributes != NextPageAttributes) {
// Convert Section Attributes into GCD Attributes // Convert Section Attributes into GCD Attributes
@ -190,8 +190,8 @@ SyncCacheConfigPage (
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes); SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
// start on a new region // start on a new region
*NextRegionLength = 0; *NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = PageAttributes; NextPageAttributes = PageAttributes;
} }
} else if (NextPageAttributes != 0) { } else if (NextPageAttributes != 0) {
@ -202,37 +202,37 @@ SyncCacheConfigPage (
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes); SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
*NextRegionLength = 0; *NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = 0; NextPageAttributes = 0;
} }
*NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE; *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;
} }
// Convert back PageAttributes into SectionAttributes // Convert back PageAttributes into SectionAttributes
*NextSectionAttributes = *NextSectionAttributes =
TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) | TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes, 0) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes); TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
EFI_STATUS EFI_STATUS
SyncCacheConfig ( SyncCacheConfig (
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 i; UINT32 i;
EFI_PHYSICAL_ADDRESS NextRegionBase; EFI_PHYSICAL_ADDRESS NextRegionBase;
UINT64 NextRegionLength; UINT64 NextRegionLength;
UINT32 NextSectionAttributes; UINT32 NextSectionAttributes;
UINT32 SectionAttributes; UINT32 SectionAttributes;
UINT64 GcdAttributes; UINT64 GcdAttributes;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
UINTN NumberOfDescriptors; UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
DEBUG ((DEBUG_PAGE, "SyncCacheConfig()\n")); DEBUG ((DEBUG_PAGE, "SyncCacheConfig()\n"));
@ -243,10 +243,9 @@ SyncCacheConfig (
// Get the memory space map from GCD // Get the memory space map from GCD
// //
MemorySpaceMap = NULL; MemorySpaceMap = NULL;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
// to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
// GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
@ -261,15 +260,15 @@ SyncCacheConfig (
// iterate through each 1MB descriptor // iterate through each 1MB descriptor
NextRegionBase = NextRegionLength = 0; NextRegionBase = NextRegionLength = 0;
for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) { for (i = 0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) { if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
// extract attributes (cacheability and permissions) // extract attributes (cacheability and permissions)
SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK); SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
if (NextSectionAttributes == 0) { if (NextSectionAttributes == 0) {
// start on a new region // start on a new region
NextRegionLength = 0; NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = SectionAttributes; NextSectionAttributes = SectionAttributes;
} else if (SectionAttributes != NextSectionAttributes) { } else if (SectionAttributes != NextSectionAttributes) {
// Convert Section Attributes into GCD Attributes // Convert Section Attributes into GCD Attributes
@ -280,21 +279,27 @@ SyncCacheConfig (
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes); SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
// start on a new region // start on a new region
NextRegionLength = 0; NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = SectionAttributes; NextSectionAttributes = SectionAttributes;
} }
NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE; NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
} else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) { } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (FirstLevelTable[i])) {
// In this case any bits set in the 'NextSectionAttributes' are garbage and were set from // In this case any bits set in the 'NextSectionAttributes' are garbage and were set from
// bits that are actually part of the pagetable address. We clear it out to zero so that // bits that are actually part of the pagetable address. We clear it out to zero so that
// the SyncCacheConfigPage will use the page attributes instead of trying to convert the // the SyncCacheConfigPage will use the page attributes instead of trying to convert the
// section attributes into page attributes // section attributes into page attributes
NextSectionAttributes = 0; NextSectionAttributes = 0;
Status = SyncCacheConfigPage ( Status = SyncCacheConfigPage (
i,FirstLevelTable[i], i,
NumberOfDescriptors, MemorySpaceMap, FirstLevelTable[i],
&NextRegionBase,&NextRegionLength,&NextSectionAttributes); NumberOfDescriptors,
MemorySpaceMap,
&NextRegionBase,
&NextRegionLength,
&NextSectionAttributes
);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} else { } else {
// We do not support yet 16MB sections // We do not support yet 16MB sections
@ -309,10 +314,11 @@ SyncCacheConfig (
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes); SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
NextRegionLength = 0; NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = 0; NextSectionAttributes = 0;
} }
NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE; NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
} }
} // section entry loop } // section entry loop
@ -333,10 +339,10 @@ SyncCacheConfig (
UINT64 UINT64
EfiAttributeToArmAttribute ( EfiAttributeToArmAttribute (
IN UINT64 EfiAttributes IN UINT64 EfiAttributes
) )
{ {
UINT64 ArmAttributes; UINT64 ArmAttributes;
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {
case EFI_MEMORY_UC: case EFI_MEMORY_UC:
@ -382,15 +388,15 @@ EfiAttributeToArmAttribute (
EFI_STATUS EFI_STATUS
GetMemoryRegionPage ( GetMemoryRegionPage (
IN UINT32 *PageTable, IN UINT32 *PageTable,
IN OUT UINTN *BaseAddress, IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength, OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes OUT UINTN *RegionAttributes
) )
{ {
UINT32 PageAttributes; UINT32 PageAttributes;
UINT32 TableIndex; UINT32 TableIndex;
UINT32 PageDescriptor; UINT32 PageDescriptor;
// Convert the section attributes into page attributes // Convert the section attributes into page attributes
PageAttributes = ConvertSectionAttributesToPageAttributes (*RegionAttributes, 0); PageAttributes = ConvertSectionAttributesToPageAttributes (*RegionAttributes, 0);
@ -400,7 +406,7 @@ GetMemoryRegionPage (
ASSERT (TableIndex < TRANSLATION_TABLE_PAGE_COUNT); ASSERT (TableIndex < TRANSLATION_TABLE_PAGE_COUNT);
// Go through the page table to find the end of the section // Go through the page table to find the end of the section
for (; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) { for ( ; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) {
// Get the section at the given index // Get the section at the given index
PageDescriptor = PageTable[TableIndex]; PageDescriptor = PageTable[TableIndex];
@ -416,7 +422,7 @@ GetMemoryRegionPage (
} }
} else { } else {
// We do not support Large Page yet. We return EFI_SUCCESS that means end of the region. // We do not support Large Page yet. We return EFI_SUCCESS that means end of the region.
ASSERT(0); ASSERT (0);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
@ -426,9 +432,9 @@ GetMemoryRegionPage (
EFI_STATUS EFI_STATUS
GetMemoryRegion ( GetMemoryRegion (
IN OUT UINTN *BaseAddress, IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength, OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes OUT UINTN *RegionAttributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -436,8 +442,8 @@ GetMemoryRegion (
UINT32 PageAttributes; UINT32 PageAttributes;
UINT32 PageTableIndex; UINT32 PageTableIndex;
UINT32 SectionDescriptor; UINT32 SectionDescriptor;
ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
UINT32 *PageTable; UINT32 *PageTable;
// Initialize the arguments // Initialize the arguments
*RegionLength = 0; *RegionLength = 0;
@ -459,32 +465,32 @@ GetMemoryRegion (
if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) || if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||
((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))
{ {
*BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK; *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
*RegionAttributes = SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK; *RegionAttributes = SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK;
} else { } else {
// Otherwise, we round it to the page boundary // Otherwise, we round it to the page boundary
*BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK; *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK;
// Get the attribute at the page table level (Level 2) // Get the attribute at the page table level (Level 2)
PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); PageTable = (UINT32 *)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
// Calculate index into first level translation table for start of modification // Calculate index into first level translation table for start of modification
PageTableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; PageTableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK; PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK;
*RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes, 0) | *RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes, 0) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes); TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes);
} }
for (;TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) { for ( ; TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) {
// Get the section at the given index // Get the section at the given index
SectionDescriptor = FirstLevelTable[TableIndex]; SectionDescriptor = FirstLevelTable[TableIndex];
// If the entry is a level-2 page table then we scan it to find the end of the region // If the entry is a level-2 page table then we scan it to find the end of the region
if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (SectionDescriptor)) { if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (SectionDescriptor)) {
// Extract the page table location from the descriptor // Extract the page table location from the descriptor
PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); PageTable = (UINT32 *)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
// Scan the page table to find the end of the region. // Scan the page table to find the end of the region.
Status = GetMemoryRegionPage (PageTable, BaseAddress, RegionLength, RegionAttributes); Status = GetMemoryRegionPage (PageTable, BaseAddress, RegionLength, RegionAttributes);
@ -494,7 +500,8 @@ GetMemoryRegion (
break; break;
} }
} else if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) || } else if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||
((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) { ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))
{
if ((SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK) != *RegionAttributes) { if ((SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK) != *RegionAttributes) {
// If the attributes of the section differ from the one targeted then we exit the loop // If the attributes of the section differ from the one targeted then we exit the loop
break; break;

72
ArmPkg/Drivers/CpuDxe/CpuDxe.c
View File

@ -11,7 +11,7 @@
#include <Guid/IdleLoopEvent.h> #include <Guid/IdleLoopEvent.h>
BOOLEAN mIsFlushingGCD; BOOLEAN mIsFlushingGCD;
/** /**
This function flushes the range of addresses from Start to Start+Length This function flushes the range of addresses from Start to Start+Length
@ -43,13 +43,12 @@ BOOLEAN mIsFlushingGCD;
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuFlushCpuDataCache ( CpuFlushCpuDataCache (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS Start, IN EFI_PHYSICAL_ADDRESS Start,
IN UINT64 Length, IN UINT64 Length,
IN EFI_CPU_FLUSH_TYPE FlushType IN EFI_CPU_FLUSH_TYPE FlushType
) )
{ {
switch (FlushType) { switch (FlushType) {
case EfiCpuFlushTypeWriteBack: case EfiCpuFlushTypeWriteBack:
WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
@ -67,7 +66,6 @@ CpuFlushCpuDataCache (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
This function enables interrupt processing by the processor. This function enables interrupt processing by the processor.
@ -80,7 +78,7 @@ CpuFlushCpuDataCache (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuEnableInterrupt ( CpuEnableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This IN EFI_CPU_ARCH_PROTOCOL *This
) )
{ {
ArmEnableInterrupts (); ArmEnableInterrupts ();
@ -88,7 +86,6 @@ CpuEnableInterrupt (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
This function disables interrupt processing by the processor. This function disables interrupt processing by the processor.
@ -101,7 +98,7 @@ CpuEnableInterrupt (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuDisableInterrupt ( CpuDisableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This IN EFI_CPU_ARCH_PROTOCOL *This
) )
{ {
ArmDisableInterrupts (); ArmDisableInterrupts ();
@ -109,7 +106,6 @@ CpuDisableInterrupt (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
This function retrieves the processor's current interrupt state a returns it in This function retrieves the processor's current interrupt state a returns it in
State. If interrupts are currently enabled, then TRUE is returned. If interrupts State. If interrupts are currently enabled, then TRUE is returned. If interrupts
@ -126,19 +122,18 @@ CpuDisableInterrupt (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuGetInterruptState ( CpuGetInterruptState (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
OUT BOOLEAN *State OUT BOOLEAN *State
) )
{ {
if (State == NULL) { if (State == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
*State = ArmGetInterruptState(); *State = ArmGetInterruptState ();
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
This function generates an INIT on the processor. If this function succeeds, then the This function generates an INIT on the processor. If this function succeeds, then the
processor will be reset, and control will not be returned to the caller. If InitType is processor will be reset, and control will not be returned to the caller. If InitType is
@ -158,8 +153,8 @@ CpuGetInterruptState (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuInit ( CpuInit (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_CPU_INIT_TYPE InitType IN EFI_CPU_INIT_TYPE InitType
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@ -168,9 +163,9 @@ CpuInit (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuRegisterInterruptHandler ( CpuRegisterInterruptHandler (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
) )
{ {
return RegisterInterruptHandler (InterruptType, InterruptHandler); return RegisterInterruptHandler (InterruptType, InterruptHandler);
@ -179,10 +174,10 @@ CpuRegisterInterruptHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuGetTimerValue ( CpuGetTimerValue (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN UINT32 TimerIndex, IN UINT32 TimerIndex,
OUT UINT64 *TimerValue, OUT UINT64 *TimerValue,
OUT UINT64 *TimerPeriod OPTIONAL OUT UINT64 *TimerPeriod OPTIONAL
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@ -199,8 +194,8 @@ CpuGetTimerValue (
VOID VOID
EFIAPI EFIAPI
IdleLoopEventCallback ( IdleLoopEventCallback (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
CpuSleep (); CpuSleep ();
@ -209,8 +204,8 @@ IdleLoopEventCallback (
// //
// Globals used to initialize the protocol // Globals used to initialize the protocol
// //
EFI_HANDLE mCpuHandle = NULL; EFI_HANDLE mCpuHandle = NULL;
EFI_CPU_ARCH_PROTOCOL mCpu = { EFI_CPU_ARCH_PROTOCOL mCpu = {
CpuFlushCpuDataCache, CpuFlushCpuDataCache,
CpuEnableInterrupt, CpuEnableInterrupt,
CpuDisableInterrupt, CpuDisableInterrupt,
@ -226,7 +221,7 @@ EFI_CPU_ARCH_PROTOCOL mCpu = {
STATIC STATIC
VOID VOID
InitializeDma ( InitializeDma (
IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
) )
{ {
CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule (); CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();
@ -234,22 +229,23 @@ InitializeDma (
EFI_STATUS EFI_STATUS
CpuDxeInitialize ( CpuDxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_EVENT IdleLoopEvent; EFI_EVENT IdleLoopEvent;
InitializeExceptions (&mCpu); InitializeExceptions (&mCpu);
InitializeDma (&mCpu); InitializeDma (&mCpu);
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&mCpuHandle, &mCpuHandle,
&gEfiCpuArchProtocolGuid, &mCpu, &gEfiCpuArchProtocolGuid,
NULL &mCpu,
); NULL
);
// //
// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes () // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
@ -262,8 +258,8 @@ CpuDxeInitialize (
// If the platform is a MPCore system then install the Configuration Table describing the // If the platform is a MPCore system then install the Configuration Table describing the
// secondary core states // secondary core states
if (ArmIsMpCore()) { if (ArmIsMpCore ()) {
PublishArmProcessorTable(); PublishArmProcessorTable ();
} }
// //

44
ArmPkg/Drivers/CpuDxe/CpuDxe.h
View File

@ -31,7 +31,7 @@
#include <Protocol/DebugSupport.h> #include <Protocol/DebugSupport.h>
#include <Protocol/LoadedImage.h> #include <Protocol/LoadedImage.h>
extern BOOLEAN mIsFlushingGCD; extern BOOLEAN mIsFlushingGCD;
/** /**
This function registers and enables the handler specified by InterruptHandler for a processor This function registers and enables the handler specified by InterruptHandler for a processor
@ -55,11 +55,10 @@ extern BOOLEAN mIsFlushingGCD;
**/ **/
EFI_STATUS EFI_STATUS
RegisterInterruptHandler ( RegisterInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
); );
/** /**
This function registers and enables the handler specified by InterruptHandler for a processor This function registers and enables the handler specified by InterruptHandler for a processor
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
@ -82,28 +81,27 @@ RegisterInterruptHandler (
**/ **/
EFI_STATUS EFI_STATUS
RegisterDebuggerInterruptHandler ( RegisterDebuggerInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuSetMemoryAttributes ( CpuSetMemoryAttributes (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
); );
EFI_STATUS EFI_STATUS
InitializeExceptions ( InitializeExceptions (
IN EFI_CPU_ARCH_PROTOCOL *Cpu IN EFI_CPU_ARCH_PROTOCOL *Cpu
); );
EFI_STATUS EFI_STATUS
SyncCacheConfig ( SyncCacheConfig (
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
); );
/** /**
@ -117,30 +115,30 @@ SyncCacheConfig (
**/ **/
VOID VOID
EFIAPI EFIAPI
PublishArmProcessorTable( PublishArmProcessorTable (
VOID VOID
); );
// The ARM Attributes might be defined on 64-bit (case of the long format description table) // The ARM Attributes might be defined on 64-bit (case of the long format description table)
UINT64 UINT64
EfiAttributeToArmAttribute ( EfiAttributeToArmAttribute (
IN UINT64 EfiAttributes IN UINT64 EfiAttributes
); );
EFI_STATUS EFI_STATUS
GetMemoryRegion ( GetMemoryRegion (
IN OUT UINTN *BaseAddress, IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength, OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes OUT UINTN *RegionAttributes
); );
EFI_STATUS EFI_STATUS
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors, IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
); );
#endif // CPU_DXE_H_ #endif // CPU_DXE_H_

63
ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
View File

@ -29,33 +29,36 @@
**/ **/
EFI_STATUS EFI_STATUS
SearchGcdMemorySpaces ( SearchGcdMemorySpaces (
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors, IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
OUT UINTN *StartIndex, OUT UINTN *StartIndex,
OUT UINTN *EndIndex OUT UINTN *EndIndex
) )
{ {
UINTN Index; UINTN Index;
*StartIndex = 0; *StartIndex = 0;
*EndIndex = 0; *EndIndex = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) { for (Index = 0; Index < NumberOfDescriptors; Index++) {
if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) && if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&
(BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) { (BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)))
{
*StartIndex = Index; *StartIndex = Index;
} }
if (((BaseAddress + Length - 1) >= MemorySpaceMap[Index].BaseAddress) && if (((BaseAddress + Length - 1) >= MemorySpaceMap[Index].BaseAddress) &&
((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) { ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)))
{
*EndIndex = Index; *EndIndex = Index;
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
/** /**
Sets the attributes for a specified range in Gcd Memory Space Map. Sets the attributes for a specified range in Gcd Memory Space Map.
@ -74,11 +77,11 @@ SearchGcdMemorySpaces (
**/ **/
EFI_STATUS EFI_STATUS
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors, IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -88,14 +91,21 @@ SetGcdMemorySpaceAttributes (
EFI_PHYSICAL_ADDRESS RegionStart; EFI_PHYSICAL_ADDRESS RegionStart;
UINT64 RegionLength; UINT64 RegionLength;
DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n", DEBUG ((
BaseAddress, BaseAddress + Length, Attributes)); DEBUG_GCD,
"SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",
BaseAddress,
BaseAddress + Length,
Attributes
));
// We do not support a smaller granularity than 4KB on ARM Architecture // We do not support a smaller granularity than 4KB on ARM Architecture
if ((Length & EFI_PAGE_MASK) != 0) { if ((Length & EFI_PAGE_MASK) != 0) {
DEBUG ((DEBUG_WARN, DEBUG ((
"Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n", DEBUG_WARN,
Length)); "Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",
Length
));
} }
// //
@ -120,6 +130,7 @@ SetGcdMemorySpaceAttributes (
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue; continue;
} }
// //
// Calculate the start and end address of the overlapping range // Calculate the start and end address of the overlapping range
// //
@ -128,11 +139,13 @@ SetGcdMemorySpaceAttributes (
} else { } else {
RegionStart = MemorySpaceMap[Index].BaseAddress; RegionStart = MemorySpaceMap[Index].BaseAddress;
} }
if ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) { if ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) {
RegionLength = BaseAddress + Length - RegionStart; RegionLength = BaseAddress + Length - RegionStart;
} else { } else {
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart; RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
} }
// //
// Set memory attributes according to MTRR attribute and the original attribute of descriptor // Set memory attributes according to MTRR attribute and the original attribute of descriptor
// //
@ -170,10 +183,10 @@ SetGcdMemorySpaceAttributes (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuSetMemoryAttributes ( CpuSetMemoryAttributes (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 EfiAttributes IN UINT64 EfiAttributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -197,7 +210,7 @@ CpuSetMemoryAttributes (
// Get the region starting from 'BaseAddress' and its 'Attribute' // Get the region starting from 'BaseAddress' and its 'Attribute'
RegionBaseAddress = BaseAddress; RegionBaseAddress = BaseAddress;
Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes); Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes);
// Data & Instruction Caches are flushed when we set new memory attributes. // Data & Instruction Caches are flushed when we set new memory attributes.
// So, we only set the attributes if the new region is different. // So, we only set the attributes if the new region is different.

35
ArmPkg/Drivers/CpuDxe/CpuMpCore.c
View File

@ -14,7 +14,7 @@
#include <Guid/ArmMpCoreInfo.h> #include <Guid/ArmMpCoreInfo.h>
ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = { ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
{ {
EFI_ARM_PROCESSOR_TABLE_SIGNATURE, EFI_ARM_PROCESSOR_TABLE_SIGNATURE,
0, 0,
@ -26,7 +26,7 @@ ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION, EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION,
{ 0 }, { 0 },
0 0
}, //ARM Processor table header }, // ARM Processor table header
0, // Number of entries in ARM processor Table 0, // Number of entries in ARM processor Table
NULL // ARM Processor Table NULL // ARM Processor Table
}; };
@ -45,47 +45,48 @@ PublishArmProcessorTable (
VOID VOID
) )
{ {
EFI_PEI_HOB_POINTERS Hob; EFI_PEI_HOB_POINTERS Hob;
Hob.Raw = GetHobList (); Hob.Raw = GetHobList ();
// Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB // Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB
for (; !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) { for ( ; !END_OF_HOB_LIST (Hob); Hob.Raw = GET_NEXT_HOB (Hob)) {
// Check for Correct HOB type // Check for Correct HOB type
if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) { if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {
// Check for correct GUID type // Check for correct GUID type
if (CompareGuid(&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) { if (CompareGuid (&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {
ARM_PROCESSOR_TABLE *ArmProcessorTable; ARM_PROCESSOR_TABLE *ArmProcessorTable;
EFI_STATUS Status; EFI_STATUS Status;
// Allocate Runtime memory for ARM processor table // Allocate Runtime memory for ARM processor table
ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE)); ArmProcessorTable = (ARM_PROCESSOR_TABLE *)AllocateRuntimePool (sizeof (ARM_PROCESSOR_TABLE));
// Check if the memory allocation is successful or not // Check if the memory allocation is successful or not
ASSERT(NULL != ArmProcessorTable); ASSERT (NULL != ArmProcessorTable);
// Set ARM processor table to default values // Set ARM processor table to default values
CopyMem(ArmProcessorTable,&mArmProcessorTableTemplate,sizeof(ARM_PROCESSOR_TABLE)); CopyMem (ArmProcessorTable, &mArmProcessorTableTemplate, sizeof (ARM_PROCESSOR_TABLE));
// Fill in Length fields of ARM processor table // Fill in Length fields of ARM processor table
ArmProcessorTable->Header.Length = sizeof(ARM_PROCESSOR_TABLE); ArmProcessorTable->Header.Length = sizeof (ARM_PROCESSOR_TABLE);
ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE(Hob); ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE (Hob);
// Fill in Identifier(ARM processor table GUID) // Fill in Identifier(ARM processor table GUID)
ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid; ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid;
// Set Number of ARM core entries in the Table // Set Number of ARM core entries in the Table
ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO); ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE (Hob)/sizeof (ARM_CORE_INFO);
// Allocate runtime memory for ARM processor Table entries // Allocate runtime memory for ARM processor Table entries
ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool ( ArmProcessorTable->ArmCpus = (ARM_CORE_INFO *)AllocateRuntimePool (
ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO)); ArmProcessorTable->NumberOfEntries * sizeof (ARM_CORE_INFO)
);
// Check if the memory allocation is successful or not // Check if the memory allocation is successful or not
ASSERT(NULL != ArmProcessorTable->ArmCpus); ASSERT (NULL != ArmProcessorTable->ArmCpus);
// Copy ARM Processor Table data from HOB list to newly allocated memory // Copy ARM Processor Table data from HOB list to newly allocated memory
CopyMem(ArmProcessorTable->ArmCpus,GET_GUID_HOB_DATA(Hob), ArmProcessorTable->Header.DataLen); CopyMem (ArmProcessorTable->ArmCpus, GET_GUID_HOB_DATA (Hob), ArmProcessorTable->Header.DataLen);
// Install the ARM Processor table into EFI system configuration table // Install the ARM Processor table into EFI system configuration table
Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable); Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable);

28
ArmPkg/Drivers/CpuDxe/Exception.c
View File

@ -13,23 +13,23 @@
EFI_STATUS EFI_STATUS
InitializeExceptions ( InitializeExceptions (
IN EFI_CPU_ARCH_PROTOCOL *Cpu IN EFI_CPU_ARCH_PROTOCOL *Cpu
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_VECTOR_HANDOFF_INFO *VectorInfoList; EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
EFI_VECTOR_HANDOFF_INFO *VectorInfo; EFI_VECTOR_HANDOFF_INFO *VectorInfo;
BOOLEAN IrqEnabled; BOOLEAN IrqEnabled;
BOOLEAN FiqEnabled; BOOLEAN FiqEnabled;
VectorInfo = (EFI_VECTOR_HANDOFF_INFO *)NULL; VectorInfo = (EFI_VECTOR_HANDOFF_INFO *)NULL;
Status = EfiGetSystemConfigurationTable(&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList); Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
if (Status == EFI_SUCCESS && VectorInfoList != NULL) { if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {
VectorInfo = VectorInfoList; VectorInfo = VectorInfoList;
} }
// initialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core // initialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core
InitializeCpuExceptionHandlers(VectorInfo); InitializeCpuExceptionHandlers (VectorInfo);
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@ -64,7 +64,7 @@ InitializeExceptions (
// //
DEBUG_CODE ( DEBUG_CODE (
ArmEnableAsynchronousAbort (); ArmEnableAsynchronousAbort ();
); );
return Status; return Status;
} }
@ -90,11 +90,11 @@ previously installed.
**/ **/
EFI_STATUS EFI_STATUS
RegisterInterruptHandler( RegisterInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
) )
{ {
// pass down to CpuExceptionHandlerLib // pass down to CpuExceptionHandlerLib
return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler); return (EFI_STATUS)RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
} }

18
ArmPkg/Drivers/CpuPei/CpuPei.c
View File

@ -16,8 +16,6 @@ Abstract:
**/ **/
// //
// The package level header files this module uses // The package level header files this module uses
// //
@ -58,10 +56,10 @@ InitializeCpuPeim (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi; ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN ArmCoreCount; UINTN ArmCoreCount;
ARM_CORE_INFO *ArmCoreInfoTable; ARM_CORE_INFO *ArmCoreInfoTable;
// Enable program flow prediction, if supported. // Enable program flow prediction, if supported.
ArmEnableBranchPrediction (); ArmEnableBranchPrediction ();
@ -70,12 +68,12 @@ InitializeCpuPeim (
BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize)); BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
// Only MP Core platform need to produce gArmMpCoreInfoPpiGuid // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi); Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID **)&ArmMpCoreInfoPpi);
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
// Build the MP Core Info Table // Build the MP Core Info Table
ArmCoreCount = 0; ArmCoreCount = 0;
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable); Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) { if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {
// Build MPCore Info HOB // Build MPCore Info HOB
BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount); BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
} }

17
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
View File

@ -5,20 +5,21 @@
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
* *
**/ **/
#ifndef GENERIC_WATCHDOG_H_ #ifndef GENERIC_WATCHDOG_H_
#define GENERIC_WATCHDOG_H_ #define GENERIC_WATCHDOG_H_
// Refresh Frame: // Refresh Frame:
#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000) #define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
// Control Frame: // Control Frame:
#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000) #define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)
#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008) #define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)
#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010) #define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014) #define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)
// Values of bit 0 of the Control/Status Register // Values of bit 0 of the Control/Status Register
#define GENERIC_WDOG_ENABLED 1 #define GENERIC_WDOG_ENABLED 1
#define GENERIC_WDOG_DISABLED 0 #define GENERIC_WDOG_DISABLED 0
#endif // GENERIC_WATCHDOG_H_ #endif // GENERIC_WATCHDOG_H_

100
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
View File

@ -25,18 +25,18 @@
/* The number of 100ns periods (the unit of time passed to these functions) /* The number of 100ns periods (the unit of time passed to these functions)
in a second */ in a second */
#define TIME_UNITS_PER_SECOND 10000000 #define TIME_UNITS_PER_SECOND 10000000
// Tick frequency of the generic timer basis of the generic watchdog. // Tick frequency of the generic timer basis of the generic watchdog.
STATIC UINTN mTimerFrequencyHz = 0; STATIC UINTN mTimerFrequencyHz = 0;
/* In cases where the compare register was set manually, information about /* In cases where the compare register was set manually, information about
how long the watchdog was asked to wait cannot be retrieved from hardware. how long the watchdog was asked to wait cannot be retrieved from hardware.
It is therefore stored here. 0 means the timer is not running. */ It is therefore stored here. 0 means the timer is not running. */
STATIC UINT64 mNumTimerTicks = 0; STATIC UINT64 mNumTimerTicks = 0;
STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify; STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
STATIC STATIC
VOID VOID
@ -97,12 +97,12 @@ STATIC
VOID VOID
EFIAPI EFIAPI
WatchdogInterruptHandler ( WatchdogInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
STATIC CONST CHAR16 ResetString[]= L"The generic watchdog timer ran out."; STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";
UINT64 TimerPeriod; UINT64 TimerPeriod;
WatchdogDisable (); WatchdogDisable ();
@ -119,8 +119,12 @@ WatchdogInterruptHandler (
mWatchdogNotify (TimerPeriod + 1); mWatchdogNotify (TimerPeriod + 1);
} }
gRT->ResetSystem (EfiResetCold, EFI_TIMEOUT, StrSize (ResetString), gRT->ResetSystem (
(CHAR16 *)ResetString); EfiResetCold,
EFI_TIMEOUT,
StrSize (ResetString),
(CHAR16 *)ResetString
);
// If we got here then the reset didn't work // If we got here then the reset didn't work
ASSERT (FALSE); ASSERT (FALSE);
@ -154,15 +158,15 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
WatchdogRegisterHandler ( WatchdogRegisterHandler (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
) )
{ {
if (mWatchdogNotify == NULL && NotifyFunction == NULL) { if ((mWatchdogNotify == NULL) && (NotifyFunction == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (mWatchdogNotify != NULL && NotifyFunction != NULL) { if ((mWatchdogNotify != NULL) && (NotifyFunction != NULL)) {
return EFI_ALREADY_STARTED; return EFI_ALREADY_STARTED;
} }
@ -188,11 +192,11 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
WatchdogSetTimerPeriod ( WatchdogSetTimerPeriod (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod // In 100ns units IN UINT64 TimerPeriod // In 100ns units
) )
{ {
UINTN SystemCount; UINTN SystemCount;
// if TimerPeriod is 0, this is a request to stop the watchdog. // if TimerPeriod is 0, this is a request to stop the watchdog.
if (TimerPeriod == 0) { if (TimerPeriod == 0) {
@ -244,8 +248,8 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
WatchdogGetTimerPeriod ( WatchdogGetTimerPeriod (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod OUT UINT64 *TimerPeriod
) )
{ {
if (TimerPeriod == NULL) { if (TimerPeriod == NULL) {
@ -289,26 +293,29 @@ WatchdogGetTimerPeriod (
Retrieves the period of the timer interrupt in 100ns units. Retrieves the period of the timer interrupt in 100ns units.
**/ **/
STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = { STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
WatchdogRegisterHandler, WatchdogRegisterHandler,
WatchdogSetTimerPeriod, WatchdogSetTimerPeriod,
WatchdogGetTimerPeriod WatchdogGetTimerPeriod
}; };
STATIC EFI_EVENT mEfiExitBootServicesEvent; STATIC EFI_EVENT mEfiExitBootServicesEvent;
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GenericWatchdogEntry ( GenericWatchdogEntry (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_HANDLE Handle; EFI_HANDLE Handle;
Status = gBS->LocateProtocol (&gHardwareInterrupt2ProtocolGuid, NULL, Status = gBS->LocateProtocol (
(VOID **)&mInterruptProtocol); &gHardwareInterrupt2ProtocolGuid,
NULL,
(VOID **)&mInterruptProtocol
);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
/* Make sure the Watchdog Timer Architectural Protocol has not been installed /* Make sure the Watchdog Timer Architectural Protocol has not been installed
@ -320,33 +327,44 @@ GenericWatchdogEntry (
ASSERT (mTimerFrequencyHz != 0); ASSERT (mTimerFrequencyHz != 0);
// Install interrupt handler // Install interrupt handler
Status = mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol, Status = mInterruptProtocol->RegisterInterruptSource (
mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
WatchdogInterruptHandler); WatchdogInterruptHandler
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
Status = mInterruptProtocol->SetTriggerType (mInterruptProtocol, Status = mInterruptProtocol->SetTriggerType (
mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING); EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
goto UnregisterHandler; goto UnregisterHandler;
} }
// Install the Timer Architectural Protocol onto a new handle // Install the Timer Architectural Protocol onto a new handle
Handle = NULL; Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces (&Handle, Status = gBS->InstallMultipleProtocolInterfaces (
&gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer, &Handle,
NULL); &gEfiWatchdogTimerArchProtocolGuid,
&mWatchdogTimer,
NULL
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
goto UnregisterHandler; goto UnregisterHandler;
} }
// Register for an ExitBootServicesEvent // Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, Status = gBS->CreateEvent (
WatchdogExitBootServicesEvent, NULL, EVT_SIGNAL_EXIT_BOOT_SERVICES,
&mEfiExitBootServicesEvent); TPL_NOTIFY,
WatchdogExitBootServicesEvent,
NULL,
&mEfiExitBootServicesEvent
);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
mNumTimerTicks = 0; mNumTimerTicks = 0;
@ -356,8 +374,10 @@ GenericWatchdogEntry (
UnregisterHandler: UnregisterHandler:
// Unregister the handler // Unregister the handler
mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol, mInterruptProtocol->RegisterInterruptSource (
mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
NULL); NULL
);
return Status; return Status;
} }

14
ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h
View File

@ -9,14 +9,14 @@
#ifndef MM_COMMUNICATE_H_ #ifndef MM_COMMUNICATE_H_
#define MM_COMMUNICATE_H_ #define MM_COMMUNICATE_H_
#define MM_MAJOR_VER_MASK 0xEFFF0000 #define MM_MAJOR_VER_MASK 0xEFFF0000
#define MM_MINOR_VER_MASK 0x0000FFFF #define MM_MINOR_VER_MASK 0x0000FFFF
#define MM_MAJOR_VER_SHIFT 16 #define MM_MAJOR_VER_SHIFT 16
#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT) #define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT)
#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK) #define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK)
#define MM_CALLER_MAJOR_VER 0x1UL #define MM_CALLER_MAJOR_VER 0x1UL
#define MM_CALLER_MINOR_VER 0x0 #define MM_CALLER_MINOR_VER 0x0
#endif /* MM_COMMUNICATE_H_ */ #endif /* MM_COMMUNICATE_H_ */

186
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
View File

@ -63,18 +63,18 @@ STATIC EFI_HANDLE mMmCommunicateHandle;
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MmCommunication2Communicate ( MmCommunication2Communicate (
IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This, IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,
IN OUT VOID *CommBufferPhysical, IN OUT VOID *CommBufferPhysical,
IN OUT VOID *CommBufferVirtual, IN OUT VOID *CommBufferVirtual,
IN OUT UINTN *CommSize OPTIONAL IN OUT UINTN *CommSize OPTIONAL
) )
{ {
EFI_MM_COMMUNICATE_HEADER *CommunicateHeader; EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;
ARM_SMC_ARGS CommunicateSmcArgs; ARM_SMC_ARGS CommunicateSmcArgs;
EFI_STATUS Status; EFI_STATUS Status;
UINTN BufferSize; UINTN BufferSize;
Status = EFI_ACCESS_DENIED; Status = EFI_ACCESS_DENIED;
BufferSize = 0; BufferSize = 0;
ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS)); ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS));
@ -100,15 +100,17 @@ MmCommunication2Communicate (
// This case can be used by the consumer of this driver to find out the // This case can be used by the consumer of this driver to find out the
// max size that can be used for allocating CommBuffer. // max size that can be used for allocating CommBuffer.
if ((*CommSize == 0) || if ((*CommSize == 0) ||
(*CommSize > mNsCommBuffMemRegion.Length)) { (*CommSize > mNsCommBuffMemRegion.Length))
{
*CommSize = mNsCommBuffMemRegion.Length; *CommSize = mNsCommBuffMemRegion.Length;
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
// //
// CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER); // CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER);
// //
if (*CommSize != BufferSize) { if (*CommSize != BufferSize) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
} }
@ -117,7 +119,8 @@ MmCommunication2Communicate (
// environment then return the expected size. // environment then return the expected size.
// //
if ((BufferSize == 0) || if ((BufferSize == 0) ||
(BufferSize > mNsCommBuffMemRegion.Length)) { (BufferSize > mNsCommBuffMemRegion.Length))
{
CommunicateHeader->MessageLength = mNsCommBuffMemRegion.Length - CommunicateHeader->MessageLength = mNsCommBuffMemRegion.Length -
sizeof (CommunicateHeader->HeaderGuid) - sizeof (CommunicateHeader->HeaderGuid) -
sizeof (CommunicateHeader->MessageLength); sizeof (CommunicateHeader->MessageLength);
@ -143,41 +146,41 @@ MmCommunication2Communicate (
ArmCallSmc (&CommunicateSmcArgs); ArmCallSmc (&CommunicateSmcArgs);
switch (CommunicateSmcArgs.Arg0) { switch (CommunicateSmcArgs.Arg0) {
case ARM_SMC_MM_RET_SUCCESS: case ARM_SMC_MM_RET_SUCCESS:
ZeroMem (CommBufferVirtual, BufferSize); ZeroMem (CommBufferVirtual, BufferSize);
// On successful return, the size of data being returned is inferred from // On successful return, the size of data being returned is inferred from
// MessageLength + Header. // MessageLength + Header.
CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase; CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
BufferSize = CommunicateHeader->MessageLength + BufferSize = CommunicateHeader->MessageLength +
sizeof (CommunicateHeader->HeaderGuid) + sizeof (CommunicateHeader->HeaderGuid) +
sizeof (CommunicateHeader->MessageLength); sizeof (CommunicateHeader->MessageLength);
CopyMem ( CopyMem (
CommBufferVirtual, CommBufferVirtual,
(VOID *)mNsCommBuffMemRegion.VirtualBase, (VOID *)mNsCommBuffMemRegion.VirtualBase,
BufferSize BufferSize
); );
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
break; break;
case ARM_SMC_MM_RET_INVALID_PARAMS: case ARM_SMC_MM_RET_INVALID_PARAMS:
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
break; break;
case ARM_SMC_MM_RET_DENIED: case ARM_SMC_MM_RET_DENIED:
Status = EFI_ACCESS_DENIED; Status = EFI_ACCESS_DENIED;
break; break;
case ARM_SMC_MM_RET_NO_MEMORY: case ARM_SMC_MM_RET_NO_MEMORY:
// Unexpected error since the CommSize was checked for zero length // Unexpected error since the CommSize was checked for zero length
// prior to issuing the SMC // prior to issuing the SMC
Status = EFI_OUT_OF_RESOURCES; Status = EFI_OUT_OF_RESOURCES;
ASSERT (0); ASSERT (0);
break; break;
default: default:
Status = EFI_ACCESS_DENIED; Status = EFI_ACCESS_DENIED;
ASSERT (0); ASSERT (0);
} }
return Status; return Status;
@ -209,7 +212,7 @@ VOID
EFIAPI EFIAPI
NotifySetVirtualAddressMap ( NotifySetVirtualAddressMap (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -219,19 +222,23 @@ NotifySetVirtualAddressMap (
(VOID **)&mNsCommBuffMemRegion.VirtualBase (VOID **)&mNsCommBuffMemRegion.VirtualBase
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "NotifySetVirtualAddressMap():" DEBUG ((
" Unable to convert MM runtime pointer. Status:0x%r\n", Status)); DEBUG_ERROR,
"NotifySetVirtualAddressMap():"
" Unable to convert MM runtime pointer. Status:0x%r\n",
Status
));
} }
} }
STATIC STATIC
EFI_STATUS EFI_STATUS
GetMmCompatibility () GetMmCompatibility (
)
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 MmVersion; UINT32 MmVersion;
ARM_SMC_ARGS MmVersionArgs; ARM_SMC_ARGS MmVersionArgs;
// MM_VERSION uses SMC32 calling conventions // MM_VERSION uses SMC32 calling conventions
MmVersionArgs.Arg0 = ARM_SMC_ID_MM_VERSION_AARCH32; MmVersionArgs.Arg0 = ARM_SMC_ID_MM_VERSION_AARCH32;
@ -240,27 +247,38 @@ GetMmCompatibility ()
MmVersion = MmVersionArgs.Arg0; MmVersion = MmVersionArgs.Arg0;
if ((MM_MAJOR_VER(MmVersion) == MM_CALLER_MAJOR_VER) && if ((MM_MAJOR_VER (MmVersion) == MM_CALLER_MAJOR_VER) &&
(MM_MINOR_VER(MmVersion) >= MM_CALLER_MINOR_VER)) { (MM_MINOR_VER (MmVersion) >= MM_CALLER_MINOR_VER))
DEBUG ((DEBUG_INFO, "MM Version: Major=0x%x, Minor=0x%x\n", {
MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion))); DEBUG ((
DEBUG_INFO,
"MM Version: Major=0x%x, Minor=0x%x\n",
MM_MAJOR_VER (MmVersion),
MM_MINOR_VER (MmVersion)
));
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
} else { } else {
DEBUG ((DEBUG_ERROR, "Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n", DEBUG ((
MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion), MM_CALLER_MAJOR_VER, MM_CALLER_MINOR_VER)); DEBUG_ERROR,
"Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",
MM_MAJOR_VER (MmVersion),
MM_MINOR_VER (MmVersion),
MM_CALLER_MAJOR_VER,
MM_CALLER_MINOR_VER
));
Status = EFI_UNSUPPORTED; Status = EFI_UNSUPPORTED;
} }
return Status; return Status;
} }
STATIC EFI_GUID* CONST mGuidedEventGuid[] = { STATIC EFI_GUID *CONST mGuidedEventGuid[] = {
&gEfiEndOfDxeEventGroupGuid, &gEfiEndOfDxeEventGroupGuid,
&gEfiEventExitBootServicesGuid, &gEfiEventExitBootServicesGuid,
&gEfiEventReadyToBootGuid, &gEfiEventReadyToBootGuid,
}; };
STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)]; STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)];
/** /**
Event notification that is fired when GUIDed Event Group is signaled. Event notification that is fired when GUIDed Event Group is signaled.
@ -277,15 +295,15 @@ MmGuidedEventNotify (
IN VOID *Context IN VOID *Context
) )
{ {
EFI_MM_COMMUNICATE_HEADER Header; EFI_MM_COMMUNICATE_HEADER Header;
UINTN Size; UINTN Size;
// //
// Use Guid to initialize EFI_SMM_COMMUNICATE_HEADER structure // Use Guid to initialize EFI_SMM_COMMUNICATE_HEADER structure
// //
CopyGuid (&Header.HeaderGuid, Context); CopyGuid (&Header.HeaderGuid, Context);
Header.MessageLength = 1; Header.MessageLength = 1;
Header.Data[0] = 0; Header.Data[0] = 0;
Size = sizeof (Header); Size = sizeof (Header);
MmCommunication2Communicate (&mMmCommunication2, &Header, &Header, &Size); MmCommunication2Communicate (&mMmCommunication2, &Header, &Header, &Size);
@ -308,23 +326,23 @@ MmGuidedEventNotify (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MmCommunication2Initialize ( MmCommunication2Initialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
// Check if we can make the MM call // Check if we can make the MM call
Status = GetMmCompatibility (); Status = GetMmCompatibility ();
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
goto ReturnErrorStatus; goto ReturnErrorStatus;
} }
mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase); mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase);
// During boot , Virtual and Physical are same // During boot , Virtual and Physical are same
mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase; mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase;
mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize); mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);
ASSERT (mNsCommBuffMemRegion.PhysicalBase != 0); ASSERT (mNsCommBuffMemRegion.PhysicalBase != 0);
@ -339,8 +357,11 @@ MmCommunication2Initialize (
EFI_MEMORY_RUNTIME EFI_MEMORY_RUNTIME
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: " DEBUG ((
"Failed to add MM-NS Buffer Memory Space\n")); DEBUG_ERROR,
"MmCommunicateInitialize: "
"Failed to add MM-NS Buffer Memory Space\n"
));
goto ReturnErrorStatus; goto ReturnErrorStatus;
} }
@ -350,8 +371,11 @@ MmCommunication2Initialize (
EFI_MEMORY_WB | EFI_MEMORY_XP | EFI_MEMORY_RUNTIME EFI_MEMORY_WB | EFI_MEMORY_XP | EFI_MEMORY_RUNTIME
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: " DEBUG ((
"Failed to set MM-NS Buffer Memory attributes\n")); DEBUG_ERROR,
"MmCommunicateInitialize: "
"Failed to set MM-NS Buffer Memory attributes\n"
));
goto CleanAddedMemorySpace; goto CleanAddedMemorySpace;
} }
@ -362,9 +386,12 @@ MmCommunication2Initialize (
EFI_NATIVE_INTERFACE, EFI_NATIVE_INTERFACE,
&mMmCommunication2 &mMmCommunication2
); );
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "MmCommunicationInitialize: " DEBUG ((
"Failed to install MM communication protocol\n")); DEBUG_ERROR,
"MmCommunicationInitialize: "
"Failed to install MM communication protocol\n"
));
goto CleanAddedMemorySpace; goto CleanAddedMemorySpace;
} }
@ -381,17 +408,24 @@ MmCommunication2Initialize (
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
for (Index = 0; Index < ARRAY_SIZE (mGuidedEventGuid); Index++) { for (Index = 0; Index < ARRAY_SIZE (mGuidedEventGuid); Index++) {
Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_CALLBACK, Status = gBS->CreateEventEx (
MmGuidedEventNotify, mGuidedEventGuid[Index], EVT_NOTIFY_SIGNAL,
mGuidedEventGuid[Index], &mGuidedEvent[Index]); TPL_CALLBACK,
MmGuidedEventNotify,
mGuidedEventGuid[Index],
mGuidedEventGuid[Index],
&mGuidedEvent[Index]
);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
while (Index-- > 0) { while (Index-- > 0) {
gBS->CloseEvent (mGuidedEvent[Index]); gBS->CloseEvent (mGuidedEvent[Index]);
} }
goto UninstallProtocol; goto UninstallProtocol;
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
UninstallProtocol: UninstallProtocol:

56
ArmPkg/Drivers/TimerDxe/TimerDxe.c
View File

@ -7,7 +7,6 @@
**/ **/
#include <PiDxe.h> #include <PiDxe.h>
#include <Library/ArmLib.h> #include <Library/ArmLib.h>
@ -24,18 +23,18 @@
#include <Protocol/HardwareInterrupt.h> #include <Protocol/HardwareInterrupt.h>
// The notification function to call on every timer interrupt. // The notification function to call on every timer interrupt.
EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL; EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// The current period of the timer interrupt // The current period of the timer interrupt
UINT64 mTimerPeriod = 0; UINT64 mTimerPeriod = 0;
// The latest Timer Tick calculated for mTimerPeriod // The latest Timer Tick calculated for mTimerPeriod
UINT64 mTimerTicks = 0; UINT64 mTimerTicks = 0;
// Number of elapsed period since the last Timer interrupt // Number of elapsed period since the last Timer interrupt
UINT64 mElapsedPeriod = 1; UINT64 mElapsedPeriod = 1;
// Cached copy of the Hardware Interrupt protocol instance // Cached copy of the Hardware Interrupt protocol instance
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL; EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
/** /**
This function registers the handler NotifyFunction so it is called every time This function registers the handler NotifyFunction so it is called every time
@ -133,9 +132,9 @@ TimerDriverSetTimerPeriod (
IN UINT64 TimerPeriod IN UINT64 TimerPeriod
) )
{ {
UINT64 CounterValue; UINT64 CounterValue;
UINT64 TimerTicks; UINT64 TimerTicks;
EFI_TPL OriginalTPL; EFI_TPL OriginalTPL;
// Always disable the timer // Always disable the timer
ArmGenericTimerDisableTimer (); ArmGenericTimerDisableTimer ();
@ -166,7 +165,7 @@ TimerDriverSetTimerPeriod (
ArmGenericTimerEnableTimer (); ArmGenericTimerEnableTimer ();
} else { } else {
// Save the new timer period // Save the new timer period
mTimerPeriod = TimerPeriod; mTimerPeriod = TimerPeriod;
// Reset the elapsed period // Reset the elapsed period
mElapsedPeriod = 1; mElapsedPeriod = 1;
} }
@ -192,8 +191,8 @@ TimerDriverSetTimerPeriod (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
TimerDriverGetTimerPeriod ( TimerDriverGetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This, IN EFI_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod OUT UINT64 *TimerPeriod
) )
{ {
if (TimerPeriod == NULL) { if (TimerPeriod == NULL) {
@ -262,7 +261,7 @@ TimerDriverGenerateSoftInterrupt (
a period of time. a period of time.
**/ **/
EFI_TIMER_ARCH_PROTOCOL gTimer = { EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler, TimerDriverRegisterHandler,
TimerDriverSetTimerPeriod, TimerDriverSetTimerPeriod,
TimerDriverGetTimerPeriod, TimerDriverGetTimerPeriod,
@ -285,13 +284,13 @@ EFI_TIMER_ARCH_PROTOCOL gTimer = {
VOID VOID
EFIAPI EFIAPI
TimerInterruptHandler ( TimerInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source, IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
EFI_TPL OriginalTPL; EFI_TPL OriginalTPL;
UINT64 CurrentValue; UINT64 CurrentValue;
UINT64 CompareValue; UINT64 CompareValue;
// //
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
@ -305,8 +304,7 @@ TimerInterruptHandler (
gInterrupt->EndOfInterrupt (gInterrupt, Source); gInterrupt->EndOfInterrupt (gInterrupt, Source);
// Check if the timer interrupt is active // Check if the timer interrupt is active
if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) { if ((ArmGenericTimerGetTimerCtrlReg ()) & ARM_ARCH_TIMER_ISTATUS) {
if (mTimerNotifyFunction != 0) { if (mTimerNotifyFunction != 0) {
mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod); mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);
} }
@ -338,7 +336,6 @@ TimerInterruptHandler (
gBS->RestoreTPL (OriginalTPL); gBS->RestoreTPL (OriginalTPL);
} }
/** /**
Initialize the state information for the Timer Architectural Protocol and Initialize the state information for the Timer Architectural Protocol and
the Timer Debug support protocol that allows the debugger to break into a the Timer Debug support protocol that allows the debugger to break into a
@ -355,8 +352,8 @@ TimerInterruptHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
TimerInitialize ( TimerInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_HANDLE Handle; EFI_HANDLE Handle;
@ -374,7 +371,7 @@ TimerInitialize (
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Disable the timer // Disable the timer
TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg (); TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg ();
TimerCtrlReg |= ARM_ARCH_TIMER_IMASK; TimerCtrlReg |= ARM_ARCH_TIMER_IMASK;
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE; TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg); ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg);
@ -405,17 +402,18 @@ TimerInitialize (
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Set up default timer // Set up default timer
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32 (PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
Handle = NULL; Handle = NULL;
// Install the Timer Architectural Protocol onto a new handle // Install the Timer Architectural Protocol onto a new handle
Status = gBS->InstallMultipleProtocolInterfaces( Status = gBS->InstallMultipleProtocolInterfaces (
&Handle, &Handle,
&gEfiTimerArchProtocolGuid, &gTimer, &gEfiTimerArchProtocolGuid,
&gTimer,
NULL NULL
); );
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR (Status);
// Everything is ready, unmask and enable timer interrupts // Everything is ready, unmask and enable timer interrupts
TimerCtrlReg = ARM_ARCH_TIMER_ENABLE; TimerCtrlReg = ARM_ARCH_TIMER_ENABLE;

207
ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c
View File

@ -27,16 +27,16 @@
#include "SemihostFs.h" #include "SemihostFs.h"
#define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs" #define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs"
STATIC CHAR16 *mSemihostFsLabel; STATIC CHAR16 *mSemihostFsLabel;
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = { EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION, EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,
VolumeOpen VolumeOpen
}; };
EFI_FILE gSemihostFsFile = { EFI_FILE gSemihostFsFile = {
EFI_FILE_PROTOCOL_REVISION, EFI_FILE_PROTOCOL_REVISION,
FileOpen, FileOpen,
FileClose, FileClose,
@ -54,43 +54,45 @@ EFI_FILE gSemihostFsFile = {
// Device path for semi-hosting. It contains our auto-generated Caller ID GUID. // Device path for semi-hosting. It contains our auto-generated Caller ID GUID.
// //
typedef struct { typedef struct {
VENDOR_DEVICE_PATH Guid; VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End; EFI_DEVICE_PATH_PROTOCOL End;
} SEMIHOST_DEVICE_PATH; } SEMIHOST_DEVICE_PATH;
SEMIHOST_DEVICE_PATH gDevicePath = { SEMIHOST_DEVICE_PATH gDevicePath = {
{ {
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } }, { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 }
},
EFI_CALLER_ID_GUID EFI_CALLER_ID_GUID
}, },
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } } { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
}
}; };
typedef struct { typedef struct {
LIST_ENTRY Link; LIST_ENTRY Link;
UINT64 Signature; UINT64 Signature;
EFI_FILE File; EFI_FILE File;
CHAR8 *FileName; CHAR8 *FileName;
UINT64 OpenMode; UINT64 OpenMode;
UINT32 Position; UINT32 Position;
UINTN SemihostHandle; UINTN SemihostHandle;
BOOLEAN IsRoot; BOOLEAN IsRoot;
EFI_FILE_INFO Info; EFI_FILE_INFO Info;
} SEMIHOST_FCB; } SEMIHOST_FCB;
#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' ) #define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' )
#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE) #define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)
#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE); #define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);
EFI_HANDLE gInstallHandle = NULL; EFI_HANDLE gInstallHandle = NULL;
LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList); LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);
SEMIHOST_FCB * SEMIHOST_FCB *
AllocateFCB ( AllocateFCB (
VOID VOID
) )
{ {
SEMIHOST_FCB *Fcb; SEMIHOST_FCB *Fcb;
Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB)); Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
if (Fcb != NULL) { if (Fcb != NULL) {
@ -103,7 +105,7 @@ AllocateFCB (
VOID VOID
FreeFCB ( FreeFCB (
IN SEMIHOST_FCB *Fcb IN SEMIHOST_FCB *Fcb
) )
{ {
// Remove Fcb from gFileList. // Remove Fcb from gFileList.
@ -115,15 +117,13 @@ FreeFCB (
FreePool (Fcb); FreePool (Fcb);
} }
EFI_STATUS EFI_STATUS
VolumeOpen ( VolumeOpen (
IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This, IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
OUT EFI_FILE **Root OUT EFI_FILE **Root
) )
{ {
SEMIHOST_FCB *RootFcb; SEMIHOST_FCB *RootFcb;
if (Root == NULL) { if (Root == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
@ -134,7 +134,7 @@ VolumeOpen (
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
RootFcb->IsRoot = TRUE; RootFcb->IsRoot = TRUE;
RootFcb->Info.Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY; RootFcb->Info.Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;
InsertTailList (&gFileList, &RootFcb->Link); InsertTailList (&gFileList, &RootFcb->Link);
@ -191,29 +191,33 @@ FileOpen (
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if ( (OpenMode != EFI_FILE_MODE_READ) && if ((OpenMode != EFI_FILE_MODE_READ) &&
(OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) && (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) &&
(OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)) ) { (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (((OpenMode & EFI_FILE_MODE_CREATE) != 0) && if (((OpenMode & EFI_FILE_MODE_CREATE) != 0) &&
((Attributes & EFI_FILE_DIRECTORY) != 0)) { ((Attributes & EFI_FILE_DIRECTORY) != 0))
{
return EFI_WRITE_PROTECTED; return EFI_WRITE_PROTECTED;
} }
Length = StrLen (FileName) + 1; Length = StrLen (FileName) + 1;
AsciiFileName = AllocatePool (Length); AsciiFileName = AllocatePool (Length);
if (AsciiFileName == NULL) { if (AsciiFileName == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
UnicodeStrToAsciiStrS (FileName, AsciiFileName, Length); UnicodeStrToAsciiStrS (FileName, AsciiFileName, Length);
// Opening '/', '\', '.', or the NULL pathname is trying to open the root directory // Opening '/', '\', '.', or the NULL pathname is trying to open the root directory
if ((AsciiStrCmp (AsciiFileName, "\\") == 0) || if ((AsciiStrCmp (AsciiFileName, "\\") == 0) ||
(AsciiStrCmp (AsciiFileName, "/") == 0) || (AsciiStrCmp (AsciiFileName, "/") == 0) ||
(AsciiStrCmp (AsciiFileName, "") == 0) || (AsciiStrCmp (AsciiFileName, "") == 0) ||
(AsciiStrCmp (AsciiFileName, ".") == 0) ) { (AsciiStrCmp (AsciiFileName, ".") == 0))
{
FreePool (AsciiFileName); FreePool (AsciiFileName);
return (VolumeOpen (&gSemihostFs, NewHandle)); return (VolumeOpen (&gSemihostFs, NewHandle));
} }
@ -232,6 +236,7 @@ FileOpen (
} else { } else {
SemihostMode = SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE; SemihostMode = SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;
} }
Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle); Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
@ -279,7 +284,7 @@ FileOpen (
FileFcb->Info.FileSize = Length; FileFcb->Info.FileSize = Length;
FileFcb->Info.PhysicalSize = Length; FileFcb->Info.PhysicalSize = Length;
FileFcb->Info.Attribute = ((OpenMode & EFI_FILE_MODE_CREATE) != 0) ? FileFcb->Info.Attribute = ((OpenMode & EFI_FILE_MODE_CREATE) != 0) ?
Attributes : 0; Attributes : 0;
InsertTailList (&gFileList, &FileFcb->Link); InsertTailList (&gFileList, &FileFcb->Link);
@ -308,7 +313,7 @@ STATIC
EFI_STATUS EFI_STATUS
TruncateFile ( TruncateFile (
IN CHAR8 *FileName, IN CHAR8 *FileName,
IN UINTN Size IN UINTN Size
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@ -338,7 +343,7 @@ TruncateFile (
goto Error; goto Error;
} }
Read = 0; Read = 0;
Remaining = Size; Remaining = Size;
while (Remaining > 0) { while (Remaining > 0) {
ToRead = Remaining; ToRead = Remaining;
@ -346,11 +351,12 @@ TruncateFile (
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
goto Error; goto Error;
} }
Remaining -= ToRead; Remaining -= ToRead;
Read += ToRead; Read += ToRead;
} }
Return = SemihostFileClose (FileHandle); Return = SemihostFileClose (FileHandle);
FileHandle = 0; FileHandle = 0;
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
goto Error; goto Error;
@ -379,12 +385,12 @@ Error:
if (FileHandle != 0) { if (FileHandle != 0) {
SemihostFileClose (FileHandle); SemihostFileClose (FileHandle);
} }
if (Buffer != NULL) { if (Buffer != NULL) {
FreePool (Buffer); FreePool (Buffer);
} }
return (Status); return (Status);
} }
/** /**
@ -402,13 +408,13 @@ FileClose (
IN EFI_FILE *This IN EFI_FILE *This
) )
{ {
SEMIHOST_FCB *Fcb; SEMIHOST_FCB *Fcb;
if (This == NULL) { if (This == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
Fcb = SEMIHOST_FCB_FROM_THIS(This); Fcb = SEMIHOST_FCB_FROM_THIS (This);
if (!Fcb->IsRoot) { if (!Fcb->IsRoot) {
SemihostFileClose (Fcb->SemihostHandle); SemihostFileClose (Fcb->SemihostHandle);
@ -420,6 +426,7 @@ FileClose (
if (Fcb->Info.FileSize < Fcb->Info.PhysicalSize) { if (Fcb->Info.FileSize < Fcb->Info.PhysicalSize) {
TruncateFile (Fcb->FileName, Fcb->Info.FileSize); TruncateFile (Fcb->FileName, Fcb->Info.FileSize);
} }
FreePool (Fcb->FileName); FreePool (Fcb->FileName);
} }
@ -441,7 +448,7 @@ FileClose (
**/ **/
EFI_STATUS EFI_STATUS
FileDelete ( FileDelete (
IN EFI_FILE *This IN EFI_FILE *This
) )
{ {
SEMIHOST_FCB *Fcb; SEMIHOST_FCB *Fcb;
@ -471,6 +478,7 @@ FileDelete (
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
return EFI_WARN_DELETE_FAILURE; return EFI_WARN_DELETE_FAILURE;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} else { } else {
return EFI_WARN_DELETE_FAILURE; return EFI_WARN_DELETE_FAILURE;
@ -566,14 +574,15 @@ ExtendFile (
} }
Remaining = Size; Remaining = Size;
SetMem (WriteBuffer, 0, sizeof(WriteBuffer)); SetMem (WriteBuffer, 0, sizeof (WriteBuffer));
while (Remaining > 0) { while (Remaining > 0) {
WriteNb = MIN (Remaining, sizeof(WriteBuffer)); WriteNb = MIN (Remaining, sizeof (WriteBuffer));
WriteSize = WriteNb; WriteSize = WriteNb;
Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer); Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer);
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
Remaining -= WriteNb; Remaining -= WriteNb;
} }
@ -599,9 +608,9 @@ ExtendFile (
**/ **/
EFI_STATUS EFI_STATUS
FileWrite ( FileWrite (
IN EFI_FILE *This, IN EFI_FILE *This,
IN OUT UINTN *BufferSize, IN OUT UINTN *BufferSize,
IN VOID *Buffer IN VOID *Buffer
) )
{ {
SEMIHOST_FCB *Fcb; SEMIHOST_FCB *Fcb;
@ -617,8 +626,9 @@ FileWrite (
Fcb = SEMIHOST_FCB_FROM_THIS (This); Fcb = SEMIHOST_FCB_FROM_THIS (This);
// We cannot write a read-only file // We cannot write a read-only file
if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY) if ( (Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
|| !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) { || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE))
{
return EFI_ACCESS_DENIED; return EFI_ACCESS_DENIED;
} }
@ -632,11 +642,12 @@ FileWrite (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
Fcb->Info.FileSize = Fcb->Position; Fcb->Info.FileSize = Fcb->Position;
} }
WriteSize = *BufferSize; WriteSize = *BufferSize;
Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer); Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
@ -650,6 +661,7 @@ FileWrite (
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
Fcb->Info.PhysicalSize = Length; Fcb->Info.PhysicalSize = Length;
return EFI_SUCCESS; return EFI_SUCCESS;
@ -668,17 +680,17 @@ FileWrite (
**/ **/
EFI_STATUS EFI_STATUS
FileGetPosition ( FileGetPosition (
IN EFI_FILE *This, IN EFI_FILE *This,
OUT UINT64 *Position OUT UINT64 *Position
) )
{ {
SEMIHOST_FCB *Fcb; SEMIHOST_FCB *Fcb;
if ((This == NULL) || (Position == NULL)) { if ((This == NULL) || (Position == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
Fcb = SEMIHOST_FCB_FROM_THIS(This); Fcb = SEMIHOST_FCB_FROM_THIS (This);
*Position = Fcb->Position; *Position = Fcb->Position;
@ -701,8 +713,8 @@ FileGetPosition (
**/ **/
EFI_STATUS EFI_STATUS
FileSetPosition ( FileSetPosition (
IN EFI_FILE *This, IN EFI_FILE *This,
IN UINT64 Position IN UINT64 Position
) )
{ {
SEMIHOST_FCB *Fcb; SEMIHOST_FCB *Fcb;
@ -718,8 +730,7 @@ FileSetPosition (
if (Position != 0) { if (Position != 0) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
} } else {
else {
// //
// UEFI Spec section 12.5: // UEFI Spec section 12.5:
// "Seeking to position 0xFFFFFFFFFFFFFFFF causes the current position to // "Seeking to position 0xFFFFFFFFFFFFFFFF causes the current position to
@ -728,6 +739,7 @@ FileSetPosition (
if (Position == 0xFFFFFFFFFFFFFFFF) { if (Position == 0xFFFFFFFFFFFFFFFF) {
Position = Fcb->Info.FileSize; Position = Fcb->Info.FileSize;
} }
Return = SemihostFileSeek (Fcb->SemihostHandle, MIN (Position, Fcb->Info.FileSize)); Return = SemihostFileSeek (Fcb->SemihostHandle, MIN (Position, Fcb->Info.FileSize));
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
@ -760,14 +772,14 @@ GetFileInfo (
OUT VOID *Buffer OUT VOID *Buffer
) )
{ {
EFI_FILE_INFO *Info; EFI_FILE_INFO *Info;
UINTN NameSize; UINTN NameSize;
UINTN ResultSize; UINTN ResultSize;
UINTN Index; UINTN Index;
if (Fcb->IsRoot) { if (Fcb->IsRoot) {
NameSize = 0; NameSize = 0;
ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16); ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof (CHAR16);
} else { } else {
NameSize = AsciiStrLen (Fcb->FileName) + 1; NameSize = AsciiStrLen (Fcb->FileName) + 1;
ResultSize = SIZE_OF_EFI_FILE_INFO + NameSize * sizeof (CHAR16); ResultSize = SIZE_OF_EFI_FILE_INFO + NameSize * sizeof (CHAR16);
@ -787,7 +799,7 @@ GetFileInfo (
Info->Size = ResultSize; Info->Size = ResultSize;
if (Fcb->IsRoot) { if (Fcb->IsRoot) {
Info->FileName[0] = L'\0'; Info->FileName[0] = L'\0';
} else { } else {
for (Index = 0; Index < NameSize; Index++) { for (Index = 0; Index < NameSize; Index++) {
Info->FileName[Index] = Fcb->FileName[Index]; Info->FileName[Index] = Fcb->FileName[Index];
@ -818,9 +830,9 @@ GetFileInfo (
STATIC STATIC
EFI_STATUS EFI_STATUS
GetFilesystemInfo ( GetFilesystemInfo (
IN SEMIHOST_FCB *Fcb, IN SEMIHOST_FCB *Fcb,
IN OUT UINTN *BufferSize, IN OUT UINTN *BufferSize,
OUT VOID *Buffer OUT VOID *Buffer
) )
{ {
EFI_FILE_SYSTEM_INFO *Info; EFI_FILE_SYSTEM_INFO *Info;
@ -882,18 +894,19 @@ FileGetInfo (
OUT VOID *Buffer OUT VOID *Buffer
) )
{ {
SEMIHOST_FCB *Fcb; SEMIHOST_FCB *Fcb;
EFI_STATUS Status; EFI_STATUS Status;
UINTN ResultSize; UINTN ResultSize;
if ((This == NULL) || if ((This == NULL) ||
(InformationType == NULL) || (InformationType == NULL) ||
(BufferSize == NULL) || (BufferSize == NULL) ||
((Buffer == NULL) && (*BufferSize > 0)) ) { ((Buffer == NULL) && (*BufferSize > 0)))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
Fcb = SEMIHOST_FCB_FROM_THIS(This); Fcb = SEMIHOST_FCB_FROM_THIS (This);
if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) { if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {
Status = GetFilesystemInfo (Fcb, BufferSize, Buffer); Status = GetFilesystemInfo (Fcb, BufferSize, Buffer);
@ -963,11 +976,12 @@ SetFileInfo (
return EFI_ACCESS_DENIED; return EFI_ACCESS_DENIED;
} }
Length = StrLen (Info->FileName) + 1; Length = StrLen (Info->FileName) + 1;
AsciiFileName = AllocatePool (Length); AsciiFileName = AllocatePool (Length);
if (AsciiFileName == NULL) { if (AsciiFileName == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
UnicodeStrToAsciiStrS (Info->FileName, AsciiFileName, Length); UnicodeStrToAsciiStrS (Info->FileName, AsciiFileName, Length);
FileSizeIsDifferent = (Info->FileSize != Fcb->Info.FileSize); FileSizeIsDifferent = (Info->FileSize != Fcb->Info.FileSize);
@ -985,7 +999,8 @@ SetFileInfo (
// description. // description.
// //
if ((Fcb->OpenMode == EFI_FILE_MODE_READ) || if ((Fcb->OpenMode == EFI_FILE_MODE_READ) ||
(Fcb->Info.Attribute & EFI_FILE_READ_ONLY) ) { (Fcb->Info.Attribute & EFI_FILE_READ_ONLY))
{
if (FileSizeIsDifferent || FileNameIsDifferent || ReadOnlyIsDifferent) { if (FileSizeIsDifferent || FileNameIsDifferent || ReadOnlyIsDifferent) {
Status = EFI_ACCESS_DENIED; Status = EFI_ACCESS_DENIED;
goto Error; goto Error;
@ -1006,6 +1021,7 @@ SetFileInfo (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
goto Error; goto Error;
} }
// //
// The read/write position from the host file system point of view // The read/write position from the host file system point of view
// is at the end of the file. If the position from this module // is at the end of the file. If the position from this module
@ -1016,12 +1032,14 @@ SetFileInfo (
FileSetPosition (&Fcb->File, Fcb->Position); FileSetPosition (&Fcb->File, Fcb->Position);
} }
} }
Fcb->Info.FileSize = FileSize; Fcb->Info.FileSize = FileSize;
Return = SemihostFileLength (Fcb->SemihostHandle, &Length); Return = SemihostFileLength (Fcb->SemihostHandle, &Length);
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
goto Error; goto Error;
} }
Fcb->Info.PhysicalSize = Length; Fcb->Info.PhysicalSize = Length;
} }
@ -1048,6 +1066,7 @@ SetFileInfo (
if (RETURN_ERROR (Return)) { if (RETURN_ERROR (Return)) {
goto Error; goto Error;
} }
FreePool (Fcb->FileName); FreePool (Fcb->FileName);
Fcb->FileName = AsciiFileName; Fcb->FileName = AsciiFileName;
AsciiFileName = NULL; AsciiFileName = NULL;
@ -1119,19 +1138,24 @@ FileSetInfo (
if (Info->Size < (SIZE_OF_EFI_FILE_INFO + StrSize (Info->FileName))) { if (Info->Size < (SIZE_OF_EFI_FILE_INFO + StrSize (Info->FileName))) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (BufferSize < Info->Size) { if (BufferSize < Info->Size) {
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
return SetFileInfo (Fcb, Info); return SetFileInfo (Fcb, Info);
} else if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) { } else if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {
SystemInfo = Buffer; SystemInfo = Buffer;
if (SystemInfo->Size < if (SystemInfo->Size <
(SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel))) { (SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel)))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (BufferSize < SystemInfo->Size) { if (BufferSize < SystemInfo->Size) {
return EFI_BAD_BUFFER_SIZE; return EFI_BAD_BUFFER_SIZE;
} }
Buffer = SystemInfo->VolumeLabel; Buffer = SystemInfo->VolumeLabel;
if (StrSize (Buffer) > 0) { if (StrSize (Buffer) > 0) {
@ -1155,18 +1179,19 @@ FileSetInfo (
EFI_STATUS EFI_STATUS
FileFlush ( FileFlush (
IN EFI_FILE *File IN EFI_FILE *File
) )
{ {
SEMIHOST_FCB *Fcb; SEMIHOST_FCB *Fcb;
Fcb = SEMIHOST_FCB_FROM_THIS(File); Fcb = SEMIHOST_FCB_FROM_THIS (File);
if (Fcb->IsRoot) { if (Fcb->IsRoot) {
return EFI_SUCCESS; return EFI_SUCCESS;
} else { } else {
if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY) if ( (Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
|| !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) { || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE))
{
return EFI_ACCESS_DENIED; return EFI_ACCESS_DENIED;
} else { } else {
return EFI_SUCCESS; return EFI_SUCCESS;
@ -1176,11 +1201,11 @@ FileFlush (
EFI_STATUS EFI_STATUS
SemihostFsEntryPoint ( SemihostFsEntryPoint (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = EFI_NOT_FOUND; Status = EFI_NOT_FOUND;
@ -1192,12 +1217,14 @@ SemihostFsEntryPoint (
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&gInstallHandle, &gInstallHandle,
&gEfiSimpleFileSystemProtocolGuid, &gSemihostFs, &gEfiSimpleFileSystemProtocolGuid,
&gEfiDevicePathProtocolGuid, &gDevicePath, &gSemihostFs,
&gEfiDevicePathProtocolGuid,
&gDevicePath,
NULL NULL
); );
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
FreePool (mSemihostFsLabel); FreePool (mSemihostFsLabel);
} }
} }

23
ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h
View File

@ -12,8 +12,8 @@
EFI_STATUS EFI_STATUS
VolumeOpen ( VolumeOpen (
IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This, IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
OUT EFI_FILE **Root OUT EFI_FILE **Root
); );
/** /**
@ -79,7 +79,7 @@ FileClose (
**/ **/
EFI_STATUS EFI_STATUS
FileDelete ( FileDelete (
IN EFI_FILE *This IN EFI_FILE *This
); );
/** /**
@ -127,9 +127,9 @@ FileRead (
**/ **/
EFI_STATUS EFI_STATUS
FileWrite ( FileWrite (
IN EFI_FILE *This, IN EFI_FILE *This,
IN OUT UINTN *BufferSize, IN OUT UINTN *BufferSize,
IN VOID *Buffer IN VOID *Buffer
); );
/** /**
@ -145,8 +145,8 @@ FileWrite (
**/ **/
EFI_STATUS EFI_STATUS
FileGetPosition ( FileGetPosition (
IN EFI_FILE *File, IN EFI_FILE *File,
OUT UINT64 *Position OUT UINT64 *Position
); );
/** /**
@ -164,8 +164,8 @@ FileGetPosition (
**/ **/
EFI_STATUS EFI_STATUS
FileSetPosition ( FileSetPosition (
IN EFI_FILE *File, IN EFI_FILE *File,
IN UINT64 Position IN UINT64 Position
); );
/** /**
@ -239,8 +239,7 @@ FileSetInfo (
EFI_STATUS EFI_STATUS
FileFlush ( FileFlush (
IN EFI_FILE *File IN EFI_FILE *File
); );
#endif // SEMIHOST_FS_H_ #endif // SEMIHOST_FS_H_

3
ArmPkg/Include/AsmMacroIoLib.h
View File

@ -9,7 +9,6 @@
**/ **/
#ifndef ASM_MACRO_IO_LIB_H_ #ifndef ASM_MACRO_IO_LIB_H_
#define ASM_MACRO_IO_LIB_H_ #define ASM_MACRO_IO_LIB_H_
@ -20,7 +19,7 @@
.p2align 2 ; \ .p2align 2 ; \
Name: Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) #define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define MOV32(Reg, Val) \ #define MOV32(Reg, Val) \
movw Reg, #(Val) & 0xffff ; \ movw Reg, #(Val) & 0xffff ; \

4
ArmPkg/Include/AsmMacroIoLibV8.h
View File

@ -9,7 +9,6 @@
**/ **/
#ifndef ASM_MACRO_IO_LIBV8_H_ #ifndef ASM_MACRO_IO_LIBV8_H_
#define ASM_MACRO_IO_LIBV8_H_ #define ASM_MACRO_IO_LIBV8_H_
@ -24,7 +23,6 @@
cbnz SAFE_XREG, 1f ;\ cbnz SAFE_XREG, 1f ;\
b . ;// We should never get here b . ;// We should never get here
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1 // CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
// This only selects between EL1 and EL2 and EL3, else we die. // This only selects between EL1 and EL2 and EL3, else we die.
// Provide the Macro with a safe temp xreg to use. // Provide the Macro with a safe temp xreg to use.
@ -42,7 +40,7 @@
.type Name, %function ; \ .type Name, %function ; \
Name: Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) #define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define MOV32(Reg, Val) \ #define MOV32(Reg, Val) \
movz Reg, (Val) >> 16, lsl #16 ; \ movz Reg, (Val) >> 16, lsl #16 ; \

150
ArmPkg/Include/Chipset/AArch64.h
View File

@ -13,108 +13,108 @@
#include <Chipset/AArch64Mmu.h> #include <Chipset/AArch64Mmu.h>
// ARM Interrupt ID in Exception Table // ARM Interrupt ID in Exception Table
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
// CPACR - Coprocessor Access Control Register definitions // CPACR - Coprocessor Access Control Register definitions
#define CPACR_TTA_EN (1UL << 28) #define CPACR_TTA_EN (1UL << 28)
#define CPACR_FPEN_EL1 (1UL << 20) #define CPACR_FPEN_EL1 (1UL << 20)
#define CPACR_FPEN_FULL (3UL << 20) #define CPACR_FPEN_FULL (3UL << 20)
#define CPACR_CP_FULL_ACCESS 0x300000 #define CPACR_CP_FULL_ACCESS 0x300000
// Coprocessor Trap Register (CPTR) // Coprocessor Trap Register (CPTR)
#define AARCH64_CPTR_TFP (1 << 10) #define AARCH64_CPTR_TFP (1 << 10)
// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
#define AARCH64_PFR0_FP (0xF << 16) #define AARCH64_PFR0_FP (0xF << 16)
#define AARCH64_PFR0_GIC (0xF << 24) #define AARCH64_PFR0_GIC (0xF << 24)
// SCR - Secure Configuration Register definitions // SCR - Secure Configuration Register definitions
#define SCR_NS (1 << 0) #define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1) #define SCR_IRQ (1 << 1)
#define SCR_FIQ (1 << 2) #define SCR_FIQ (1 << 2)
#define SCR_EA (1 << 3) #define SCR_EA (1 << 3)
#define SCR_FW (1 << 4) #define SCR_FW (1 << 4)
#define SCR_AW (1 << 5) #define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions // MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4 #define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF #define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMV8 0xD0F #define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03 #define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07 #define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A72 0xD08 #define ARM_CPU_TYPE_A72 0xD08
#define ARM_CPU_TYPE_A15 0xC0F #define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A9 0xC09 #define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A7 0xC07 #define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05 #define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) ) #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF)) #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
// Hypervisor Configuration Register // Hypervisor Configuration Register
#define ARM_HCR_FMO BIT3 #define ARM_HCR_FMO BIT3
#define ARM_HCR_IMO BIT4 #define ARM_HCR_IMO BIT4
#define ARM_HCR_AMO BIT5 #define ARM_HCR_AMO BIT5
#define ARM_HCR_TSC BIT19 #define ARM_HCR_TSC BIT19
#define ARM_HCR_TGE BIT27 #define ARM_HCR_TGE BIT27
// Exception Syndrome Register // Exception Syndrome Register
#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr)) #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr)) #define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
#define AARCH64_ESR_EC_SMC32 (0x13 << 26) #define AARCH64_ESR_EC_SMC32 (0x13 << 26)
#define AARCH64_ESR_EC_SMC64 (0x17 << 26) #define AARCH64_ESR_EC_SMC64 (0x17 << 26)
// AArch64 Exception Level // AArch64 Exception Level
#define AARCH64_EL3 0xC #define AARCH64_EL3 0xC
#define AARCH64_EL2 0x8 #define AARCH64_EL2 0x8
#define AARCH64_EL1 0x4 #define AARCH64_EL1 0x4
// Saved Program Status Register definitions // Saved Program Status Register definitions
#define SPSR_A BIT8 #define SPSR_A BIT8
#define SPSR_I BIT7 #define SPSR_I BIT7
#define SPSR_F BIT6 #define SPSR_F BIT6
#define SPSR_AARCH32 BIT4 #define SPSR_AARCH32 BIT4
#define SPSR_AARCH32_MODE_USER 0x0 #define SPSR_AARCH32_MODE_USER 0x0
#define SPSR_AARCH32_MODE_FIQ 0x1 #define SPSR_AARCH32_MODE_FIQ 0x1
#define SPSR_AARCH32_MODE_IRQ 0x2 #define SPSR_AARCH32_MODE_IRQ 0x2
#define SPSR_AARCH32_MODE_SVC 0x3 #define SPSR_AARCH32_MODE_SVC 0x3
#define SPSR_AARCH32_MODE_ABORT 0x7 #define SPSR_AARCH32_MODE_ABORT 0x7
#define SPSR_AARCH32_MODE_UNDEF 0xB #define SPSR_AARCH32_MODE_UNDEF 0xB
#define SPSR_AARCH32_MODE_SYS 0xF #define SPSR_AARCH32_MODE_SYS 0xF
// Counter-timer Hypervisor Control register definitions // Counter-timer Hypervisor Control register definitions
#define CNTHCTL_EL2_EL1PCTEN BIT0 #define CNTHCTL_EL2_EL1PCTEN BIT0
#define CNTHCTL_EL2_EL1PCEN BIT1 #define CNTHCTL_EL2_EL1PCEN BIT1
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1) #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
// Vector table offset definitions // Vector table offset definitions
#define ARM_VECTOR_CUR_SP0_SYNC 0x000 #define ARM_VECTOR_CUR_SP0_SYNC 0x000
#define ARM_VECTOR_CUR_SP0_IRQ 0x080 #define ARM_VECTOR_CUR_SP0_IRQ 0x080
#define ARM_VECTOR_CUR_SP0_FIQ 0x100 #define ARM_VECTOR_CUR_SP0_FIQ 0x100
#define ARM_VECTOR_CUR_SP0_SERR 0x180 #define ARM_VECTOR_CUR_SP0_SERR 0x180
#define ARM_VECTOR_CUR_SPX_SYNC 0x200 #define ARM_VECTOR_CUR_SPX_SYNC 0x200
#define ARM_VECTOR_CUR_SPX_IRQ 0x280 #define ARM_VECTOR_CUR_SPX_IRQ 0x280
#define ARM_VECTOR_CUR_SPX_FIQ 0x300 #define ARM_VECTOR_CUR_SPX_FIQ 0x300
#define ARM_VECTOR_CUR_SPX_SERR 0x380 #define ARM_VECTOR_CUR_SPX_SERR 0x380
#define ARM_VECTOR_LOW_A64_SYNC 0x400 #define ARM_VECTOR_LOW_A64_SYNC 0x400
#define ARM_VECTOR_LOW_A64_IRQ 0x480 #define ARM_VECTOR_LOW_A64_IRQ 0x480
#define ARM_VECTOR_LOW_A64_FIQ 0x500 #define ARM_VECTOR_LOW_A64_FIQ 0x500
#define ARM_VECTOR_LOW_A64_SERR 0x580 #define ARM_VECTOR_LOW_A64_SERR 0x580
#define ARM_VECTOR_LOW_A32_SYNC 0x600 #define ARM_VECTOR_LOW_A32_SYNC 0x600
#define ARM_VECTOR_LOW_A32_IRQ 0x680 #define ARM_VECTOR_LOW_A32_IRQ 0x680
#define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_FIQ 0x700
#define ARM_VECTOR_LOW_A32_SERR 0x780 #define ARM_VECTOR_LOW_A32_SERR 0x780
// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we // The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
// build for ARMv8.0, we need to define the register here. // build for ARMv8.0, we need to define the register here.
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
#define VECTOR_BASE(tbl) \ #define VECTOR_BASE(tbl) \
.section .text.##tbl##,"ax"; \ .section .text.##tbl##,"ax"; \
@ -151,7 +151,7 @@ ArmReadTpidrurw (
VOID VOID
EFIAPI EFIAPI
ArmWriteTpidrurw ( ArmWriteTpidrurw (
UINTN Value UINTN Value
); );
UINTN UINTN
@ -163,7 +163,7 @@ ArmGetTCR (
VOID VOID
EFIAPI EFIAPI
ArmSetTCR ( ArmSetTCR (
UINTN Value UINTN Value
); );
UINTN UINTN
@ -175,7 +175,7 @@ ArmGetMAIR (
VOID VOID
EFIAPI EFIAPI
ArmSetMAIR ( ArmSetMAIR (
UINTN Value UINTN Value
); );
VOID VOID
@ -210,7 +210,7 @@ ArmDisableAllExceptions (
VOID VOID
ArmWriteHcr ( ArmWriteHcr (
IN UINTN Hcr IN UINTN Hcr
); );
UINTN UINTN
@ -225,7 +225,7 @@ ArmReadCurrentEL (
UINTN UINTN
ArmWriteCptr ( ArmWriteCptr (
IN UINT64 Cptr IN UINT64 Cptr
); );
UINT32 UINT32
@ -235,7 +235,7 @@ ArmReadCntHctl (
VOID VOID
ArmWriteCntHctl ( ArmWriteCntHctl (
IN UINT32 CntHctl IN UINT32 CntHctl
); );
#endif // AARCH64_H_ #endif // AARCH64_H_

257
ArmPkg/Include/Chipset/AArch64Mmu.h
View File

@ -12,12 +12,12 @@
// //
// Memory Attribute Indirection register Definitions // Memory Attribute Indirection register Definitions
// //
#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL #define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL #define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL #define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL #define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
#define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8)) #define MAIR_ATTR(n, value) ((value) << (((n) >> 2)*8))
// //
// Long-descriptor Translation Table format // Long-descriptor Translation Table format
@ -27,7 +27,7 @@
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0 // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9)) #define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))
#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level)) #define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
// Get the associated entry in the given Translation Table // Get the associated entry in the given Translation Table
#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \ #define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \
@ -35,164 +35,161 @@
// Return the smallest address granularity from the table level. // Return the smallest address granularity from the table level.
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0 // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel)) #define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \ #define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64)))) ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))
// There are 512 entries per table when 4K Granularity // There are 512 entries per table when 4K Granularity
#define TT_ENTRY_COUNT 512 #define TT_ENTRY_COUNT 512
#define TT_ALIGNMENT_BLOCK_ENTRY BIT12 #define TT_ALIGNMENT_BLOCK_ENTRY BIT12
#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12 #define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12) #define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12) #define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
#define TT_TYPE_MASK 0x3 #define TT_TYPE_MASK 0x3
#define TT_TYPE_TABLE_ENTRY 0x3 #define TT_TYPE_TABLE_ENTRY 0x3
#define TT_TYPE_BLOCK_ENTRY 0x1 #define TT_TYPE_BLOCK_ENTRY 0x1
#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3 #define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
#define TT_ATTR_INDX_MASK (0x7 << 2) #define TT_ATTR_INDX_MASK (0x7 << 2)
#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2) #define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2) #define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2) #define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2) #define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
#define TT_AP_MASK (0x3UL << 6) #define TT_AP_MASK (0x3UL << 6)
#define TT_AP_NO_RW (0x0UL << 6) #define TT_AP_NO_RW (0x0UL << 6)
#define TT_AP_RW_RW (0x1UL << 6) #define TT_AP_RW_RW (0x1UL << 6)
#define TT_AP_NO_RO (0x2UL << 6) #define TT_AP_NO_RO (0x2UL << 6)
#define TT_AP_RO_RO (0x3UL << 6) #define TT_AP_RO_RO (0x3UL << 6)
#define TT_NS BIT5 #define TT_NS BIT5
#define TT_AF BIT10 #define TT_AF BIT10
#define TT_SH_NON_SHAREABLE (0x0 << 8) #define TT_SH_NON_SHAREABLE (0x0 << 8)
#define TT_SH_OUTER_SHAREABLE (0x2 << 8) #define TT_SH_OUTER_SHAREABLE (0x2 << 8)
#define TT_SH_INNER_SHAREABLE (0x3 << 8) #define TT_SH_INNER_SHAREABLE (0x3 << 8)
#define TT_SH_MASK (0x3 << 8) #define TT_SH_MASK (0x3 << 8)
#define TT_PXN_MASK BIT53 #define TT_PXN_MASK BIT53
#define TT_UXN_MASK BIT54 // EL1&0 #define TT_UXN_MASK BIT54 // EL1&0
#define TT_XN_MASK BIT54 // EL2 / EL3 #define TT_XN_MASK BIT54 // EL2 / EL3
#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2)) #define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
#define TT_TABLE_PXN BIT59 #define TT_TABLE_PXN BIT59
#define TT_TABLE_UXN BIT60 // EL1&0 #define TT_TABLE_UXN BIT60 // EL1&0
#define TT_TABLE_XN BIT60 // EL2 / EL3 #define TT_TABLE_XN BIT60 // EL2 / EL3
#define TT_TABLE_NS BIT63 #define TT_TABLE_NS BIT63
#define TT_TABLE_AP_MASK (BIT62 | BIT61) #define TT_TABLE_AP_MASK (BIT62 | BIT61)
#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61) #define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61) #define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61) #define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
// //
// Translation Control Register // Translation Control Register
// //
#define TCR_T0SZ_MASK 0x3FUL #define TCR_T0SZ_MASK 0x3FUL
#define TCR_PS_4GB (0UL << 16) #define TCR_PS_4GB (0UL << 16)
#define TCR_PS_64GB (1UL << 16) #define TCR_PS_64GB (1UL << 16)
#define TCR_PS_1TB (2UL << 16) #define TCR_PS_1TB (2UL << 16)
#define TCR_PS_4TB (3UL << 16) #define TCR_PS_4TB (3UL << 16)
#define TCR_PS_16TB (4UL << 16) #define TCR_PS_16TB (4UL << 16)
#define TCR_PS_256TB (5UL << 16) #define TCR_PS_256TB (5UL << 16)
#define TCR_TG0_4KB (0UL << 14) #define TCR_TG0_4KB (0UL << 14)
#define TCR_TG1_4KB (2UL << 30) #define TCR_TG1_4KB (2UL << 30)
#define TCR_IPS_4GB (0ULL << 32) #define TCR_IPS_4GB (0ULL << 32)
#define TCR_IPS_64GB (1ULL << 32) #define TCR_IPS_64GB (1ULL << 32)
#define TCR_IPS_1TB (2ULL << 32) #define TCR_IPS_1TB (2ULL << 32)
#define TCR_IPS_4TB (3ULL << 32) #define TCR_IPS_4TB (3ULL << 32)
#define TCR_IPS_16TB (4ULL << 32) #define TCR_IPS_16TB (4ULL << 32)
#define TCR_IPS_256TB (5ULL << 32) #define TCR_IPS_256TB (5ULL << 32)
#define TCR_EPD1 (1UL << 23) #define TCR_EPD1 (1UL << 23)
#define TTBR_ASID_FIELD (48) #define TTBR_ASID_FIELD (48)
#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD) #define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits #define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
#define TCR_EL1_T0SZ_FIELD (0) #define TCR_EL1_T0SZ_FIELD (0)
#define TCR_EL1_EPD0_FIELD (7) #define TCR_EL1_EPD0_FIELD (7)
#define TCR_EL1_IRGN0_FIELD (8) #define TCR_EL1_IRGN0_FIELD (8)
#define TCR_EL1_ORGN0_FIELD (10) #define TCR_EL1_ORGN0_FIELD (10)
#define TCR_EL1_SH0_FIELD (12) #define TCR_EL1_SH0_FIELD (12)
#define TCR_EL1_TG0_FIELD (14) #define TCR_EL1_TG0_FIELD (14)
#define TCR_EL1_T1SZ_FIELD (16) #define TCR_EL1_T1SZ_FIELD (16)
#define TCR_EL1_A1_FIELD (22) #define TCR_EL1_A1_FIELD (22)
#define TCR_EL1_EPD1_FIELD (23) #define TCR_EL1_EPD1_FIELD (23)
#define TCR_EL1_IRGN1_FIELD (24) #define TCR_EL1_IRGN1_FIELD (24)
#define TCR_EL1_ORGN1_FIELD (26) #define TCR_EL1_ORGN1_FIELD (26)
#define TCR_EL1_SH1_FIELD (28) #define TCR_EL1_SH1_FIELD (28)
#define TCR_EL1_TG1_FIELD (30) #define TCR_EL1_TG1_FIELD (30)
#define TCR_EL1_IPS_FIELD (32) #define TCR_EL1_IPS_FIELD (32)
#define TCR_EL1_AS_FIELD (36) #define TCR_EL1_AS_FIELD (36)
#define TCR_EL1_TBI0_FIELD (37) #define TCR_EL1_TBI0_FIELD (37)
#define TCR_EL1_TBI1_FIELD (38) #define TCR_EL1_TBI1_FIELD (38)
#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD) #define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD) #define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD) #define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD) #define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD) #define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD) #define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD) #define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD) #define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD) #define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD) #define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD) #define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD) #define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD) #define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD) #define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD) #define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD) #define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD) #define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
#define TCR_EL23_T0SZ_FIELD (0)
#define TCR_EL23_IRGN0_FIELD (8)
#define TCR_EL23_ORGN0_FIELD (10)
#define TCR_EL23_SH0_FIELD (12)
#define TCR_EL23_TG0_FIELD (14)
#define TCR_EL23_PS_FIELD (16)
#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
#define TCR_EL23_T0SZ_FIELD (0) #define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
#define TCR_EL23_IRGN0_FIELD (8) #define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
#define TCR_EL23_ORGN0_FIELD (10) #define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
#define TCR_EL23_SH0_FIELD (12) #define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
#define TCR_EL23_TG0_FIELD (14)
#define TCR_EL23_PS_FIELD (16)
#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10) #define TCR_SH_NON_SHAREABLE (0x0UL << 12)
#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10) #define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10) #define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8) #define TCR_PASZ_32BITS_4GB (0x0UL)
#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8) #define TCR_PASZ_36BITS_64GB (0x1UL)
#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8) #define TCR_PASZ_40BITS_1TB (0x2UL)
#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8) #define TCR_PASZ_42BITS_4TB (0x3UL)
#define TCR_PASZ_44BITS_16TB (0x4UL)
#define TCR_SH_NON_SHAREABLE (0x0UL << 12) #define TCR_PASZ_48BITS_256TB (0x5UL)
#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
#define TCR_PASZ_32BITS_4GB (0x0UL)
#define TCR_PASZ_36BITS_64GB (0x1UL)
#define TCR_PASZ_40BITS_1TB (0x2UL)
#define TCR_PASZ_42BITS_4TB (0x3UL)
#define TCR_PASZ_44BITS_16TB (0x4UL)
#define TCR_PASZ_48BITS_256TB (0x5UL)
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
// Virtual address range for 512GB of virtual space sets T*SZ to 25 // Virtual address range for 512GB of virtual space sets T*SZ to 25
#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a) #define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
// Uses LPAE Page Table format // Uses LPAE Page Table format
#endif // AARCH64_MMU_H_ #endif // AARCH64_MMU_H_

8
ArmPkg/Include/Chipset/ArmCortexA5x.h
View File

@ -12,7 +12,7 @@
// //
// Cortex A5x feature bit definitions // Cortex A5x feature bit definitions
// //
#define A5X_FEATURE_SMP (1 << 6) #define A5X_FEATURE_SMP (1 << 6)
// //
// Helper functions to access CPU Extended Control Register // Helper functions to access CPU Extended Control Register
@ -26,19 +26,19 @@ ArmReadCpuExCr (
VOID VOID
EFIAPI EFIAPI
ArmWriteCpuExCr ( ArmWriteCpuExCr (
IN UINT64 Val IN UINT64 Val
); );
VOID VOID
EFIAPI EFIAPI
ArmSetCpuExCrBit ( ArmSetCpuExCrBit (
IN UINT64 Bits IN UINT64 Bits
); );
VOID VOID
EFIAPI EFIAPI
ArmUnsetCpuExCrBit ( ArmUnsetCpuExCrBit (
IN UINT64 Bits IN UINT64 Bits
); );
#endif // ARM_CORTEX_A5X_H_ #endif // ARM_CORTEX_A5X_H_

32
ArmPkg/Include/Chipset/ArmCortexA9.h
View File

@ -26,28 +26,27 @@
// //
// Cortex A9 Watchdog // Cortex A9 Watchdog
// //
#define ARM_A9_WATCHDOG_REGION 0x600 #define ARM_A9_WATCHDOG_REGION 0x600
#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20 #define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20
#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28 #define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28
#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3) #define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)
#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3) #define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)
#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1) #define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)
#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1) #define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)
#define ARM_A9_WATCHDOG_ENABLE 1 #define ARM_A9_WATCHDOG_ENABLE 1
// //
// SCU register offsets & masks // SCU register offsets & masks
// //
#define A9_SCU_CONTROL_OFFSET 0x0 #define A9_SCU_CONTROL_OFFSET 0x0
#define A9_SCU_CONFIG_OFFSET 0x4 #define A9_SCU_CONFIG_OFFSET 0x4
#define A9_SCU_INVALL_OFFSET 0xC #define A9_SCU_INVALL_OFFSET 0xC
#define A9_SCU_FILT_START_OFFSET 0x40 #define A9_SCU_FILT_START_OFFSET 0x40
#define A9_SCU_FILT_END_OFFSET 0x44 #define A9_SCU_FILT_END_OFFSET 0x44
#define A9_SCU_SACR_OFFSET 0x50 #define A9_SCU_SACR_OFFSET 0x50
#define A9_SCU_SSACR_OFFSET 0x54 #define A9_SCU_SSACR_OFFSET 0x54
UINTN UINTN
EFIAPI EFIAPI
@ -56,4 +55,3 @@ ArmGetScuBaseAddress (
); );
#endif // ARM_CORTEX_A9_H_ #endif // ARM_CORTEX_A9_H_

87
ArmPkg/Include/Chipset/ArmV7.h
View File

@ -13,19 +13,19 @@
#include <Chipset/ArmV7Mmu.h> #include <Chipset/ArmV7Mmu.h>
// ARM Interrupt ID in Exception Table // ARM Interrupt ID in Exception Table
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
// ID_PFR1 - ARM Processor Feature Register 1 definitions // ID_PFR1 - ARM Processor Feature Register 1 definitions
#define ARM_PFR1_SEC (0xFUL << 4) #define ARM_PFR1_SEC (0xFUL << 4)
#define ARM_PFR1_TIMER (0xFUL << 16) #define ARM_PFR1_TIMER (0xFUL << 16)
#define ARM_PFR1_GIC (0xFUL << 28) #define ARM_PFR1_GIC (0xFUL << 28)
// Domain Access Control Register // Domain Access Control Register
#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
// CPSR - Coprocessor Status Register definitions // CPSR - Coprocessor Status Register definitions
#define CPSR_MODE_USER 0x10 #define CPSR_MODE_USER 0x10
@ -41,48 +41,47 @@
#define CPSR_IRQ (1 << 7) #define CPSR_IRQ (1 << 7)
#define CPSR_FIQ (1 << 6) #define CPSR_FIQ (1 << 6)
// CPACR - Coprocessor Access Control Register definitions // CPACR - Coprocessor Access Control Register definitions
#define CPACR_CP_DENIED(cp) 0x00 #define CPACR_CP_DENIED(cp) 0x00
#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF) #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF) #define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
#define CPACR_ASEDIS (1 << 31) #define CPACR_ASEDIS (1 << 31)
#define CPACR_D32DIS (1 << 30) #define CPACR_D32DIS (1 << 30)
#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF #define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
// NSACR - Non-Secure Access Control Register definitions // NSACR - Non-Secure Access Control Register definitions
#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF) #define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
#define NSACR_NSD32DIS (1 << 14) #define NSACR_NSD32DIS (1 << 14)
#define NSACR_NSASEDIS (1 << 15) #define NSACR_NSASEDIS (1 << 15)
#define NSACR_PLE (1 << 16) #define NSACR_PLE (1 << 16)
#define NSACR_TL (1 << 17) #define NSACR_TL (1 << 17)
#define NSACR_NS_SMP (1 << 18) #define NSACR_NS_SMP (1 << 18)
#define NSACR_RFR (1 << 19) #define NSACR_RFR (1 << 19)
// SCR - Secure Configuration Register definitions // SCR - Secure Configuration Register definitions
#define SCR_NS (1 << 0) #define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1) #define SCR_IRQ (1 << 1)
#define SCR_FIQ (1 << 2) #define SCR_FIQ (1 << 2)
#define SCR_EA (1 << 3) #define SCR_EA (1 << 3)
#define SCR_FW (1 << 4) #define SCR_FW (1 << 4)
#define SCR_AW (1 << 5) #define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions // MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4 #define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF #define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMV8 0xD0F #define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03 #define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07 #define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F #define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A12 0xC0D #define ARM_CPU_TYPE_A12 0xC0D
#define ARM_CPU_TYPE_A9 0xC09 #define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A7 0xC07 #define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05 #define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) ) #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF)) #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1) #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
VOID VOID
EFIAPI EFIAPI
@ -105,7 +104,7 @@ ArmReadTpidrurw (
VOID VOID
EFIAPI EFIAPI
ArmWriteTpidrurw ( ArmWriteTpidrurw (
UINTN Value UINTN Value
); );
UINT32 UINT32
@ -117,7 +116,7 @@ ArmReadNsacr (
VOID VOID
EFIAPI EFIAPI
ArmWriteNsacr ( ArmWriteNsacr (
IN UINT32 Nsacr IN UINT32 Nsacr
); );
#endif // ARM_V7_H_ #endif // ARM_V7_H_

257
ArmPkg/Include/Chipset/ArmV7Mmu.h
View File

@ -9,183 +9,182 @@
#ifndef ARMV7_MMU_H_ #ifndef ARMV7_MMU_H_
#define ARMV7_MMU_H_ #define ARMV7_MMU_H_
#define TTBR_NOT_OUTER_SHAREABLE BIT5 #define TTBR_NOT_OUTER_SHAREABLE BIT5
#define TTBR_RGN_OUTER_NON_CACHEABLE 0 #define TTBR_RGN_OUTER_NON_CACHEABLE 0
#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3 #define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4 #define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4) #define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
#define TTBR_SHAREABLE BIT1 #define TTBR_SHAREABLE BIT1
#define TTBR_NON_SHAREABLE 0 #define TTBR_NON_SHAREABLE 0
#define TTBR_INNER_CACHEABLE BIT0 #define TTBR_INNER_CACHEABLE BIT0
#define TTBR_INNER_NON_CACHEABLE 0 #define TTBR_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_NON_CACHEABLE 0 #define TTBR_RGN_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6 #define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
#define TTBR_RGN_INNER_WRITE_THROUGH BIT0 #define TTBR_RGN_INNER_WRITE_THROUGH BIT0
#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6) #define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE) #define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE) #define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE ) #define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE) #define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE) #define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE) #define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE ) #define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE) #define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
#define TRANSLATION_TABLE_SECTION_COUNT 4096
#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
#define TRANSLATION_TABLE_SECTION_COUNT 4096 #define TRANSLATION_TABLE_PAGE_COUNT 256
#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT) #define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT) #define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1) #define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
#define TRANSLATION_TABLE_PAGE_COUNT 256 #define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
// Translation table descriptor types // Translation table descriptor types
#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0)) #define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0) #define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0) #define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0)) #define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0)) #define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE) #define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
// Translation table descriptor types // Translation table descriptor types
#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0) #define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0) #define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0) #define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0) #define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0) #define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
// Section descriptor definitions // Section descriptor definitions
#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000) #define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19) #define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NS (1UL << 19) #define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17) #define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17) #define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17) #define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11) #define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11) #define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11) #define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16) #define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16) #define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16) #define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10) #define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10) #define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10) #define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10)) #define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10)) #define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10)) #define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10)) #define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10)) #define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10)) #define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10)) #define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4)) #define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4)) #define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4)) #define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4)) #define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4)) #define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4)) #define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4)) #define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4) #define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0) #define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15) #define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3) #define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000) #define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3) #define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2)) #define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2)) #define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK) #define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK) #define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK) #define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \ #define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc, IsLargePage) ((IsLargePage)?\
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \ ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK)) ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK))
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \ #define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \ (((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2))))) (((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK) #define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \ #define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \ (((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2))))) (((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))
#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \ #define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \ TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \
TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)
#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \ #define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \ TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)
#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5) #define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5) #define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000) #define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00) #define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK) #define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20 #define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000) #define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000) #define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) #define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12 #define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ #define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_SHARED | \ TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC) TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ #define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_SHARED | \ TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC) TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ #define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
@ -193,7 +192,7 @@
TT_DESCRIPTOR_SECTION_AP_RW_RW | \ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_XN_MASK | \ TT_DESCRIPTOR_SECTION_XN_MASK | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE) TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ #define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
@ -201,33 +200,33 @@
TT_DESCRIPTOR_SECTION_AP_RW_RW | \ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE) TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ #define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \ TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \ TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC) TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ #define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \ TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \ TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC) TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ #define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \ TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_XN_MASK | \ TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE) TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ #define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \ TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE) TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
// First Level Descriptors // First Level Descriptors
typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR; typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
// Second Level Descriptors // Second Level Descriptors
typedef UINT32 ARM_PAGE_TABLE_ENTRY; typedef UINT32 ARM_PAGE_TABLE_ENTRY;
UINT32 UINT32
ConvertSectionAttributesToPageAttributes ( ConvertSectionAttributesToPageAttributes (

63
ArmPkg/Include/Guid/ArmMpCoreInfo.h
View File

@ -9,52 +9,51 @@
#ifndef ARM_MP_CORE_INFO_GUID_H_ #ifndef ARM_MP_CORE_INFO_GUID_H_
#define ARM_MP_CORE_INFO_GUID_H_ #define ARM_MP_CORE_INFO_GUID_H_
#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04 #define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
#define SCU_CONFIG_REG_OFFSET 0x04 #define SCU_CONFIG_REG_OFFSET 0x04
#define MPIDR_U_BIT_MASK 0x40000000 #define MPIDR_U_BIT_MASK 0x40000000
typedef struct { typedef struct {
UINT32 ClusterId; UINT32 ClusterId;
UINT32 CoreId; UINT32 CoreId;
// MP Core Mailbox // MP Core Mailbox
EFI_PHYSICAL_ADDRESS MailboxSetAddress; EFI_PHYSICAL_ADDRESS MailboxSetAddress;
EFI_PHYSICAL_ADDRESS MailboxGetAddress; EFI_PHYSICAL_ADDRESS MailboxGetAddress;
EFI_PHYSICAL_ADDRESS MailboxClearAddress; EFI_PHYSICAL_ADDRESS MailboxClearAddress;
UINT64 MailboxClearValue; UINT64 MailboxClearValue;
} ARM_CORE_INFO; } ARM_CORE_INFO;
typedef struct{ typedef struct {
UINT64 Signature; UINT64 Signature;
UINT32 Length; UINT32 Length;
UINT32 Revision; UINT32 Revision;
UINT64 OemId; UINT64 OemId;
UINT64 OemTableId; UINT64 OemTableId;
UINTN OemRevision; UINTN OemRevision;
UINTN CreatorId; UINTN CreatorId;
UINTN CreatorRevision; UINTN CreatorRevision;
EFI_GUID Identifier; EFI_GUID Identifier;
UINTN DataLen; UINTN DataLen;
} ARM_PROCESSOR_TABLE_HEADER; } ARM_PROCESSOR_TABLE_HEADER;
typedef struct { typedef struct {
ARM_PROCESSOR_TABLE_HEADER Header; ARM_PROCESSOR_TABLE_HEADER Header;
UINTN NumberOfEntries; UINTN NumberOfEntries;
ARM_CORE_INFO *ArmCpus; ARM_CORE_INFO *ArmCpus;
} ARM_PROCESSOR_TABLE; } ARM_PROCESSOR_TABLE;
#define ARM_MP_CORE_INFO_GUID \ #define ARM_MP_CORE_INFO_GUID \
{ 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} } { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E') #define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0 #define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000// 1.0
#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ') #define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L') #define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001 #define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5 #define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001 #define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
extern EFI_GUID gArmMpCoreInfoGuid; extern EFI_GUID gArmMpCoreInfoGuid;
#endif /* ARM_MP_CORE_INFO_GUID_H_ */ #endif /* ARM_MP_CORE_INFO_GUID_H_ */

83
ArmPkg/Include/IndustryStandard/ArmCache.h
View File

@ -13,22 +13,21 @@
// The ARM Architecture Reference Manual for ARMv8-A defines up // The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7. // to 7 levels of cache, L1 through L7.
#define MAX_ARM_CACHE_LEVEL 7 #define MAX_ARM_CACHE_LEVEL 7
/// Defines the structure of the CSSELR (Cache Size Selection) register /// Defines the structure of the CSSELR (Cache Size Selection) register
typedef union { typedef union {
struct { struct {
UINT32 InD :1; ///< Instruction not Data bit UINT32 InD : 1; ///< Instruction not Data bit
UINT32 Level :3; ///< Cache level (zero based) UINT32 Level : 3; ///< Cache level (zero based)
UINT32 TnD :1; ///< Allocation not Data bit UINT32 TnD : 1; ///< Allocation not Data bit
UINT32 Reserved :27; ///< Reserved, RES0 UINT32 Reserved : 27; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register } Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value UINT32 Data; ///< The entire 32-bit value
} CSSELR_DATA; } CSSELR_DATA;
/// The cache type values for the InD field of the CSSELR register /// The cache type values for the InD field of the CSSELR register
typedef enum typedef enum {
{
/// Select the data or unified cache /// Select the data or unified cache
CsselrCacheTypeDataOrUnified = 0, CsselrCacheTypeDataOrUnified = 0,
/// Select the instruction cache /// Select the instruction cache
@ -39,35 +38,35 @@ typedef enum
/// Defines the structure of the CCSIDR (Current Cache Size ID) register /// Defines the structure of the CCSIDR (Current Cache Size ID) register
typedef union { typedef union {
struct { struct {
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :10; ///< Associativity - 1 UINT64 Associativity : 10; ///< Associativity - 1
UINT64 NumSets :15; ///< Number of sets in the cache -1 UINT64 NumSets : 15; ///< Number of sets in the cache -1
UINT64 Unknown :4; ///< Reserved, UNKNOWN UINT64 Unknown : 4; ///< Reserved, UNKNOWN
UINT64 Reserved :32; ///< Reserved, RES0 UINT64 Reserved : 32; ///< Reserved, RES0
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
struct { struct {
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :21; ///< Associativity - 1 UINT64 Associativity : 21; ///< Associativity - 1
UINT64 Reserved1 :8; ///< Reserved, RES0 UINT64 Reserved1 : 8; ///< Reserved, RES0
UINT64 NumSets :24; ///< Number of sets in the cache -1 UINT64 NumSets : 24; ///< Number of sets in the cache -1
UINT64 Reserved2 :8; ///< Reserved, RES0 UINT64 Reserved2 : 8; ///< Reserved, RES0
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported. } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
struct { struct {
UINT64 LineSize : 3; UINT64 LineSize : 3;
UINT64 Associativity : 21; UINT64 Associativity : 21;
UINT64 Reserved : 8; UINT64 Reserved : 8;
UINT64 Unallocated : 32; UINT64 Unallocated : 32;
} BitsCcidxAA32; } BitsCcidxAA32;
UINT64 Data; ///< The entire 64-bit value UINT64 Data; ///< The entire 64-bit value
} CCSIDR_DATA; } CCSIDR_DATA;
/// Defines the structure of the AARCH32 CCSIDR2 register. /// Defines the structure of the AARCH32 CCSIDR2 register.
typedef union { typedef union {
struct { struct {
UINT32 NumSets :24; ///< Number of sets in the cache - 1 UINT32 NumSets : 24; ///< Number of sets in the cache - 1
UINT32 Reserved :8; ///< Reserved, RES0 UINT32 Reserved : 8; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register } Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value UINT32 Data; ///< The entire 32-bit value
} CCSIDR2_DATA; } CCSIDR2_DATA;
/** Defines the structure of the CLIDR (Cache Level ID) register. /** Defines the structure of the CLIDR (Cache Level ID) register.
@ -77,19 +76,19 @@ typedef union {
**/ **/
typedef union { typedef union {
struct { struct {
UINT32 Ctype1 : 3; ///< Level 1 cache type UINT32 Ctype1 : 3; ///< Level 1 cache type
UINT32 Ctype2 : 3; ///< Level 2 cache type UINT32 Ctype2 : 3; ///< Level 2 cache type
UINT32 Ctype3 : 3; ///< Level 3 cache type UINT32 Ctype3 : 3; ///< Level 3 cache type
UINT32 Ctype4 : 3; ///< Level 4 cache type UINT32 Ctype4 : 3; ///< Level 4 cache type
UINT32 Ctype5 : 3; ///< Level 5 cache type UINT32 Ctype5 : 3; ///< Level 5 cache type
UINT32 Ctype6 : 3; ///< Level 6 cache type UINT32 Ctype6 : 3; ///< Level 6 cache type
UINT32 Ctype7 : 3; ///< Level 7 cache type UINT32 Ctype7 : 3; ///< Level 7 cache type
UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
UINT32 LoC : 3; ///< Level of Coherency UINT32 LoC : 3; ///< Level of Coherency
UINT32 LoUU : 3; ///< Level of Unification Uniprocessor UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
UINT32 Icb : 3; ///< Inner Cache Boundary UINT32 Icb : 3; ///< Inner Cache Boundary
} Bits; ///< Bitfield definition of the register } Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value UINT32 Data; ///< The entire 32-bit value
} CLIDR_DATA; } CLIDR_DATA;
/// The cache types reported in the CLIDR register. /// The cache types reported in the CLIDR register.
@ -107,6 +106,6 @@ typedef enum {
ClidrCacheTypeMax ClidrCacheTypeMax
} CLIDR_CACHE_TYPE; } CLIDR_CACHE_TYPE;
#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111) #define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
#endif /* ARM_CACHE_H_ */ #endif /* ARM_CACHE_H_ */

42
ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
View File

@ -16,34 +16,34 @@
#ifndef ARM_FFA_SVC_H_ #ifndef ARM_FFA_SVC_H_
#define ARM_FFA_SVC_H_ #define ARM_FFA_SVC_H_
#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063 #define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
/* Generic IDs when using AArch32 or AArch64 execution state */ /* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64 #ifdef MDE_CPU_AARCH64
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
#endif #endif
#ifdef MDE_CPU_ARM #ifdef MDE_CPU_ARM
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
#endif #endif
#define SPM_MAJOR_VERSION_FFA 1 #define SPM_MAJOR_VERSION_FFA 1
#define SPM_MINOR_VERSION_FFA 0 #define SPM_MINOR_VERSION_FFA 0
#define ARM_FFA_SPM_RET_SUCCESS 0 #define ARM_FFA_SPM_RET_SUCCESS 0
#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1 #define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2 #define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
#define ARM_FFA_SPM_RET_NO_MEMORY -3 #define ARM_FFA_SPM_RET_NO_MEMORY -3
#define ARM_FFA_SPM_RET_BUSY -4 #define ARM_FFA_SPM_RET_BUSY -4
#define ARM_FFA_SPM_RET_INTERRUPTED -5 #define ARM_FFA_SPM_RET_INTERRUPTED -5
#define ARM_FFA_SPM_RET_DENIED -6 #define ARM_FFA_SPM_RET_DENIED -6
#define ARM_FFA_SPM_RET_RETRY -7 #define ARM_FFA_SPM_RET_RETRY -7
#define ARM_FFA_SPM_RET_ABORTED -8 #define ARM_FFA_SPM_RET_ABORTED -8
// For now, the destination id to be used in the FF-A calls // For now, the destination id to be used in the FF-A calls
// is being hard-coded. Subsequently, support will be added // is being hard-coded. Subsequently, support will be added
@ -51,6 +51,6 @@
// This is the endpoint id used by the optee os's implementation // This is the endpoint id used by the optee os's implementation
// of the spmc. // of the spmc.
// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66 // https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
#define ARM_FFA_DESTINATION_ENDPOINT_ID 3 #define ARM_FFA_DESTINATION_ENDPOINT_ID 3
#endif // ARM_FFA_SVC_H_ #endif // ARM_FFA_SVC_H_

54
ArmPkg/Include/IndustryStandard/ArmMmSvc.h
View File

@ -14,49 +14,49 @@
* delegated events and request the Secure partition manager to perform * delegated events and request the Secure partition manager to perform
* privileged operations on its behalf. * privileged operations on its behalf.
*/ */
#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060 #define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061 #define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061 #define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
/* Generic IDs when using AArch32 or AArch64 execution state */ /* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64 #ifdef MDE_CPU_AARCH64
#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 #define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
#endif #endif
#ifdef MDE_CPU_ARM #ifdef MDE_CPU_ARM
#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 #define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
#endif #endif
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3 #define SET_MEM_ATTR_DATA_PERM_MASK 0x3
#define SET_MEM_ATTR_DATA_PERM_SHIFT 0 #define SET_MEM_ATTR_DATA_PERM_SHIFT 0
#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0 #define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
#define SET_MEM_ATTR_DATA_PERM_RW 1 #define SET_MEM_ATTR_DATA_PERM_RW 1
#define SET_MEM_ATTR_DATA_PERM_RO 3 #define SET_MEM_ATTR_DATA_PERM_RO 3
#define SET_MEM_ATTR_CODE_PERM_MASK 0x1 #define SET_MEM_ATTR_CODE_PERM_MASK 0x1
#define SET_MEM_ATTR_CODE_PERM_SHIFT 2 #define SET_MEM_ATTR_CODE_PERM_SHIFT 2
#define SET_MEM_ATTR_CODE_PERM_X 0 #define SET_MEM_ATTR_CODE_PERM_X 0
#define SET_MEM_ATTR_CODE_PERM_XN 1 #define SET_MEM_ATTR_CODE_PERM_XN 1
#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \ #define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \
((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \ ((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
(( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT)) (( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
/* MM SVC Return error codes */ /* MM SVC Return error codes */
#define ARM_SVC_SPM_RET_SUCCESS 0 #define ARM_SVC_SPM_RET_SUCCESS 0
#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1 #define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
#define ARM_SVC_SPM_RET_INVALID_PARAMS -2 #define ARM_SVC_SPM_RET_INVALID_PARAMS -2
#define ARM_SVC_SPM_RET_DENIED -3 #define ARM_SVC_SPM_RET_DENIED -3
#define ARM_SVC_SPM_RET_NO_MEMORY -5 #define ARM_SVC_SPM_RET_NO_MEMORY -5
#define SPM_MAJOR_VERSION 0 #define SPM_MAJOR_VERSION 0
#define SPM_MINOR_VERSION 1 #define SPM_MINOR_VERSION 1
#endif // ARM_MM_SVC_H_ #endif // ARM_MM_SVC_H_

88
ArmPkg/Include/IndustryStandard/ArmStdSmc.h
View File

@ -17,64 +17,64 @@
* SMC function IDs for Standard Service queries * SMC function IDs for Standard Service queries
*/ */
#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00 #define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
#define ARM_SMC_ID_STD_UID 0x8400ff01 #define ARM_SMC_ID_STD_UID 0x8400ff01
/* 0x8400ff02 is reserved */ /* 0x8400ff02 is reserved */
#define ARM_SMC_ID_STD_REVISION 0x8400ff03 #define ARM_SMC_ID_STD_REVISION 0x8400ff03
/* /*
* The 'Standard Service Call UID' is supposed to return the Standard * The 'Standard Service Call UID' is supposed to return the Standard
* Service UUID. This is a 128-bit value. * Service UUID. This is a 128-bit value.
*/ */
#define ARM_SMC_STD_UUID0 0x108d905b #define ARM_SMC_STD_UUID0 0x108d905b
#define ARM_SMC_STD_UUID1 0x47e8f863 #define ARM_SMC_STD_UUID1 0x47e8f863
#define ARM_SMC_STD_UUID2 0xfbc02dae #define ARM_SMC_STD_UUID2 0xfbc02dae
#define ARM_SMC_STD_UUID3 0xe2f64156 #define ARM_SMC_STD_UUID3 0xe2f64156
/* /*
* ARM Standard Service Calls revision numbers * ARM Standard Service Calls revision numbers
* The current revision is: 0.1 * The current revision is: 0.1
*/ */
#define ARM_SMC_STD_REVISION_MAJOR 0x0 #define ARM_SMC_STD_REVISION_MAJOR 0x0
#define ARM_SMC_STD_REVISION_MINOR 0x1 #define ARM_SMC_STD_REVISION_MINOR 0x1
/* /*
* Management Mode (MM) calls cover a subset of the Standard Service Call range. * Management Mode (MM) calls cover a subset of the Standard Service Call range.
* The list below is not exhaustive. * The list below is not exhaustive.
*/ */
#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040 #define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040 #define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
// Request service from secure standalone MM environment // Request service from secure standalone MM environment
#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
/* Generic ID when using AArch32 or AArch64 execution state */ /* Generic ID when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64 #ifdef MDE_CPU_AARCH64
#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64 #define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
#endif #endif
#ifdef MDE_CPU_ARM #ifdef MDE_CPU_ARM
#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32 #define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
#endif #endif
/* MM return error codes */ /* MM return error codes */
#define ARM_SMC_MM_RET_SUCCESS 0 #define ARM_SMC_MM_RET_SUCCESS 0
#define ARM_SMC_MM_RET_NOT_SUPPORTED -1 #define ARM_SMC_MM_RET_NOT_SUPPORTED -1
#define ARM_SMC_MM_RET_INVALID_PARAMS -2 #define ARM_SMC_MM_RET_INVALID_PARAMS -2
#define ARM_SMC_MM_RET_DENIED -3 #define ARM_SMC_MM_RET_DENIED -3
#define ARM_SMC_MM_RET_NO_MEMORY -4 #define ARM_SMC_MM_RET_NO_MEMORY -4
// ARM Architecture Calls // ARM Architecture Calls
#define SMCCC_VERSION 0x80000000 #define SMCCC_VERSION 0x80000000
#define SMCCC_ARCH_FEATURES 0x80000001 #define SMCCC_ARCH_FEATURES 0x80000001
#define SMCCC_ARCH_SOC_ID 0x80000002 #define SMCCC_ARCH_SOC_ID 0x80000002
#define SMCCC_ARCH_WORKAROUND_1 0x80008000 #define SMCCC_ARCH_WORKAROUND_1 0x80008000
#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF #define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
#define SMC_ARCH_CALL_SUCCESS 0 #define SMC_ARCH_CALL_SUCCESS 0
#define SMC_ARCH_CALL_NOT_SUPPORTED -1 #define SMC_ARCH_CALL_NOT_SUPPORTED -1
#define SMC_ARCH_CALL_NOT_REQUIRED -2 #define SMC_ARCH_CALL_NOT_REQUIRED -2
#define SMC_ARCH_CALL_INVALID_PARAMETER -3 #define SMC_ARCH_CALL_INVALID_PARAMETER -3
/* /*
* Power State Coordination Interface (PSCI) calls cover a subset of the * Power State Coordination Interface (PSCI) calls cover a subset of the
@ -101,15 +101,15 @@
((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR) ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
/* PSCI return error codes */ /* PSCI return error codes */
#define ARM_SMC_PSCI_RET_SUCCESS 0 #define ARM_SMC_PSCI_RET_SUCCESS 0
#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1 #define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2 #define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
#define ARM_SMC_PSCI_RET_DENIED -3 #define ARM_SMC_PSCI_RET_DENIED -3
#define ARM_SMC_PSCI_RET_ALREADY_ON -4 #define ARM_SMC_PSCI_RET_ALREADY_ON -4
#define ARM_SMC_PSCI_RET_ON_PENDING -5 #define ARM_SMC_PSCI_RET_ON_PENDING -5
#define ARM_SMC_PSCI_RET_INTERN_FAIL -6 #define ARM_SMC_PSCI_RET_INTERN_FAIL -6
#define ARM_SMC_PSCI_RET_NOT_PRESENT -7 #define ARM_SMC_PSCI_RET_NOT_PRESENT -7
#define ARM_SMC_PSCI_RET_DISABLED -8 #define ARM_SMC_PSCI_RET_DISABLED -8
#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \ #define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF)) ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
@ -120,10 +120,10 @@
#define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF) #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)
#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF) #define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1
@ -132,9 +132,9 @@
/* /*
* SMC function IDs for Trusted OS Service queries * SMC function IDs for Trusted OS Service queries
*/ */
#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00 #define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
#define ARM_SMC_ID_TOS_UID 0xbf00ff01 #define ARM_SMC_ID_TOS_UID 0xbf00ff01
/* 0xbf00ff02 is reserved */ /* 0xbf00ff02 is reserved */
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03 #define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
#endif // ARM_STD_SMC_H_ #endif // ARM_STD_SMC_H_

12
ArmPkg/Include/Library/ArmDisassemblerLib.h
View File

@ -26,12 +26,12 @@
**/ **/
VOID VOID
DisassembleInstruction ( DisassembleInstruction (
IN UINT8 **OpCodePtr, IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb, IN BOOLEAN Thumb,
IN BOOLEAN Extended, IN BOOLEAN Extended,
IN OUT UINT32 *ItBlock, IN OUT UINT32 *ItBlock,
OUT CHAR8 *Buf, OUT CHAR8 *Buf,
OUT UINTN Size OUT UINTN Size
); );
#endif // ARM_DISASSEMBLER_LIB_H_ #endif // ARM_DISASSEMBLER_LIB_H_

6
ArmPkg/Include/Library/ArmGenericTimerCounterLib.h
View File

@ -43,7 +43,7 @@ ArmGenericTimerGetTimerFreq (
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetTimerVal ( ArmGenericTimerSetTimerVal (
IN UINTN Value IN UINTN Value
); );
UINTN UINTN
@ -67,7 +67,7 @@ ArmGenericTimerGetTimerCtrlReg (
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetTimerCtrlReg ( ArmGenericTimerSetTimerCtrlReg (
UINTN Value UINTN Value
); );
UINT64 UINT64
@ -79,7 +79,7 @@ ArmGenericTimerGetCompareVal (
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetCompareVal ( ArmGenericTimerSetCompareVal (
IN UINT64 Value IN UINT64 Value
); );
#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_ #endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_

1
ArmPkg/Include/Library/ArmGicArchLib.h
View File

@ -17,7 +17,6 @@ typedef enum {
ARM_GIC_ARCH_REVISION_3 ARM_GIC_ARCH_REVISION_3
} ARM_GIC_ARCH_REVISION; } ARM_GIC_ARCH_REVISION;
ARM_GIC_ARCH_REVISION ARM_GIC_ARCH_REVISION
EFIAPI EFIAPI
ArmGicGetSupportedArchRevision ( ArmGicGetSupportedArchRevision (

207
ArmPkg/Include/Library/ArmGicLib.h
View File

@ -12,36 +12,36 @@
#include <Library/ArmGicArchLib.h> #include <Library/ArmGicArchLib.h>
// GIC Distributor // GIC Distributor
#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
// Each reg base below repeats for Number of interrupts / 4 (see GIC spec) // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
#define ARM_GIC_ICDABR 0x300 // Active Bit Registers #define ARM_GIC_ICDABR 0x300 // Active Bit Registers
// Each reg base below repeats for Number of interrupts / 4 // Each reg base below repeats for Number of interrupts / 4
#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
// Each reg base below repeats for Number of interrupts // Each reg base below repeats for Number of interrupts
#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
// just one of these // just one of these
#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
// GICv3 specific registers // GICv3 specific registers
#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
// GICD_CTLR bits // GICD_CTLR bits
#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS) #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
// GICD_ICDICFR bits // GICD_ICDICFR bits
#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register #define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
@ -52,125 +52,124 @@
#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt #define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt #define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
// GIC Redistributor // GIC Redistributor
#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB #define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB #define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
// GIC Redistributor Control frame // GIC Redistributor Control frame
#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register #define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
// GIC Redistributor TYPER bit assignments // GIC Redistributor TYPER bit assignments
#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs #define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs #define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs #define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series #define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group #define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
// Selection Support // Selection Support
#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number #define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity #define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity #define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \ #define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
ARM_GICR_TYPER_AFFINITY) >> 32) ARM_GICR_TYPER_AFFINITY) >> 32)
// GIC SGI & PPI Redistributor frame // GIC SGI & PPI Redistributor frame
#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
// GIC Cpu interface // GIC Cpu interface
#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
#define ARM_GIC_ICCBPR 0x08 // Binary Point Register #define ARM_GIC_ICCBPR 0x08 // Binary Point Register
#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
#define ARM_GIC_ICCRPR 0x14 // Running Priority Register #define ARM_GIC_ICCRPR 0x14 // Running Priority Register
#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
#define ARM_GIC_ICCIIDR 0xFC // Identification Register #define ARM_GIC_ICCIIDR 0xFC // Identification Register
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2 #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
// Bit-masks to configure the CPU Interface Control register // Bit-masks to configure the CPU Interface Control register
#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01 #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
#define ARM_GIC_ICCICR_ENABLE_NS 0x02 #define ARM_GIC_ICCICR_ENABLE_NS 0x02
#define ARM_GIC_ICCICR_ACK_CTL 0x04 #define ARM_GIC_ICCICR_ACK_CTL 0x04
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
#define ARM_GIC_ICCICR_USE_SBPR 0x10 #define ARM_GIC_ICCICR_USE_SBPR 0x10
// Bit Mask for GICC_IIDR // Bit Mask for GICC_IIDR
#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF) #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF) #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF) #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF) #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
// Bit Mask for // Bit Mask for
#define ARM_GIC_ICCIAR_ACKINTID 0x3FF #define ARM_GIC_ICCIAR_ACKINTID 0x3FF
UINTN UINTN
EFIAPI EFIAPI
ArmGicGetInterfaceIdentification ( ArmGicGetInterfaceIdentification (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
); );
// GIC Secure interfaces // GIC Secure interfaces
VOID VOID
EFIAPI EFIAPI
ArmGicSetupNonSecure ( ArmGicSetupNonSecure (
IN UINTN MpId, IN UINTN MpId,
IN INTN GicDistributorBase, IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
); );
VOID VOID
EFIAPI EFIAPI
ArmGicSetSecureInterrupts ( ArmGicSetSecureInterrupts (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN* GicSecureInterruptMask, IN UINTN *GicSecureInterruptMask,
IN UINTN GicSecureInterruptMaskSize IN UINTN GicSecureInterruptMaskSize
); );
VOID VOID
EFIAPI EFIAPI
ArmGicEnableInterruptInterface ( ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
); );
VOID VOID
EFIAPI EFIAPI
ArmGicDisableInterruptInterface ( ArmGicDisableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
); );
VOID VOID
EFIAPI EFIAPI
ArmGicEnableDistributor ( ArmGicEnableDistributor (
IN INTN GicDistributorBase IN INTN GicDistributorBase
); );
VOID VOID
EFIAPI EFIAPI
ArmGicDisableDistributor ( ArmGicDisableDistributor (
IN INTN GicDistributorBase IN INTN GicDistributorBase
); );
UINTN UINTN
EFIAPI EFIAPI
ArmGicGetMaxNumInterrupts ( ArmGicGetMaxNumInterrupts (
IN INTN GicDistributorBase IN INTN GicDistributorBase
); );
VOID VOID
EFIAPI EFIAPI
ArmGicSendSgiTo ( ArmGicSendSgiTo (
IN INTN GicDistributorBase, IN INTN GicDistributorBase,
IN INTN TargetListFilter, IN INTN TargetListFilter,
IN INTN CPUTargetList, IN INTN CPUTargetList,
IN INTN SgiId IN INTN SgiId
); );
/* /*
@ -190,55 +189,55 @@ ArmGicSendSgiTo (
UINTN UINTN
EFIAPI EFIAPI
ArmGicAcknowledgeInterrupt ( ArmGicAcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase, IN UINTN GicInterruptInterfaceBase,
OUT UINTN *InterruptId OUT UINTN *InterruptId
); );
VOID VOID
EFIAPI EFIAPI
ArmGicEndOfInterrupt ( ArmGicEndOfInterrupt (
IN UINTN GicInterruptInterfaceBase, IN UINTN GicInterruptInterfaceBase,
IN UINTN Source IN UINTN Source
); );
UINTN UINTN
EFIAPI EFIAPI
ArmGicSetPriorityMask ( ArmGicSetPriorityMask (
IN INTN GicInterruptInterfaceBase, IN INTN GicInterruptInterfaceBase,
IN INTN PriorityMask IN INTN PriorityMask
); );
VOID VOID
EFIAPI EFIAPI
ArmGicSetInterruptPriority ( ArmGicSetInterruptPriority (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN UINTN Source, IN UINTN Source,
IN UINTN Priority IN UINTN Priority
); );
VOID VOID
EFIAPI EFIAPI
ArmGicEnableInterrupt ( ArmGicEnableInterrupt (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN UINTN Source IN UINTN Source
); );
VOID VOID
EFIAPI EFIAPI
ArmGicDisableInterrupt ( ArmGicDisableInterrupt (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN UINTN Source IN UINTN Source
); );
BOOLEAN BOOLEAN
EFIAPI EFIAPI
ArmGicIsInterruptEnabled ( ArmGicIsInterruptEnabled (
IN UINTN GicDistributorBase, IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase, IN UINTN GicRedistributorBase,
IN UINTN Source IN UINTN Source
); );
// GIC revision 2 specific declarations // GIC revision 2 specific declarations
@ -251,41 +250,41 @@ ArmGicIsInterruptEnabled (
VOID VOID
EFIAPI EFIAPI
ArmGicV2SetupNonSecure ( ArmGicV2SetupNonSecure (
IN UINTN MpId, IN UINTN MpId,
IN INTN GicDistributorBase, IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
); );
VOID VOID
EFIAPI EFIAPI
ArmGicV2EnableInterruptInterface ( ArmGicV2EnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
); );
VOID VOID
EFIAPI EFIAPI
ArmGicV2DisableInterruptInterface ( ArmGicV2DisableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
); );
UINTN UINTN
EFIAPI EFIAPI
ArmGicV2AcknowledgeInterrupt ( ArmGicV2AcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase IN UINTN GicInterruptInterfaceBase
); );
VOID VOID
EFIAPI EFIAPI
ArmGicV2EndOfInterrupt ( ArmGicV2EndOfInterrupt (
IN UINTN GicInterruptInterfaceBase, IN UINTN GicInterruptInterfaceBase,
IN UINTN Source IN UINTN Source
); );
// GIC revision 3 specific declarations // GIC revision 3 specific declarations
#define ICC_SRE_EL2_SRE (1 << 0) #define ICC_SRE_EL2_SRE (1 << 0)
#define ARM_GICD_IROUTER_IRM BIT31 #define ARM_GICD_IROUTER_IRM BIT31
UINT32 UINT32
EFIAPI EFIAPI
@ -296,7 +295,7 @@ ArmGicV3GetControlSystemRegisterEnable (
VOID VOID
EFIAPI EFIAPI
ArmGicV3SetControlSystemRegisterEnable ( ArmGicV3SetControlSystemRegisterEnable (
IN UINT32 ControlSystemRegisterEnable IN UINT32 ControlSystemRegisterEnable
); );
VOID VOID
@ -320,17 +319,17 @@ ArmGicV3AcknowledgeInterrupt (
VOID VOID
EFIAPI EFIAPI
ArmGicV3EndOfInterrupt ( ArmGicV3EndOfInterrupt (
IN UINTN Source IN UINTN Source
); );
VOID VOID
ArmGicV3SetBinaryPointer ( ArmGicV3SetBinaryPointer (
IN UINTN BinaryPoint IN UINTN BinaryPoint
); );
VOID VOID
ArmGicV3SetPriorityMask ( ArmGicV3SetPriorityMask (
IN UINTN Priority IN UINTN Priority
); );
#endif // ARMGIC_H_ #endif // ARMGIC_H_

18
ArmPkg/Include/Library/ArmHvcLib.h
View File

@ -14,14 +14,14 @@
* The native size is used for the arguments. * The native size is used for the arguments.
*/ */
typedef struct { typedef struct {
UINTN Arg0; UINTN Arg0;
UINTN Arg1; UINTN Arg1;
UINTN Arg2; UINTN Arg2;
UINTN Arg3; UINTN Arg3;
UINTN Arg4; UINTN Arg4;
UINTN Arg5; UINTN Arg5;
UINTN Arg6; UINTN Arg6;
UINTN Arg7; UINTN Arg7;
} ARM_HVC_ARGS; } ARM_HVC_ARGS;
/** /**
@ -34,7 +34,7 @@ typedef struct {
**/ **/
VOID VOID
ArmCallHvc ( ArmCallHvc (
IN OUT ARM_HVC_ARGS *Args IN OUT ARM_HVC_ARGS *Args
); );
#endif // ARM_HVC_LIB_H_ #endif // ARM_HVC_LIB_H_

143
ArmPkg/Include/Library/ArmLib.h
View File

@ -15,13 +15,13 @@
#ifdef MDE_CPU_ARM #ifdef MDE_CPU_ARM
#include <Chipset/ArmV7.h> #include <Chipset/ArmV7.h>
#elif defined(MDE_CPU_AARCH64) #elif defined (MDE_CPU_AARCH64)
#include <Chipset/AArch64.h> #include <Chipset/AArch64.h>
#else #else
#error "Unknown chipset." #error "Unknown chipset."
#endif #endif
#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
EFI_MEMORY_WT | EFI_MEMORY_WB | \ EFI_MEMORY_WT | EFI_MEMORY_WB | \
EFI_MEMORY_UCE) EFI_MEMORY_UCE)
@ -50,17 +50,21 @@ typedef enum {
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
} ARM_MEMORY_REGION_ATTRIBUTES; } ARM_MEMORY_REGION_ATTRIBUTES;
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1) #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
typedef struct { typedef struct {
EFI_PHYSICAL_ADDRESS PhysicalBase; EFI_PHYSICAL_ADDRESS PhysicalBase;
EFI_VIRTUAL_ADDRESS VirtualBase; EFI_VIRTUAL_ADDRESS VirtualBase;
UINT64 Length; UINT64 Length;
ARM_MEMORY_REGION_ATTRIBUTES Attributes; ARM_MEMORY_REGION_ATTRIBUTES Attributes;
} ARM_MEMORY_REGION_DESCRIPTOR; } ARM_MEMORY_REGION_DESCRIPTOR;
typedef VOID (*CACHE_OPERATION)(VOID); typedef VOID (*CACHE_OPERATION)(
typedef VOID (*LINE_OPERATION)(UINTN); VOID
);
typedef VOID (*LINE_OPERATION)(
UINTN
);
// //
// ARM Processor Mode // ARM Processor Mode
@ -80,34 +84,34 @@ typedef enum {
// //
// ARM Cpu IDs // ARM Cpu IDs
// //
#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24) #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24) #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24) #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24) #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24) #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24) #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4) #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4) #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4) #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4) #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4) #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4) #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
// //
// ARM MP Core IDs // ARM MP Core IDs
// //
#define ARM_CORE_AFF0 0xFF #define ARM_CORE_AFF0 0xFF
#define ARM_CORE_AFF1 (0xFF << 8) #define ARM_CORE_AFF1 (0xFF << 8)
#define ARM_CORE_AFF2 (0xFF << 16) #define ARM_CORE_AFF2 (0xFF << 16)
#define ARM_CORE_AFF3 (0xFFULL << 32) #define ARM_CORE_AFF3 (0xFFULL << 32)
#define ARM_CORE_MASK ARM_CORE_AFF0 #define ARM_CORE_MASK ARM_CORE_AFF0
#define ARM_CLUSTER_MASK ARM_CORE_AFF1 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK) #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8) #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
/** Reads the CCSIDR register for the specified cache. /** Reads the CCSIDR register for the specified cache.
@ -118,7 +122,7 @@ typedef enum {
**/ **/
UINTN UINTN
ReadCCSIDR ( ReadCCSIDR (
IN UINT32 CSSELR IN UINT32 CSSELR
); );
/** Reads the CCSIDR2 for the specified cache. /** Reads the CCSIDR2 for the specified cache.
@ -129,7 +133,7 @@ ReadCCSIDR (
**/ **/
UINT32 UINT32
ReadCCSIDR2 ( ReadCCSIDR2 (
IN UINT32 CSSELR IN UINT32 CSSELR
); );
/** Reads the Cache Level ID (CLIDR) register. /** Reads the Cache Level ID (CLIDR) register.
@ -183,7 +187,6 @@ ArmInvalidateDataCache (
VOID VOID
); );
VOID VOID
EFIAPI EFIAPI
ArmCleanInvalidateDataCache ( ArmCleanInvalidateDataCache (
@ -205,31 +208,31 @@ ArmInvalidateInstructionCache (
VOID VOID
EFIAPI EFIAPI
ArmInvalidateDataCacheEntryByMVA ( ArmInvalidateDataCacheEntryByMVA (
IN UINTN Address IN UINTN Address
); );
VOID VOID
EFIAPI EFIAPI
ArmCleanDataCacheEntryToPoUByMVA ( ArmCleanDataCacheEntryToPoUByMVA (
IN UINTN Address IN UINTN Address
); );
VOID VOID
EFIAPI EFIAPI
ArmInvalidateInstructionCacheEntryToPoUByMVA ( ArmInvalidateInstructionCacheEntryToPoUByMVA (
IN UINTN Address IN UINTN Address
); );
VOID VOID
EFIAPI EFIAPI
ArmCleanDataCacheEntryByMVA ( ArmCleanDataCacheEntryByMVA (
IN UINTN Address IN UINTN Address
); );
VOID VOID
EFIAPI EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA ( ArmCleanInvalidateDataCacheEntryByMVA (
IN UINTN Address IN UINTN Address
); );
VOID VOID
@ -352,8 +355,8 @@ ArmInvalidateTlb (
VOID VOID
EFIAPI EFIAPI
ArmUpdateTranslationTableEntry ( ArmUpdateTranslationTableEntry (
IN VOID *TranslationTableEntry, IN VOID *TranslationTableEntry,
IN VOID *Mva IN VOID *Mva
); );
VOID VOID
@ -371,7 +374,7 @@ ArmSetTTBR0 (
VOID VOID
EFIAPI EFIAPI
ArmSetTTBCR ( ArmSetTTBCR (
IN UINT32 Bits IN UINT32 Bits
); );
VOID * VOID *
@ -431,7 +434,7 @@ ArmInstructionSynchronizationBarrier (
VOID VOID
EFIAPI EFIAPI
ArmWriteVBar ( ArmWriteVBar (
IN UINTN VectorBase IN UINTN VectorBase
); );
UINTN UINTN
@ -443,7 +446,7 @@ ArmReadVBar (
VOID VOID
EFIAPI EFIAPI
ArmWriteAuxCr ( ArmWriteAuxCr (
IN UINT32 Bit IN UINT32 Bit
); );
UINT32 UINT32
@ -455,13 +458,13 @@ ArmReadAuxCr (
VOID VOID
EFIAPI EFIAPI
ArmSetAuxCrBit ( ArmSetAuxCrBit (
IN UINT32 Bits IN UINT32 Bits
); );
VOID VOID
EFIAPI EFIAPI
ArmUnsetAuxCrBit ( ArmUnsetAuxCrBit (
IN UINT32 Bits IN UINT32 Bits
); );
VOID VOID
@ -504,7 +507,7 @@ ArmReadCpacr (
VOID VOID
EFIAPI EFIAPI
ArmWriteCpacr ( ArmWriteCpacr (
IN UINT32 Access IN UINT32 Access
); );
VOID VOID
@ -534,7 +537,7 @@ ArmReadScr (
VOID VOID
EFIAPI EFIAPI
ArmWriteScr ( ArmWriteScr (
IN UINT32 Value IN UINT32 Value
); );
UINT32 UINT32
@ -546,7 +549,7 @@ ArmReadMVBar (
VOID VOID
EFIAPI EFIAPI
ArmWriteMVBar ( ArmWriteMVBar (
IN UINT32 VectorMonitorBase IN UINT32 VectorMonitorBase
); );
UINT32 UINT32
@ -558,7 +561,7 @@ ArmReadSctlr (
VOID VOID
EFIAPI EFIAPI
ArmWriteSctlr ( ArmWriteSctlr (
IN UINT32 Value IN UINT32 Value
); );
UINTN UINTN
@ -570,10 +573,9 @@ ArmReadHVBar (
VOID VOID
EFIAPI EFIAPI
ArmWriteHVBar ( ArmWriteHVBar (
IN UINTN HypModeVectorBase IN UINTN HypModeVectorBase
); );
// //
// Helper functions for accessing CPU ACTLR // Helper functions for accessing CPU ACTLR
// //
@ -587,28 +589,28 @@ ArmReadCpuActlr (
VOID VOID
EFIAPI EFIAPI
ArmWriteCpuActlr ( ArmWriteCpuActlr (
IN UINTN Val IN UINTN Val
); );
VOID VOID
EFIAPI EFIAPI
ArmSetCpuActlrBit ( ArmSetCpuActlrBit (
IN UINTN Bits IN UINTN Bits
); );
VOID VOID
EFIAPI EFIAPI
ArmUnsetCpuActlrBit ( ArmUnsetCpuActlrBit (
IN UINTN Bits IN UINTN Bits
); );
// //
// Accessors for the architected generic timer registers // Accessors for the architected generic timer registers
// //
#define ARM_ARCH_TIMER_ENABLE (1 << 0) #define ARM_ARCH_TIMER_ENABLE (1 << 0)
#define ARM_ARCH_TIMER_IMASK (1 << 1) #define ARM_ARCH_TIMER_IMASK (1 << 1)
#define ARM_ARCH_TIMER_ISTATUS (1 << 2) #define ARM_ARCH_TIMER_ISTATUS (1 << 2)
UINTN UINTN
EFIAPI EFIAPI
@ -619,7 +621,7 @@ ArmReadCntFrq (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntFrq ( ArmWriteCntFrq (
UINTN FreqInHz UINTN FreqInHz
); );
UINT64 UINT64
@ -637,7 +639,7 @@ ArmReadCntkCtl (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntkCtl ( ArmWriteCntkCtl (
UINTN Val UINTN Val
); );
UINTN UINTN
@ -649,7 +651,7 @@ ArmReadCntpTval (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntpTval ( ArmWriteCntpTval (
UINTN Val UINTN Val
); );
UINTN UINTN
@ -661,7 +663,7 @@ ArmReadCntpCtl (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntpCtl ( ArmWriteCntpCtl (
UINTN Val UINTN Val
); );
UINTN UINTN
@ -673,7 +675,7 @@ ArmReadCntvTval (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntvTval ( ArmWriteCntvTval (
UINTN Val UINTN Val
); );
UINTN UINTN
@ -685,7 +687,7 @@ ArmReadCntvCtl (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntvCtl ( ArmWriteCntvCtl (
UINTN Val UINTN Val
); );
UINT64 UINT64
@ -703,7 +705,7 @@ ArmReadCntpCval (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntpCval ( ArmWriteCntpCval (
UINT64 Val UINT64 Val
); );
UINT64 UINT64
@ -715,7 +717,7 @@ ArmReadCntvCval (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntvCval ( ArmWriteCntvCval (
UINT64 Val UINT64 Val
); );
UINT64 UINT64
@ -727,7 +729,7 @@ ArmReadCntvOff (
VOID VOID
EFIAPI EFIAPI
ArmWriteCntvOff ( ArmWriteCntvOff (
UINT64 Val UINT64 Val
); );
UINTN UINTN
@ -736,7 +738,6 @@ ArmGetPhysicalAddressBits (
VOID VOID
); );
/// ///
/// ID Register Helper functions /// ID Register Helper functions
/// ///
@ -768,6 +769,7 @@ ArmHasCcidx (
/// ///
/// AArch32-only ID Register Helper functions /// AArch32-only ID Register Helper functions
/// ///
/** /**
Check whether the CPU supports the Security extensions Check whether the CPU supports the Security extensions
@ -779,6 +781,7 @@ EFIAPI
ArmHasSecurityExtensions ( ArmHasSecurityExtensions (
VOID VOID
); );
#endif // MDE_CPU_ARM #endif // MDE_CPU_ARM
#endif // ARM_LIB_H_ #endif // ARM_LIB_H_

22
ArmPkg/Include/Library/ArmMmuLib.h
View File

@ -24,29 +24,29 @@ ArmConfigureMmu (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
ArmSetMemoryRegionNoExec ( ArmSetMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
ArmClearMemoryRegionNoExec ( ArmClearMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
ArmSetMemoryRegionReadOnly ( ArmSetMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
ArmClearMemoryRegionReadOnly ( ArmClearMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
); );
VOID VOID
@ -59,9 +59,9 @@ ArmReplaceLiveTranslationEntry (
EFI_STATUS EFI_STATUS
ArmSetMemoryAttributes ( ArmSetMemoryAttributes (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
); );
#endif // ARM_MMU_LIB_H_ #endif // ARM_MMU_LIB_H_

33
ArmPkg/Include/Library/ArmMtlLib.h
View File

@ -18,37 +18,37 @@
#pragma pack(1) #pragma pack(1)
typedef struct { typedef struct {
UINT32 Reserved1; UINT32 Reserved1;
UINT32 ChannelStatus; UINT32 ChannelStatus;
UINT64 Reserved2; UINT64 Reserved2;
UINT32 Flags; UINT32 Flags;
UINT32 Length; UINT32 Length;
UINT32 MessageHeader; UINT32 MessageHeader;
// NOTE: Since EDK2 does not allow flexible array member [] we declare // NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable // here array of 1 element length. However below is used as a variable
// length array. // length array.
UINT32 Payload[1]; // size less object gives offset to payload. UINT32 Payload[1]; // size less object gives offset to payload.
} MTL_MAILBOX; } MTL_MAILBOX;
#pragma pack() #pragma pack()
// Channel Type, Low-priority, and High-priority // Channel Type, Low-priority, and High-priority
typedef enum { typedef enum {
MTL_CHANNEL_TYPE_LOW = 0, MTL_CHANNEL_TYPE_LOW = 0,
MTL_CHANNEL_TYPE_HIGH = 1 MTL_CHANNEL_TYPE_HIGH = 1
} MTL_CHANNEL_TYPE; } MTL_CHANNEL_TYPE;
typedef struct { typedef struct {
UINT64 PhysicalAddress; UINT64 PhysicalAddress;
UINT32 ModifyMask; UINT32 ModifyMask;
UINT32 PreserveMask; UINT32 PreserveMask;
} MTL_DOORBELL; } MTL_DOORBELL;
typedef struct { typedef struct {
MTL_CHANNEL_TYPE ChannelType; MTL_CHANNEL_TYPE ChannelType;
MTL_MAILBOX * CONST MailBox; MTL_MAILBOX *CONST MailBox;
MTL_DOORBELL DoorBell; MTL_DOORBELL DoorBell;
} MTL_CHANNEL; } MTL_CHANNEL;
/** Wait until channel is free. /** Wait until channel is free.
@ -71,7 +71,7 @@ MtlWaitUntilChannelFree (
@retval UINT32* Pointer to the payload. @retval UINT32* Pointer to the payload.
**/ **/
UINT32* UINT32 *
MtlGetChannelPayload ( MtlGetChannelPayload (
IN MTL_CHANNEL *Channel IN MTL_CHANNEL *Channel
); );
@ -127,5 +127,4 @@ MtlReceiveMessage (
OUT UINT32 *PayloadLength OUT UINT32 *PayloadLength
); );
#endif /* ARM_MTL_LIB_H_ */ #endif /* ARM_MTL_LIB_H_ */

18
ArmPkg/Include/Library/ArmSmcLib.h
View File

@ -14,14 +14,14 @@
* The native size is used for the arguments. * The native size is used for the arguments.
*/ */
typedef struct { typedef struct {
UINTN Arg0; UINTN Arg0;
UINTN Arg1; UINTN Arg1;
UINTN Arg2; UINTN Arg2;
UINTN Arg3; UINTN Arg3;
UINTN Arg4; UINTN Arg4;
UINTN Arg5; UINTN Arg5;
UINTN Arg6; UINTN Arg6;
UINTN Arg7; UINTN Arg7;
} ARM_SMC_ARGS; } ARM_SMC_ARGS;
/** /**
@ -34,7 +34,7 @@ typedef struct {
**/ **/
VOID VOID
ArmCallSmc ( ArmCallSmc (
IN OUT ARM_SMC_ARGS *Args IN OUT ARM_SMC_ARGS *Args
); );
#endif // ARM_SMC_LIB_H_ #endif // ARM_SMC_LIB_H_

18
ArmPkg/Include/Library/ArmSvcLib.h
View File

@ -14,14 +14,14 @@
* The native size is used for the arguments. * The native size is used for the arguments.
*/ */
typedef struct { typedef struct {
UINTN Arg0; UINTN Arg0;
UINTN Arg1; UINTN Arg1;
UINTN Arg2; UINTN Arg2;
UINTN Arg3; UINTN Arg3;
UINTN Arg4; UINTN Arg4;
UINTN Arg5; UINTN Arg5;
UINTN Arg6; UINTN Arg6;
UINTN Arg7; UINTN Arg7;
} ARM_SVC_ARGS; } ARM_SVC_ARGS;
/** /**
@ -40,7 +40,7 @@ typedef struct {
**/ **/
VOID VOID
ArmCallSvc ( ArmCallSvc (
IN OUT ARM_SVC_ARGS *Args IN OUT ARM_SVC_ARGS *Args
); );
#endif // ARM_SVC_LIB_H_ #endif // ARM_SVC_LIB_H_

4
ArmPkg/Include/Library/DefaultExceptionHandlerLib.h
View File

@ -18,8 +18,8 @@
**/ **/
VOID VOID
DefaultExceptionHandler ( DefaultExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN OUT EFI_SYSTEM_CONTEXT SystemContext IN OUT EFI_SYSTEM_CONTEXT SystemContext
); );
#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_ #endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_

88
ArmPkg/Include/Library/OemMiscLib.h
View File

@ -8,15 +8,13 @@
* *
**/ **/
#ifndef OEM_MISC_LIB_H_ #ifndef OEM_MISC_LIB_H_
#define OEM_MISC_LIB_H_ #define OEM_MISC_LIB_H_
#include <Uefi.h> #include <Uefi.h>
#include <IndustryStandard/SmBios.h> #include <IndustryStandard/SmBios.h>
typedef enum typedef enum {
{
CpuCacheL1 = 1, CpuCacheL1 = 1,
CpuCacheL2, CpuCacheL2,
CpuCacheL3, CpuCacheL3,
@ -27,37 +25,35 @@ typedef enum
CpuCacheLevelMax CpuCacheLevelMax
} OEM_MISC_CPU_CACHE_LEVEL; } OEM_MISC_CPU_CACHE_LEVEL;
typedef struct typedef struct {
{ UINT8 Voltage; ///< Processor voltage
UINT8 Voltage; ///< Processor voltage UINT16 CurrentSpeed; ///< Current clock speed in MHz
UINT16 CurrentSpeed; ///< Current clock speed in MHz UINT16 MaxSpeed; ///< Maximum clock speed in MHz
UINT16 MaxSpeed; ///< Maximum clock speed in MHz UINT16 ExternalClock; ///< External clock speed in MHz
UINT16 ExternalClock; ///< External clock speed in MHz UINT16 CoreCount; ///< Number of cores available
UINT16 CoreCount; ///< Number of cores available UINT16 CoresEnabled; ///< Number of cores enabled
UINT16 CoresEnabled; ///< Number of cores enabled UINT16 ThreadCount; ///< Number of threads per processor
UINT16 ThreadCount; ///< Number of threads per processor
} OEM_MISC_PROCESSOR_DATA; } OEM_MISC_PROCESSOR_DATA;
typedef enum typedef enum {
{ ProductNameType01,
ProductNameType01, SerialNumType01,
SerialNumType01, UuidType01,
UuidType01, SystemManufacturerType01,
SystemManufacturerType01, SkuNumberType01,
SkuNumberType01, FamilyType01,
FamilyType01, AssertTagType02,
AssertTagType02, SerialNumberType02,
SerialNumberType02, BoardManufacturerType02,
BoardManufacturerType02, SkuNumberType02,
SkuNumberType02, ChassisLocationType02,
ChassisLocationType02, AssetTagType03,
AssetTagType03, SerialNumberType03,
SerialNumberType03, VersionType03,
VersionType03, ChassisTypeType03,
ChassisTypeType03, ManufacturerType03,
ManufacturerType03, SkuNumberType03,
SkuNumberType03, SmbiosHiiStringFieldMax
SmbiosHiiStringFieldMax
} OEM_MISC_SMBIOS_HII_STRING_FIELD; } OEM_MISC_SMBIOS_HII_STRING_FIELD;
/* /*
@ -74,7 +70,7 @@ typedef enum
UINTN UINTN
EFIAPI EFIAPI
OemGetCpuFreq ( OemGetCpuFreq (
IN UINT8 ProcessorIndex IN UINT8 ProcessorIndex
); );
/** Gets information about the specified processor and stores it in /** Gets information about the specified processor and stores it in
@ -90,10 +86,10 @@ OemGetCpuFreq (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
OemGetProcessorInformation ( OemGetProcessorInformation (
IN UINTN ProcessorIndex, IN UINTN ProcessorIndex,
IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
); );
/** Gets information about the cache at the specified cache level. /** Gets information about the cache at the specified cache level.
@ -109,11 +105,11 @@ OemGetProcessorInformation (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
OemGetCacheInformation ( OemGetCacheInformation (
IN UINT8 ProcessorIndex, IN UINT8 ProcessorIndex,
IN UINT8 CacheLevel, IN UINT8 CacheLevel,
IN BOOLEAN DataCache, IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache, IN BOOLEAN UnifiedCache,
IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
); );
/** Gets the maximum number of processors supported by the platform. /** Gets the maximum number of processors supported by the platform.
@ -145,7 +141,7 @@ OemGetChassisType (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
OemIsProcessorPresent ( OemIsProcessorPresent (
IN UINTN ProcessorIndex IN UINTN ProcessorIndex
); );
/** Updates the HII string for the specified field. /** Updates the HII string for the specified field.
@ -157,9 +153,9 @@ OemIsProcessorPresent (
VOID VOID
EFIAPI EFIAPI
OemUpdateSmbiosInfo ( OemUpdateSmbiosInfo (
IN EFI_HII_HANDLE HiiHandle, IN EFI_HII_HANDLE HiiHandle,
IN EFI_STRING_ID TokenToUpdate, IN EFI_STRING_ID TokenToUpdate,
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
); );
/** Fetches the Type 32 boot information status. /** Fetches the Type 32 boot information status.

82
ArmPkg/Include/Library/OpteeLib.h
View File

@ -15,24 +15,24 @@
* The 'Trusted OS Call UID' is supposed to return the following UUID for * The 'Trusted OS Call UID' is supposed to return the following UUID for
* OP-TEE OS. This is a 128-bit value. * OP-TEE OS. This is a 128-bit value.
*/ */
#define OPTEE_OS_UID0 0x384fb3e0 #define OPTEE_OS_UID0 0x384fb3e0
#define OPTEE_OS_UID1 0xe7f811e3 #define OPTEE_OS_UID1 0xe7f811e3
#define OPTEE_OS_UID2 0xaf630002 #define OPTEE_OS_UID2 0xaf630002
#define OPTEE_OS_UID3 0xa5d5c51b #define OPTEE_OS_UID3 0xa5d5c51b
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0 #define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1 #define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2 #define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3 #define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9 #define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa #define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb #define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff #define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff
#define OPTEE_SUCCESS 0x00000000 #define OPTEE_SUCCESS 0x00000000
#define OPTEE_ORIGIN_COMMUNICATION 0x00000002 #define OPTEE_ORIGIN_COMMUNICATION 0x00000002
#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E #define OPTEE_ERROR_COMMUNICATION 0xFFFF000E
typedef struct { typedef struct {
UINT64 BufferAddress; UINT64 BufferAddress;
@ -47,44 +47,44 @@ typedef struct {
} OPTEE_MESSAGE_PARAM_VALUE; } OPTEE_MESSAGE_PARAM_VALUE;
typedef union { typedef union {
OPTEE_MESSAGE_PARAM_MEMORY Memory; OPTEE_MESSAGE_PARAM_MEMORY Memory;
OPTEE_MESSAGE_PARAM_VALUE Value; OPTEE_MESSAGE_PARAM_VALUE Value;
} OPTEE_MESSAGE_PARAM_UNION; } OPTEE_MESSAGE_PARAM_UNION;
typedef struct { typedef struct {
UINT64 Attribute; UINT64 Attribute;
OPTEE_MESSAGE_PARAM_UNION Union; OPTEE_MESSAGE_PARAM_UNION Union;
} OPTEE_MESSAGE_PARAM; } OPTEE_MESSAGE_PARAM;
#define OPTEE_MAX_CALL_PARAMS 4 #define OPTEE_MAX_CALL_PARAMS 4
typedef struct { typedef struct {
UINT32 Command; UINT32 Command;
UINT32 Function; UINT32 Function;
UINT32 Session; UINT32 Session;
UINT32 CancelId; UINT32 CancelId;
UINT32 Pad; UINT32 Pad;
UINT32 Return; UINT32 Return;
UINT32 ReturnOrigin; UINT32 ReturnOrigin;
UINT32 NumParams; UINT32 NumParams;
// NumParams tells the actual number of element in Params // NumParams tells the actual number of element in Params
OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];
} OPTEE_MESSAGE_ARG; } OPTEE_MESSAGE_ARG;
typedef struct { typedef struct {
EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application
UINT32 Session; // [out] Session id UINT32 Session; // [out] Session id
UINT32 Return; // [out] Return value UINT32 Return; // [out] Return value
UINT32 ReturnOrigin; // [out] Origin of the return value UINT32 ReturnOrigin; // [out] Origin of the return value
} OPTEE_OPEN_SESSION_ARG; } OPTEE_OPEN_SESSION_ARG;
typedef struct { typedef struct {
UINT32 Function; // [in] Trusted Application function, specific to the TA UINT32 Function; // [in] Trusted Application function, specific to the TA
UINT32 Session; // [in] Session id UINT32 Session; // [in] Session id
UINT32 Return; // [out] Return value UINT32 Return; // [out] Return value
UINT32 ReturnOrigin; // [out] Origin of the return value UINT32 ReturnOrigin; // [out] Origin of the return value
OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked
} OPTEE_INVOKE_FUNCTION_ARG; } OPTEE_INVOKE_FUNCTION_ARG;
BOOLEAN BOOLEAN
@ -102,19 +102,19 @@ OpteeInit (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
OpteeOpenSession ( OpteeOpenSession (
IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
OpteeCloseSession ( OpteeCloseSession (
IN UINT32 Session IN UINT32 Session
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
OpteeInvokeFunction ( OpteeInvokeFunction (
IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
); );
#endif // OPTEE_LIB_H_ #endif // OPTEE_LIB_H_

30
ArmPkg/Include/Library/SemihostLib.h
View File

@ -17,12 +17,12 @@
* *
*/ */
#define SEMIHOST_FILE_MODE_READ (0 << 2) #define SEMIHOST_FILE_MODE_READ (0 << 2)
#define SEMIHOST_FILE_MODE_WRITE (1 << 2) #define SEMIHOST_FILE_MODE_WRITE (1 << 2)
#define SEMIHOST_FILE_MODE_APPEND (2 << 2) #define SEMIHOST_FILE_MODE_APPEND (2 << 2)
#define SEMIHOST_FILE_MODE_UPDATE (1 << 1) #define SEMIHOST_FILE_MODE_UPDATE (1 << 1)
#define SEMIHOST_FILE_MODE_BINARY (1 << 0) #define SEMIHOST_FILE_MODE_BINARY (1 << 0)
#define SEMIHOST_FILE_MODE_ASCII (0 << 0) #define SEMIHOST_FILE_MODE_ASCII (0 << 0)
BOOLEAN BOOLEAN
SemihostConnectionSupported ( SemihostConnectionSupported (
@ -31,9 +31,9 @@ SemihostConnectionSupported (
RETURN_STATUS RETURN_STATUS
SemihostFileOpen ( SemihostFileOpen (
IN CHAR8 *FileName, IN CHAR8 *FileName,
IN UINT32 Mode, IN UINT32 Mode,
OUT UINTN *FileHandle OUT UINTN *FileHandle
); );
RETURN_STATUS RETURN_STATUS
@ -81,7 +81,7 @@ SemihostFileLength (
**/ **/
RETURN_STATUS RETURN_STATUS
SemihostFileTmpName( SemihostFileTmpName (
OUT VOID *Buffer, OUT VOID *Buffer,
IN UINT8 Identifier, IN UINT8 Identifier,
IN UINTN Length IN UINTN Length
@ -89,7 +89,7 @@ SemihostFileTmpName(
RETURN_STATUS RETURN_STATUS
SemihostFileRemove ( SemihostFileRemove (
IN CHAR8 *FileName IN CHAR8 *FileName
); );
/** /**
@ -104,7 +104,7 @@ SemihostFileRemove (
**/ **/
RETURN_STATUS RETURN_STATUS
SemihostFileRename( SemihostFileRename (
IN CHAR8 *FileName, IN CHAR8 *FileName,
IN CHAR8 *NewFileName IN CHAR8 *NewFileName
); );
@ -116,17 +116,17 @@ SemihostReadCharacter (
VOID VOID
SemihostWriteCharacter ( SemihostWriteCharacter (
IN CHAR8 Character IN CHAR8 Character
); );
VOID VOID
SemihostWriteString ( SemihostWriteString (
IN CHAR8 *String IN CHAR8 *String
); );
UINT32 UINT32
SemihostSystem ( SemihostSystem (
IN CHAR8 *CommandLine IN CHAR8 *CommandLine
); );
#endif // SEMIHOSTING_LIB_H_ #endif // SEMIHOSTING_LIB_H_

16
ArmPkg/Include/Library/StandaloneMmMmuLib.h
View File

@ -11,26 +11,26 @@
EFI_STATUS EFI_STATUS
ArmSetMemoryRegionNoExec ( ArmSetMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
); );
EFI_STATUS EFI_STATUS
ArmClearMemoryRegionNoExec ( ArmClearMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
); );
EFI_STATUS EFI_STATUS
ArmSetMemoryRegionReadOnly ( ArmSetMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
); );
EFI_STATUS EFI_STATUS
ArmClearMemoryRegionReadOnly ( ArmClearMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
); );
#endif /* STANDALONE_MM_MMU_LIB_ */ #endif /* STANDALONE_MM_MMU_LIB_ */

10
ArmPkg/Include/Ppi/ArmMpCoreInfo.h
View File

@ -32,10 +32,10 @@
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI * ARM_MP_CORE_INFO_GET) ( (EFIAPI *ARM_MP_CORE_INFO_GET)(
OUT UINTN *ArmCoreCount, OUT UINTN *ArmCoreCount,
OUT ARM_CORE_INFO **ArmCoreTable OUT ARM_CORE_INFO **ArmCoreTable
); );
/// ///
/// This service abstracts the ability to migrate contents of the platform early memory store. /// This service abstracts the ability to migrate contents of the platform early memory store.
@ -43,10 +43,10 @@ EFI_STATUS
/// This PPI was optional. /// This PPI was optional.
/// ///
typedef struct { typedef struct {
ARM_MP_CORE_INFO_GET GetMpCoreInfo; ARM_MP_CORE_INFO_GET GetMpCoreInfo;
} ARM_MP_CORE_INFO_PPI; } ARM_MP_CORE_INFO_PPI;
extern EFI_GUID gArmMpCoreInfoPpiGuid; extern EFI_GUID gArmMpCoreInfoPpiGuid;
extern EFI_GUID gArmMpCoreInfoGuid; extern EFI_GUID gArmMpCoreInfoGuid;
#endif // ARM_MP_CORE_INFO_PPI_H_ #endif // ARM_MP_CORE_INFO_PPI_H_

3
ArmPkg/Include/Protocol/ArmScmi.h
View File

@ -15,7 +15,6 @@
/* As per SCMI specification, maximum allowed ASCII string length /* As per SCMI specification, maximum allowed ASCII string length
for various return values/parameters of a SCMI message. for various return values/parameters of a SCMI message.
*/ */
#define SCMI_MAX_STR_LEN 16 #define SCMI_MAX_STR_LEN 16
#endif /* ARM_SCMI_H_ */ #endif /* ARM_SCMI_H_ */

44
ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
View File

@ -17,24 +17,24 @@
#define BASE_PROTOCOL_VERSION_V1 0x10000 #define BASE_PROTOCOL_VERSION_V1 0x10000
#define BASE_PROTOCOL_VERSION_V2 0x20000 #define BASE_PROTOCOL_VERSION_V2 0x20000
#define NUM_PROTOCOL_MASK 0xFFU #define NUM_PROTOCOL_MASK 0xFFU
#define NUM_AGENT_MASK 0xFFU #define NUM_AGENT_MASK 0xFFU
#define NUM_AGENT_SHIFT 0x8 #define NUM_AGENT_SHIFT 0x8
/** Returns total number of protocols that are /** Returns total number of protocols that are
implemented (excluding the Base protocol) implemented (excluding the Base protocol)
*/ */
#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK) #define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)
// Returns total number of agents in the system. // Returns total number of agents in the system.
#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK) #define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)
#define ARM_SCMI_BASE_PROTOCOL_GUID { \ #define ARM_SCMI_BASE_PROTOCOL_GUID { \
0xd7e5abe9, 0x33ab, 0x418e, {0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f} \ 0xd7e5abe9, 0x33ab, 0x418e, {0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f} \
} }
extern EFI_GUID gArmScmiBaseProtocolGuid; extern EFI_GUID gArmScmiBaseProtocolGuid;
typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL; typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL;
@ -50,7 +50,7 @@ typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL;
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_BASE_GET_VERSION) ( (EFIAPI *SCMI_BASE_GET_VERSION)(
IN SCMI_BASE_PROTOCOL *This, IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *Version OUT UINT32 *Version
); );
@ -67,7 +67,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS) ( (EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS)(
IN SCMI_BASE_PROTOCOL *This, IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *TotalProtocols OUT UINT32 *TotalProtocols
); );
@ -85,7 +85,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_BASE_DISCOVER_VENDOR) ( (EFIAPI *SCMI_BASE_DISCOVER_VENDOR)(
IN SCMI_BASE_PROTOCOL *This, IN SCMI_BASE_PROTOCOL *This,
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN] OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
); );
@ -103,7 +103,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR) ( (EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR)(
IN SCMI_BASE_PROTOCOL *This, IN SCMI_BASE_PROTOCOL *This,
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN] OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
); );
@ -120,7 +120,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION) ( (EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION)(
IN SCMI_BASE_PROTOCOL *This, IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *ImplementationVersion OUT UINT32 *ImplementationVersion
); );
@ -141,7 +141,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS) ( (EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS)(
IN SCMI_BASE_PROTOCOL *This, IN SCMI_BASE_PROTOCOL *This,
IN OUT UINT32 *ProtocolListSize, IN OUT UINT32 *ProtocolListSize,
OUT UINT8 *ProtocolList OUT UINT8 *ProtocolList
@ -149,20 +149,20 @@ EFI_STATUS
// Base protocol. // Base protocol.
typedef struct _SCMI_BASE_PROTOCOL { typedef struct _SCMI_BASE_PROTOCOL {
SCMI_BASE_GET_VERSION GetVersion; SCMI_BASE_GET_VERSION GetVersion;
SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols; SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;
SCMI_BASE_DISCOVER_VENDOR DiscoverVendor; SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;
SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor; SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;
SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion; SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;
SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols; SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;
} SCMI_BASE_PROTOCOL; } SCMI_BASE_PROTOCOL;
// SCMI Message IDs for Base protocol. // SCMI Message IDs for Base protocol.
typedef enum { typedef enum {
ScmiMessageIdBaseDiscoverVendor = 0x3, ScmiMessageIdBaseDiscoverVendor = 0x3,
ScmiMessageIdBaseDiscoverSubVendor = 0x4, ScmiMessageIdBaseDiscoverSubVendor = 0x4,
ScmiMessageIdBaseDiscoverImplementationVersion = 0x5, ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
ScmiMessageIdBaseDiscoverListProtocols = 0x6 ScmiMessageIdBaseDiscoverListProtocols = 0x6
} SCMI_MESSAGE_ID_BASE; } SCMI_MESSAGE_ID_BASE;
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */ #endif /* ARM_SCMI_BASE_PROTOCOL_H_ */

36
ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h
View File

@ -15,13 +15,13 @@
#include <Protocol/ArmScmi.h> #include <Protocol/ArmScmi.h>
#include <Protocol/ArmScmiClockProtocol.h> #include <Protocol/ArmScmiClockProtocol.h>
#define ARM_SCMI_CLOCK2_PROTOCOL_GUID { \ #define ARM_SCMI_CLOCK2_PROTOCOL_GUID {\
0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \ 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \
} }
extern EFI_GUID gArmScmiClock2ProtocolGuid; extern EFI_GUID gArmScmiClock2ProtocolGuid;
#define SCMI_CLOCK2_PROTOCOL_VERSION 1 #define SCMI_CLOCK2_PROTOCOL_VERSION 1
typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL; typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL;
@ -39,7 +39,7 @@ typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL;
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK2_GET_VERSION) ( (EFIAPI *SCMI_CLOCK2_GET_VERSION)(
IN SCMI_CLOCK2_PROTOCOL *This, IN SCMI_CLOCK2_PROTOCOL *This,
OUT UINT32 *Version OUT UINT32 *Version
); );
@ -57,7 +57,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS) ( (EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS)(
IN SCMI_CLOCK2_PROTOCOL *This, IN SCMI_CLOCK2_PROTOCOL *This,
OUT UINT32 *TotalClocks OUT UINT32 *TotalClocks
); );
@ -77,7 +77,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES) ( (EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)(
IN SCMI_CLOCK2_PROTOCOL *This, IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
OUT BOOLEAN *Enabled, OUT BOOLEAN *Enabled,
@ -109,7 +109,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES) ( (EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES)(
IN SCMI_CLOCK2_PROTOCOL *This, IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format, OUT SCMI_CLOCK_RATE_FORMAT *Format,
@ -131,7 +131,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK2_RATE_GET) ( (EFIAPI *SCMI_CLOCK2_RATE_GET)(
IN SCMI_CLOCK2_PROTOCOL *This, IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
OUT UINT64 *Rate OUT UINT64 *Rate
@ -149,7 +149,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK2_RATE_SET) ( (EFIAPI *SCMI_CLOCK2_RATE_SET)(
IN SCMI_CLOCK2_PROTOCOL *This, IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
IN UINT64 Rate IN UINT64 Rate
@ -168,24 +168,24 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK2_ENABLE) ( (EFIAPI *SCMI_CLOCK2_ENABLE)(
IN SCMI_CLOCK2_PROTOCOL *This, IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
IN BOOLEAN Enable IN BOOLEAN Enable
); );
typedef struct _SCMI_CLOCK2_PROTOCOL { typedef struct _SCMI_CLOCK2_PROTOCOL {
SCMI_CLOCK2_GET_VERSION GetVersion; SCMI_CLOCK2_GET_VERSION GetVersion;
SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks; SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;
SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes; SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;
SCMI_CLOCK2_DESCRIBE_RATES DescribeRates; SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;
SCMI_CLOCK2_RATE_GET RateGet; SCMI_CLOCK2_RATE_GET RateGet;
SCMI_CLOCK2_RATE_SET RateSet; SCMI_CLOCK2_RATE_SET RateSet;
// Extension to original ClockProtocol, added here so SCMI_CLOCK2_PROTOCOL // Extension to original ClockProtocol, added here so SCMI_CLOCK2_PROTOCOL
// can be cast to SCMI_CLOCK_PROTOCOL // can be cast to SCMI_CLOCK_PROTOCOL
UINTN Version; // For future expandability UINTN Version; // For future expandability
SCMI_CLOCK2_ENABLE Enable; SCMI_CLOCK2_ENABLE Enable;
} SCMI_CLOCK2_PROTOCOL; } SCMI_CLOCK2_PROTOCOL;
#endif /* ARM_SCMI_CLOCK2_PROTOCOL_H_ */ #endif /* ARM_SCMI_CLOCK2_PROTOCOL_H_ */

53
ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
View File

@ -14,11 +14,11 @@
#include <Protocol/ArmScmi.h> #include <Protocol/ArmScmi.h>
#define ARM_SCMI_CLOCK_PROTOCOL_GUID { \ #define ARM_SCMI_CLOCK_PROTOCOL_GUID {\
0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \ 0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \
} }
extern EFI_GUID gArmScmiClockProtocolGuid; extern EFI_GUID gArmScmiClockProtocolGuid;
// Message Type for clock management protocol. // Message Type for clock management protocol.
typedef enum { typedef enum {
@ -35,21 +35,21 @@ typedef enum {
} SCMI_CLOCK_RATE_FORMAT; } SCMI_CLOCK_RATE_FORMAT;
// Clock management protocol version. // Clock management protocol version.
#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000 #define SCMI_CLOCK_PROTOCOL_VERSION 0x10000
#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU #define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU
#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16 #define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16
#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU #define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU
/** Total number of pending asynchronous clock rates changes /** Total number of pending asynchronous clock rates changes
supported by the SCP, Attr Bits[23:16] supported by the SCP, Attr Bits[23:16]
*/ */
#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \ #define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \
(Attr >> SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT) && \ (Attr >> SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT) && \
SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK) SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK)
// Total of clock devices supported by the SCP, Attr Bits[15:0] // Total of clock devices supported by the SCP, Attr Bits[15:0]
#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK) #define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)
#pragma pack(1) #pragma pack(1)
@ -57,18 +57,18 @@ typedef enum {
either Rate or Min/Max/Step triplet is valid. either Rate or Min/Max/Step triplet is valid.
*/ */
typedef struct { typedef struct {
UINT64 Min; UINT64 Min;
UINT64 Max; UINT64 Max;
UINT64 Step; UINT64 Step;
} SCMI_CLOCK_RATE_CONTINUOUS; } SCMI_CLOCK_RATE_CONTINUOUS;
typedef struct { typedef struct {
UINT64 Rate; UINT64 Rate;
} SCMI_CLOCK_RATE_DISCRETE; } SCMI_CLOCK_RATE_DISCRETE;
typedef union { typedef union {
SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate; SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
SCMI_CLOCK_RATE_DISCRETE DiscreteRate; SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
} SCMI_CLOCK_RATE; } SCMI_CLOCK_RATE;
#pragma pack() #pragma pack()
@ -89,7 +89,7 @@ typedef struct _SCMI_CLOCK_PROTOCOL SCMI_CLOCK_PROTOCOL;
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK_GET_VERSION) ( (EFIAPI *SCMI_CLOCK_GET_VERSION)(
IN SCMI_CLOCK_PROTOCOL *This, IN SCMI_CLOCK_PROTOCOL *This,
OUT UINT32 *Version OUT UINT32 *Version
); );
@ -107,7 +107,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS) ( (EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS)(
IN SCMI_CLOCK_PROTOCOL *This, IN SCMI_CLOCK_PROTOCOL *This,
OUT UINT32 *TotalClocks OUT UINT32 *TotalClocks
); );
@ -127,7 +127,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES) ( (EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES)(
IN SCMI_CLOCK_PROTOCOL *This, IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
OUT BOOLEAN *Enabled, OUT BOOLEAN *Enabled,
@ -159,7 +159,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES) ( (EFIAPI *SCMI_CLOCK_DESCRIBE_RATES)(
IN SCMI_CLOCK_PROTOCOL *This, IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format, OUT SCMI_CLOCK_RATE_FORMAT *Format,
@ -181,7 +181,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK_RATE_GET) ( (EFIAPI *SCMI_CLOCK_RATE_GET)(
IN SCMI_CLOCK_PROTOCOL *This, IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
OUT UINT64 *Rate OUT UINT64 *Rate
@ -199,20 +199,19 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_CLOCK_RATE_SET) ( (EFIAPI *SCMI_CLOCK_RATE_SET)(
IN SCMI_CLOCK_PROTOCOL *This, IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId, IN UINT32 ClockId,
IN UINT64 Rate IN UINT64 Rate
); );
typedef struct _SCMI_CLOCK_PROTOCOL { typedef struct _SCMI_CLOCK_PROTOCOL {
SCMI_CLOCK_GET_VERSION GetVersion; SCMI_CLOCK_GET_VERSION GetVersion;
SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks; SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;
SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes; SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;
SCMI_CLOCK_DESCRIBE_RATES DescribeRates; SCMI_CLOCK_DESCRIBE_RATES DescribeRates;
SCMI_CLOCK_RATE_GET RateGet; SCMI_CLOCK_RATE_GET RateGet;
SCMI_CLOCK_RATE_SET RateSet; SCMI_CLOCK_RATE_SET RateSet;
} SCMI_CLOCK_PROTOCOL; } SCMI_CLOCK_PROTOCOL;
#endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */ #endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */

81
ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
View File

@ -20,15 +20,15 @@
0x9b8ba84, 0x3dd3, 0x49a6, {0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad} \ 0x9b8ba84, 0x3dd3, 0x49a6, {0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad} \
} }
extern EFI_GUID gArmScmiPerformanceProtocolGuid; extern EFI_GUID gArmScmiPerformanceProtocolGuid;
typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL; typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL;
#pragma pack(1) #pragma pack(1)
#define POWER_IN_MW_SHIFT 16 #define POWER_IN_MW_SHIFT 16
#define POWER_IN_MW_MASK 0x1 #define POWER_IN_MW_MASK 0x1
#define NUM_PERF_DOMAINS_MASK 0xFFFF #define NUM_PERF_DOMAINS_MASK 0xFFFF
// Total number of performance domains, Attr Bits [15:0] // Total number of performance domains, Attr Bits [15:0]
#define SCMI_PERF_TOTAL_DOMAINS(Attr) (Attr & NUM_PERF_DOMAINS_MASK) #define SCMI_PERF_TOTAL_DOMAINS(Attr) (Attr & NUM_PERF_DOMAINS_MASK)
@ -39,41 +39,41 @@ typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL;
// Performance protocol attributes return values. // Performance protocol attributes return values.
typedef struct { typedef struct {
UINT32 Attributes; UINT32 Attributes;
UINT64 StatisticsAddress; UINT64 StatisticsAddress;
UINT32 StatisticsLen; UINT32 StatisticsLen;
} SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES; } SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES;
#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1) #define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)
#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1) #define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)
#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1) #define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)
#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1) #define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)
#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF) #define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)
// Performance protocol domain attributes. // Performance protocol domain attributes.
typedef struct { typedef struct {
UINT32 Attributes; UINT32 Attributes;
UINT32 RateLimit; UINT32 RateLimit;
UINT32 SustainedFreq; UINT32 SustainedFreq;
UINT32 SustainedPerfLevel; UINT32 SustainedPerfLevel;
UINT8 Name[SCMI_MAX_STR_LEN]; UINT8 Name[SCMI_MAX_STR_LEN];
} SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES; } SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES;
// Worst case latency in microseconds, Bits[15:0] // Worst case latency in microseconds, Bits[15:0]
#define PERF_LATENCY_MASK 0xFFFF #define PERF_LATENCY_MASK 0xFFFF
#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK) #define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)
// Performance protocol performance level. // Performance protocol performance level.
typedef struct { typedef struct {
UINT32 Level; UINT32 Level;
UINT32 PowerCost; UINT32 PowerCost;
UINT32 Latency; UINT32 Latency;
} SCMI_PERFORMANCE_LEVEL; } SCMI_PERFORMANCE_LEVEL;
// Performance protocol performance limit. // Performance protocol performance limit.
typedef struct { typedef struct {
UINT32 RangeMax; UINT32 RangeMax;
UINT32 RangeMin; UINT32 RangeMin;
} SCMI_PERFORMANCE_LIMITS; } SCMI_PERFORMANCE_LIMITS;
#pragma pack() #pragma pack()
@ -92,7 +92,7 @@ typedef struct {
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_GET_VERSION) ( (EFIAPI *SCMI_PERFORMANCE_GET_VERSION)(
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT UINT32 *Version OUT UINT32 *Version
); );
@ -109,7 +109,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES) ( (EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES)(
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
@ -128,7 +128,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES) ( (EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES)(
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
@ -153,7 +153,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS) ( (EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS)(
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
OUT UINT32 *NumLevels, OUT UINT32 *NumLevels,
@ -173,7 +173,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET) ( (EFIAPI *SCMI_PERFORMANCE_LIMITS_SET)(
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
IN SCMI_PERFORMANCE_LIMITS *Limits IN SCMI_PERFORMANCE_LIMITS *Limits
@ -192,7 +192,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET) ( (EFIAPI *SCMI_PERFORMANCE_LIMITS_GET)(
SCMI_PERFORMANCE_PROTOCOL *This, SCMI_PERFORMANCE_PROTOCOL *This,
UINT32 DomainId, UINT32 DomainId,
SCMI_PERFORMANCE_LIMITS *Limits SCMI_PERFORMANCE_LIMITS *Limits
@ -210,7 +210,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET) ( (EFIAPI *SCMI_PERFORMANCE_LEVEL_SET)(
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
IN UINT32 Level IN UINT32 Level
@ -229,21 +229,21 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET) ( (EFIAPI *SCMI_PERFORMANCE_LEVEL_GET)(
IN SCMI_PERFORMANCE_PROTOCOL *This, IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId, IN UINT32 DomainId,
OUT UINT32 *Level OUT UINT32 *Level
); );
typedef struct _SCMI_PERFORMANCE_PROTOCOL { typedef struct _SCMI_PERFORMANCE_PROTOCOL {
SCMI_PERFORMANCE_GET_VERSION GetVersion; SCMI_PERFORMANCE_GET_VERSION GetVersion;
SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes; SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;
SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes; SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;
SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels; SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;
SCMI_PERFORMANCE_LIMITS_SET LimitsSet; SCMI_PERFORMANCE_LIMITS_SET LimitsSet;
SCMI_PERFORMANCE_LIMITS_GET LimitsGet; SCMI_PERFORMANCE_LIMITS_GET LimitsGet;
SCMI_PERFORMANCE_LEVEL_SET LevelSet; SCMI_PERFORMANCE_LEVEL_SET LevelSet;
SCMI_PERFORMANCE_LEVEL_GET LevelGet; SCMI_PERFORMANCE_LEVEL_GET LevelGet;
} SCMI_PERFORMANCE_PROTOCOL; } SCMI_PERFORMANCE_PROTOCOL;
typedef enum { typedef enum {
@ -256,4 +256,3 @@ typedef enum {
} SCMI_MESSAGE_ID_PERFORMANCE; } SCMI_MESSAGE_ID_PERFORMANCE;
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */ #endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */

46
ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
View File

@ -7,7 +7,6 @@
**/ **/
#include <Base.h> #include <Base.h>
#include <Library/ArmLib.h> #include <Library/ArmLib.h>
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
@ -16,16 +15,15 @@
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/ArmGenericTimerCounterLib.h> #include <Library/ArmGenericTimerCounterLib.h>
#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U) #define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)
// Select appropriate multiply function for platform architecture. // Select appropriate multiply function for platform architecture.
#ifdef MDE_CPU_ARM #ifdef MDE_CPU_ARM
#define MULT_U64_X_N MultU64x32 #define MULT_U64_X_N MultU64x32
#else #else
#define MULT_U64_X_N MultU64x64 #define MULT_U64_X_N MultU64x64
#endif #endif
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
TimerConstructor ( TimerConstructor (
@ -36,7 +34,6 @@ TimerConstructor (
// Check if the ARM Generic Timer Extension is implemented. // Check if the ARM Generic Timer Extension is implemented.
// //
if (ArmIsArchTimerImplemented ()) { if (ArmIsArchTimerImplemented ()) {
// //
// Check if Architectural Timer frequency is pre-determined by the platform // Check if Architectural Timer frequency is pre-determined by the platform
// (ie. nonzero). // (ie. nonzero).
@ -49,7 +46,7 @@ TimerConstructor (
// //
ASSERT (TICKS_PER_MICRO_SEC); ASSERT (TICKS_PER_MICRO_SEC);
#ifdef MDE_CPU_ARM #ifdef MDE_CPU_ARM
// //
// Only set the frequency for ARMv7. We expect the secure firmware to // Only set the frequency for ARMv7. We expect the secure firmware to
// have already done it. // have already done it.
@ -59,7 +56,8 @@ TimerConstructor (
if (ArmHasSecurityExtensions ()) { if (ArmHasSecurityExtensions ()) {
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz)); ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
} }
#endif
#endif
} }
// //
@ -68,7 +66,6 @@ TimerConstructor (
// If the reset value (0) is returned, just ASSERT. // If the reset value (0) is returned, just ASSERT.
// //
ASSERT (ArmGenericTimerGetTimerFreq () != 0); ASSERT (ArmGenericTimerGetTimerFreq () != 0);
} else { } else {
DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n")); DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n"));
ASSERT (0); ASSERT (0);
@ -90,16 +87,16 @@ EFIAPI
GetPlatformTimerFreq ( GetPlatformTimerFreq (
) )
{ {
UINTN TimerFreq; UINTN TimerFreq;
TimerFreq = PcdGet32 (PcdArmArchTimerFreqInHz); TimerFreq = PcdGet32 (PcdArmArchTimerFreqInHz);
if (TimerFreq == 0) { if (TimerFreq == 0) {
TimerFreq = ArmGenericTimerGetTimerFreq (); TimerFreq = ArmGenericTimerGetTimerFreq ();
} }
return TimerFreq; return TimerFreq;
} }
/** /**
Stalls the CPU for the number of microseconds specified by MicroSeconds. Stalls the CPU for the number of microseconds specified by MicroSeconds.
@ -111,11 +108,11 @@ GetPlatformTimerFreq (
UINTN UINTN
EFIAPI EFIAPI
MicroSecondDelay ( MicroSecondDelay (
IN UINTN MicroSeconds IN UINTN MicroSeconds
) )
{ {
UINT64 TimerTicks64; UINT64 TimerTicks64;
UINT64 SystemCounterVal; UINT64 SystemCounterVal;
// Calculate counter ticks that represent requested delay: // Calculate counter ticks that represent requested delay:
// = MicroSeconds x TICKS_PER_MICRO_SEC // = MicroSeconds x TICKS_PER_MICRO_SEC
@ -141,7 +138,6 @@ MicroSecondDelay (
return MicroSeconds; return MicroSeconds;
} }
/** /**
Stalls the CPU for at least the given number of nanoseconds. Stalls the CPU for at least the given number of nanoseconds.
@ -158,13 +154,13 @@ MicroSecondDelay (
UINTN UINTN
EFIAPI EFIAPI
NanoSecondDelay ( NanoSecondDelay (
IN UINTN NanoSeconds IN UINTN NanoSeconds
) )
{ {
UINTN MicroSeconds; UINTN MicroSeconds;
// Round up to 1us Tick Number // Round up to 1us Tick Number
MicroSeconds = NanoSeconds / 1000; MicroSeconds = NanoSeconds / 1000;
MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1; MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;
MicroSecondDelay (MicroSeconds); MicroSecondDelay (MicroSeconds);
@ -219,13 +215,13 @@ GetPerformanceCounter (
UINT64 UINT64
EFIAPI EFIAPI
GetPerformanceCounterProperties ( GetPerformanceCounterProperties (
OUT UINT64 *StartValue OPTIONAL, OUT UINT64 *StartValue OPTIONAL,
OUT UINT64 *EndValue OPTIONAL OUT UINT64 *EndValue OPTIONAL
) )
{ {
if (StartValue != NULL) { if (StartValue != NULL) {
// Timer starts at 0 // Timer starts at 0
*StartValue = (UINT64)0ULL ; *StartValue = (UINT64)0ULL;
} }
if (EndValue != NULL) { if (EndValue != NULL) {
@ -250,7 +246,7 @@ GetPerformanceCounterProperties (
UINT64 UINT64
EFIAPI EFIAPI
GetTimeInNanoSecond ( GetTimeInNanoSecond (
IN UINT64 Ticks IN UINT64 Ticks
) )
{ {
UINT64 NanoSeconds; UINT64 NanoSeconds;
@ -267,7 +263,8 @@ GetTimeInNanoSecond (
DivU64x32Remainder ( DivU64x32Remainder (
Ticks, Ticks,
TimerFreq, TimerFreq,
&Remainder), &Remainder
),
1000000000U 1000000000U
); );
@ -277,8 +274,9 @@ GetTimeInNanoSecond (
// //
NanoSeconds += DivU64x32 ( NanoSeconds += DivU64x32 (
MULT_U64_X_N ( MULT_U64_X_N (
(UINT64) Remainder, (UINT64)Remainder,
1000000000U), 1000000000U
),
TimerFreq TimerFreq
); );

68
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
View File

@ -20,20 +20,21 @@ CacheRangeOperation (
IN UINTN LineLength IN UINTN LineLength
) )
{ {
UINTN ArmCacheLineAlignmentMask; UINTN ArmCacheLineAlignmentMask;
// Align address (rounding down) // Align address (rounding down)
UINTN AlignedAddress; UINTN AlignedAddress;
UINTN EndAddress; UINTN EndAddress;
ArmCacheLineAlignmentMask = LineLength - 1; ArmCacheLineAlignmentMask = LineLength - 1;
AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask); AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
EndAddress = (UINTN)Start + Length; EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line // Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) { while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress); LineOperation (AlignedAddress);
AlignedAddress += LineLength; AlignedAddress += LineLength;
} }
ArmDataSynchronizationBarrier (); ArmDataSynchronizationBarrier ();
} }
@ -58,15 +59,22 @@ InvalidateDataCache (
VOID * VOID *
EFIAPI EFIAPI
InvalidateInstructionCacheRange ( InvalidateInstructionCacheRange (
IN VOID *Address, IN VOID *Address,
IN UINTN Length IN UINTN Length
) )
{ {
CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA, CacheRangeOperation (
ArmDataCacheLineLength ()); Address,
CacheRangeOperation (Address, Length, Length,
ArmCleanDataCacheEntryToPoUByMVA,
ArmDataCacheLineLength ()
);
CacheRangeOperation (
Address,
Length,
ArmInvalidateInstructionCacheEntryToPoUByMVA, ArmInvalidateInstructionCacheEntryToPoUByMVA,
ArmInstructionCacheLineLength ()); ArmInstructionCacheLineLength ()
);
ArmInstructionSynchronizationBarrier (); ArmInstructionSynchronizationBarrier ();
@ -85,12 +93,16 @@ WriteBackInvalidateDataCache (
VOID * VOID *
EFIAPI EFIAPI
WriteBackInvalidateDataCacheRange ( WriteBackInvalidateDataCacheRange (
IN VOID *Address, IN VOID *Address,
IN UINTN Length IN UINTN Length
) )
{ {
CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA, CacheRangeOperation (
ArmDataCacheLineLength ()); Address,
Length,
ArmCleanInvalidateDataCacheEntryByMVA,
ArmDataCacheLineLength ()
);
return Address; return Address;
} }
@ -106,23 +118,31 @@ WriteBackDataCache (
VOID * VOID *
EFIAPI EFIAPI
WriteBackDataCacheRange ( WriteBackDataCacheRange (
IN VOID *Address, IN VOID *Address,
IN UINTN Length IN UINTN Length
) )
{ {
CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA, CacheRangeOperation (
ArmDataCacheLineLength ()); Address,
Length,
ArmCleanDataCacheEntryByMVA,
ArmDataCacheLineLength ()
);
return Address; return Address;
} }
VOID * VOID *
EFIAPI EFIAPI
InvalidateDataCacheRange ( InvalidateDataCacheRange (
IN VOID *Address, IN VOID *Address,
IN UINTN Length IN UINTN Length
) )
{ {
CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA, CacheRangeOperation (
ArmDataCacheLineLength ()); Address,
Length,
ArmInvalidateDataCacheEntryByMVA,
ArmDataCacheLineLength ()
);
return Address; return Address;
} }

12
ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c
View File

@ -26,12 +26,12 @@
**/ **/
VOID VOID
DisassembleInstruction ( DisassembleInstruction (
IN UINT8 **OpCodePtr, IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb, IN BOOLEAN Thumb,
IN BOOLEAN Extended, IN BOOLEAN Extended,
IN OUT UINT32 *ItBlock, IN OUT UINT32 *ItBlock,
OUT CHAR8 *Buf, OUT CHAR8 *Buf,
OUT UINTN Size OUT UINTN Size
) )
{ {
// Not yet supported for AArch64. // Not yet supported for AArch64.

150
ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c
View File

@ -13,7 +13,7 @@
#include <Library/PrintLib.h> #include <Library/PrintLib.h>
#include <Library/ArmDisassemblerLib.h> #include <Library/ArmDisassemblerLib.h>
CHAR8 *gCondition[] = { CHAR8 *gCondition[] = {
"EQ", "EQ",
"NE", "NE",
"CS", "CS",
@ -34,7 +34,7 @@ CHAR8 *gCondition[] = {
#define COND(_a) gCondition[((_a) >> 28)] #define COND(_a) gCondition[((_a) >> 28)]
CHAR8 *gReg[] = { CHAR8 *gReg[] = {
"r0", "r0",
"r1", "r1",
"r2", "r2",
@ -53,37 +53,36 @@ CHAR8 *gReg[] = {
"pc" "pc"
}; };
CHAR8 *gLdmAdr[] = { CHAR8 *gLdmAdr[] = {
"DA", "DA",
"IA", "IA",
"DB", "DB",
"IB" "IB"
}; };
CHAR8 *gLdmStack[] = { CHAR8 *gLdmStack[] = {
"FA", "FA",
"FD", "FD",
"EA", "EA",
"ED" "ED"
}; };
#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)]) #define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
#define SIGN(_U) ((_U) ? "" : "-")
#define WRITE(_Write) ((_Write) ? "!" : "")
#define BYTE(_B) ((_B) ? "B":"")
#define USER(_B) ((_B) ? "^" : "")
#define SIGN(_U) ((_U) ? "" : "-") CHAR8 mMregListStr[4*15 + 1];
#define WRITE(_Write) ((_Write) ? "!" : "")
#define BYTE(_B) ((_B) ? "B":"")
#define USER(_B) ((_B) ? "^" : "")
CHAR8 mMregListStr[4*15 + 1];
CHAR8 * CHAR8 *
MRegList ( MRegList (
UINT32 OpCode UINT32 OpCode
) )
{ {
UINTN Index, Start, End; UINTN Index, Start, End;
BOOLEAN First; BOOLEAN First;
mMregListStr[0] = '\0'; mMregListStr[0] = '\0';
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{"); AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{");
@ -110,9 +109,11 @@ MRegList (
} }
} }
} }
if (First) { if (First) {
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR"); AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR");
} }
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}"); AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}");
// BugBug: Make caller pass in buffer it is cleaner // BugBug: Make caller pass in buffer it is cleaner
@ -129,14 +130,13 @@ FieldMask (
UINT32 UINT32
RotateRight ( RotateRight (
IN UINT32 Op, IN UINT32 Op,
IN UINT32 Shift IN UINT32 Shift
) )
{ {
return (Op >> Shift) | (Op << (32 - Shift)); return (Op >> Shift) | (Op << (32 - Shift));
} }
/** /**
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction. point to next instruction.
@ -152,39 +152,38 @@ RotateRight (
**/ **/
VOID VOID
DisassembleArmInstruction ( DisassembleArmInstruction (
IN UINT32 **OpCodePtr, IN UINT32 **OpCodePtr,
OUT CHAR8 *Buf, OUT CHAR8 *Buf,
OUT UINTN Size, OUT UINTN Size,
IN BOOLEAN Extended IN BOOLEAN Extended
) )
{ {
UINT32 OpCode; UINT32 OpCode;
CHAR8 *Type; CHAR8 *Type;
CHAR8 *Root; CHAR8 *Root;
BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half; BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
UINT32 Rn, Rd, Rm; UINT32 Rn, Rd, Rm;
UINT32 IMod, Offset8, Offset12; UINT32 IMod, Offset8, Offset12;
UINT32 Index; UINT32 Index;
UINT32 ShiftImm, Shift; UINT32 ShiftImm, Shift;
OpCode = **OpCodePtr; OpCode = **OpCodePtr;
Imm = (OpCode & BIT25) == BIT25; // I Imm = (OpCode & BIT25) == BIT25; // I
Pre = (OpCode & BIT24) == BIT24; // P Pre = (OpCode & BIT24) == BIT24; // P
Up = (OpCode & BIT23) == BIT23; // U Up = (OpCode & BIT23) == BIT23; // U
WriteBack = (OpCode & BIT22) == BIT22; // B, also called S WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
Write = (OpCode & BIT21) == BIT21; // W Write = (OpCode & BIT21) == BIT21; // W
Load = (OpCode & BIT20) == BIT20; // L Load = (OpCode & BIT20) == BIT20; // L
Sign = (OpCode & BIT6) == BIT6; // S Sign = (OpCode & BIT6) == BIT6; // S
Half = (OpCode & BIT5) == BIT5; // H Half = (OpCode & BIT5) == BIT5; // H
Rn = (OpCode >> 16) & 0xf; Rn = (OpCode >> 16) & 0xf;
Rd = (OpCode >> 12) & 0xf; Rd = (OpCode >> 12) & 0xf;
Rm = (OpCode & 0xf); Rm = (OpCode & 0xf);
if (Extended) { if (Extended) {
Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode); Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode);
Buf += Index; Buf += Index;
Size -= Index; Size -= Index;
} }
@ -194,9 +193,10 @@ DisassembleArmInstruction (
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>] // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]); AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
} else { } else {
// A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>] // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]); AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
} }
return; return;
} }
@ -206,23 +206,25 @@ DisassembleArmInstruction (
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers> // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^ // A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^ // A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack)); AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
} else { } else {
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers> // A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^ // A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack)); AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
} }
return; return;
} }
// LDR/STR Address Mode 2 // LDR/STR Address Mode 2
if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) { if (((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000) == 0xf550f000)) {
Offset12 = OpCode & 0xfff; Offset12 = OpCode & 0xfff;
if ((OpCode & 0xfd70f000 ) == 0xf550f000) { if ((OpCode & 0xfd70f000) == 0xf550f000) {
Index = AsciiSPrint (Buf, Size, "PLD"); Index = AsciiSPrint (Buf, Size, "PLD");
} else { } else {
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]); Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T" : "", gReg[Rd]);
} }
if (Pre) { if (Pre) {
if (!Imm) { if (!Imm) {
// A5.2.2 [<Rn>, #+/-<offset_12>] // A5.2.2 [<Rn>, #+/-<offset_12>]
@ -236,7 +238,7 @@ DisassembleArmInstruction (
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>] // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]! // A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
ShiftImm = (OpCode >> 7) & 0x1f; ShiftImm = (OpCode >> 7) & 0x1f;
Shift = (OpCode >> 5) & 0x3; Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) { if (Shift == 0x0) {
Type = "LSL"; Type = "LSL";
} else if (Shift == 0x1) { } else if (Shift == 0x1) {
@ -255,7 +257,8 @@ DisassembleArmInstruction (
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
} }
} else { // !Pre } else {
// !Pre
if (!Imm) { if (!Imm) {
// A5.2.8 [<Rn>], #+/-<offset_12> // A5.2.8 [<Rn>], #+/-<offset_12>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
@ -265,7 +268,7 @@ DisassembleArmInstruction (
} else { } else {
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm> // A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
ShiftImm = (OpCode >> 7) & 0x1f; ShiftImm = (OpCode >> 7) & 0x1f;
Shift = (OpCode >> 5) & 0x3; Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) { if (Shift == 0x0) {
Type = "LSL"; Type = "LSL";
@ -287,6 +290,7 @@ DisassembleArmInstruction (
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
} }
} }
return; return;
} }
@ -313,30 +317,31 @@ DisassembleArmInstruction (
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]); Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
Sign = (OpCode & BIT6) == BIT6; Sign = (OpCode & BIT6) == BIT6;
Half = (OpCode & BIT5) == BIT5; Half = (OpCode & BIT5) == BIT5;
Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff; Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
if (Pre & !Write) { if (Pre & !Write) {
// Immediate offset/index // Immediate offset/index
if (WriteBack) { if (WriteBack) {
// A5.3.2 [<Rn>, #+/-<offset_8>] // A5.3.2 [<Rn>, #+/-<offset_8>]
// A5.3.4 [<Rn>, #+/-<offset_8>]! // A5.3.4 [<Rn>, #+/-<offset_8>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
} else { } else {
// A5.3.3 [<Rn>, +/-<Rm>] // A5.3.3 [<Rn>, +/-<Rm>]
// A5.3.5 [<Rn>, +/-<Rm>]! // A5.3.5 [<Rn>, +/-<Rm>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
} }
} else { } else {
// Register offset/index // Register offset/index
if (WriteBack) { if (WriteBack) {
// A5.3.6 [<Rn>], #+/-<offset_8> // A5.3.6 [<Rn>], #+/-<offset_8>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
} else { } else {
// A5.3.7 [<Rn>], +/-<Rm> // A5.3.7 [<Rn>], +/-<Rm>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
} }
} }
return; return;
} }
@ -370,16 +375,21 @@ DisassembleArmInstruction (
if (((OpCode >> 6) & 0x7) == 0) { if (((OpCode >> 6) & 0x7) == 0) {
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f)); AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
} else { } else {
IMod = (OpCode >> 18) & 0x3; IMod = (OpCode >> 18) & 0x3;
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", Index = AsciiSPrint (
(IMod == 3) ? "ID":"IE", Buf,
((OpCode & BIT8) != 0) ? "A":"", Size,
((OpCode & BIT7) != 0) ? "I":"", "CPS%a %a%a%a",
((OpCode & BIT6) != 0) ? "F":""); (IMod == 3) ? "ID" : "IE",
((OpCode & BIT8) != 0) ? "A" : "",
((OpCode & BIT7) != 0) ? "I" : "",
((OpCode & BIT6) != 0) ? "F" : ""
);
if ((OpCode & BIT17) != 0) { if ((OpCode & BIT17) != 0) {
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f); AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
} }
} }
return; return;
} }
@ -395,16 +405,16 @@ DisassembleArmInstruction (
return; return;
} }
if ((OpCode & 0x0db00000) == 0x01200000) { if ((OpCode & 0x0db00000) == 0x01200000) {
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm> // A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
if (Imm) { if (Imm) {
// MSR{<cond>} CPSR_<fields>, #<immediate> // MSR{<cond>} CPSR_<fields>, #<immediate>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2)); AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
} else { } else {
// MSR{<cond>} CPSR_<fields>, <Rm> // MSR{<cond>} CPSR_<fields>, <Rm>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]); AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
} }
return; return;
} }
@ -417,35 +427,34 @@ DisassembleArmInstruction (
if ((OpCode & 0x0e000000) == 0x0c000000) { if ((OpCode & 0x0e000000) == 0x0c000000) {
// A4.1.19 LDC and A4.1.96 SDC // A4.1.19 LDC and A4.1.96 SDC
if ((OpCode & 0xf0000000) == 0xf0000000) { if ((OpCode & 0xf0000000) == 0xf0000000) {
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd); Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC" : "SDC", (OpCode >> 8) & 0xf, Rd);
} else { } else {
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd); Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC" : "SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
} }
if (!Pre) { if (!Pre) {
if (!Write) { if (!Write) {
// A5.5.5.5 [<Rn>], <option> // A5.5.5.5 [<Rn>], <option>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff); AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
} else { } else {
// A.5.5.4 [<Rn>], #+/-<offset_8>*4 // A.5.5.4 [<Rn>], #+/-<offset_8>*4
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
} }
} else { } else {
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]! // A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
} }
} }
if ((OpCode & 0x0f000010) == 0x0e000010) { if ((OpCode & 0x0f000010) == 0x0e000010) {
// A4.1.32 MRC2, MCR2 // A4.1.32 MRC2, MCR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7); AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC" : "MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
return; return;
} }
if ((OpCode & 0x0ff00000) == 0x0c400000) { if ((OpCode & 0x0ff00000) == 0x0c400000) {
// A4.1.33 MRRC2, MCRR2 // A4.1.33 MRRC2, MCRR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm); AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC" : "MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
return; return;
} }
@ -454,4 +463,3 @@ DisassembleArmInstruction (
*OpCodePtr += 1; *OpCodePtr += 1;
return; return;
} }

1505
ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c
View File

File diff suppressed because it is too large Load Diff

22
ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c
View File

@ -14,39 +14,39 @@
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
#include <Protocol/DebugSupport.h> // for MAX_AARCH64_EXCEPTION #include <Protocol/DebugSupport.h> // for MAX_AARCH64_EXCEPTION
UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION; UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;
EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 }; EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 }; EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT; PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64 UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
#define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2) #define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2)
STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)]; STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
VOID VOID
RegisterEl0Stack ( RegisterEl0Stack (
IN VOID *Stack IN VOID *Stack
); );
RETURN_STATUS RETURN_STATUS
ArchVectorConfig ( ArchVectorConfig (
IN UINTN VectorBaseAddress IN UINTN VectorBaseAddress
) )
{ {
UINTN HcrReg; UINTN HcrReg;
// Round down sp by 16 bytes alignment // Round down sp by 16 bytes alignment
RegisterEl0Stack ( RegisterEl0Stack (
(VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL) (VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)
); );
if (ArmReadCurrentEL() == AARCH64_EL2) { if (ArmReadCurrentEL () == AARCH64_EL2) {
HcrReg = ArmReadHcr(); HcrReg = ArmReadHcr ();
// Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2 // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2
HcrReg |= ARM_HCR_TGE; HcrReg |= ARM_HCR_TGE;
ArmWriteHcr(HcrReg); ArmWriteHcr (HcrReg);
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;

17
ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c
View File

@ -17,28 +17,27 @@
#include <Protocol/DebugSupport.h> // for MAX_ARM_EXCEPTION #include <Protocol/DebugSupport.h> // for MAX_ARM_EXCEPTION
UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION; UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;
EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 }; EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 }; EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT; PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
// Exception handler contains branch to vector location (jmp $) so no handler // Exception handler contains branch to vector location (jmp $) so no handler
// NOTE: This code assumes vectors are ARM and not Thumb code // NOTE: This code assumes vectors are ARM and not Thumb code
UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE; UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
RETURN_STATUS RETURN_STATUS
ArchVectorConfig ( ArchVectorConfig (
IN UINTN VectorBaseAddress IN UINTN VectorBaseAddress
) )
{ {
// if the vector address corresponds to high vectors // if the vector address corresponds to high vectors
if (VectorBaseAddress == 0xFFFF0000) { if (VectorBaseAddress == 0xFFFF0000) {
// set SCTLR.V to enable high vectors // set SCTLR.V to enable high vectors
ArmSetHighVectors(); ArmSetHighVectors ();
} } else {
else {
// Set SCTLR.V to 0 to enable VBAR to be used // Set SCTLR.V to 0 to enable VBAR to be used
ArmSetLowVectors(); ArmSetLowVectors ();
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;

135
ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c
View File

@ -22,37 +22,38 @@
STATIC STATIC
RETURN_STATUS RETURN_STATUS
CopyExceptionHandlers( CopyExceptionHandlers (
IN PHYSICAL_ADDRESS BaseAddress IN PHYSICAL_ADDRESS BaseAddress
); );
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
RegisterExceptionHandler( RegisterExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
); );
VOID VOID
ExceptionHandlersStart( ExceptionHandlersStart (
VOID VOID
); );
VOID VOID
ExceptionHandlersEnd( ExceptionHandlersEnd (
VOID VOID
); );
RETURN_STATUS ArchVectorConfig( RETURN_STATUS
IN UINTN VectorBaseAddress ArchVectorConfig (
IN UINTN VectorBaseAddress
); );
// these globals are provided by the architecture specific source (Arm or AArch64) // these globals are provided by the architecture specific source (Arm or AArch64)
extern UINTN gMaxExceptionNumber; extern UINTN gMaxExceptionNumber;
extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[]; extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];
extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[]; extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];
extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask; extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;
extern UINTN gDebuggerNoHandlerValue; extern UINTN gDebuggerNoHandlerValue;
// A compiler flag adjusts the compilation of this library to a variant where // A compiler flag adjusts the compilation of this library to a variant where
// the vectors are relocated (copied) to another location versus using the // the vectors are relocated (copied) to another location versus using the
@ -60,13 +61,12 @@ extern UINTN gDebuggerNoHandlerValue;
// address this at library build time. Since this affects the build of the // address this at library build time. Since this affects the build of the
// library we cannot represent this in a PCD since PCDs are evaluated on // library we cannot represent this in a PCD since PCDs are evaluated on
// a per-module basis. // a per-module basis.
#if defined(ARM_RELOCATE_VECTORS) #if defined (ARM_RELOCATE_VECTORS)
STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE; STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;
#else #else
STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE; STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;
#endif #endif
/** /**
Initializes all CPU exceptions entries and provides the default exception handlers. Initializes all CPU exceptions entries and provides the default exception handlers.
@ -85,23 +85,21 @@ with default exception handlers.
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlers( InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
RETURN_STATUS Status; RETURN_STATUS Status;
UINTN VectorBase; UINTN VectorBase;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
// if we are requested to copy exception handlers to another location // if we are requested to copy exception handlers to another location
if (gArmRelocateVectorTable) { if (gArmRelocateVectorTable) {
VectorBase = PcdGet64 (PcdCpuVectorBaseAddress);
VectorBase = PcdGet64(PcdCpuVectorBaseAddress); Status = CopyExceptionHandlers (VectorBase);
Status = CopyExceptionHandlers(VectorBase); } else {
// use VBAR to point to where our exception handlers are
}
else { // use VBAR to point to where our exception handlers are
// The vector table must be aligned for the architecture. If this // The vector table must be aligned for the architecture. If this
// assertion fails ensure the appropriate FFS alignment is in effect, // assertion fails ensure the appropriate FFS alignment is in effect,
@ -110,7 +108,7 @@ InitializeCpuExceptionHandlers(
// for AArch64 Align=4K is required. Align=Auto can be used but this // for AArch64 Align=4K is required. Align=Auto can be used but this
// is known to cause an issue with populating the reset vector area // is known to cause an issue with populating the reset vector area
// for encapsulated FVs. // for encapsulated FVs.
ASSERT(((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0); ASSERT (((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);
// We do not copy the Exception Table at PcdGet64(PcdCpuVectorBaseAddress). We just set Vector // We do not copy the Exception Table at PcdGet64(PcdCpuVectorBaseAddress). We just set Vector
// Base Address to point into CpuDxe code. // Base Address to point into CpuDxe code.
@ -119,12 +117,12 @@ InitializeCpuExceptionHandlers(
Status = RETURN_SUCCESS; Status = RETURN_SUCCESS;
} }
if (!RETURN_ERROR(Status)) { if (!RETURN_ERROR (Status)) {
// call the architecture-specific routine to prepare for the new vector // call the architecture-specific routine to prepare for the new vector
// configuration to take effect // configuration to take effect
ArchVectorConfig(VectorBase); ArchVectorConfig (VectorBase);
ArmWriteVBar(VectorBase); ArmWriteVBar (VectorBase);
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;
@ -148,14 +146,14 @@ with default exception handlers.
**/ **/
STATIC STATIC
RETURN_STATUS RETURN_STATUS
CopyExceptionHandlers( CopyExceptionHandlers (
IN PHYSICAL_ADDRESS BaseAddress IN PHYSICAL_ADDRESS BaseAddress
) )
{ {
RETURN_STATUS Status; RETURN_STATUS Status;
UINTN Length; UINTN Length;
UINTN Index; UINTN Index;
UINT32 *VectorBase; UINT32 *VectorBase;
// ensure that the destination value specifies an address meeting the vector alignment requirements // ensure that the destination value specifies an address meeting the vector alignment requirements
ASSERT ((BaseAddress & gExceptionVectorAlignmentMask) == 0); ASSERT ((BaseAddress & gExceptionVectorAlignmentMask) == 0);
@ -167,37 +165,35 @@ CopyExceptionHandlers(
VectorBase = (UINT32 *)(UINTN)BaseAddress; VectorBase = (UINT32 *)(UINTN)BaseAddress;
if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) { if (FeaturePcdGet (PcdDebuggerExceptionSupport) == TRUE) {
// Save existing vector table, in case debugger is already hooked in // Save existing vector table, in case debugger is already hooked in
CopyMem((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1)); CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));
} }
// Copy our assembly code into the page that contains the exception vectors. // Copy our assembly code into the page that contains the exception vectors.
CopyMem((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length); CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
// //
// Initialize the C entry points for interrupts // Initialize the C entry points for interrupts
// //
for (Index = 0; Index <= gMaxExceptionNumber; Index++) { for (Index = 0; Index <= gMaxExceptionNumber; Index++) {
if (!FeaturePcdGet(PcdDebuggerExceptionSupport) || if (!FeaturePcdGet (PcdDebuggerExceptionSupport) ||
(gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue)) { (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue))
{
Status = RegisterExceptionHandler(Index, NULL); Status = RegisterExceptionHandler (Index, NULL);
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR (Status);
} } else {
else {
// If the debugger has already hooked put its vector back // If the debugger has already hooked put its vector back
VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index]; VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];
} }
} }
// Flush Caches since we updated executable stuff // Flush Caches since we updated executable stuff
InvalidateInstructionCacheRange((VOID *)(UINTN)BaseAddress, Length); InvalidateInstructionCacheRange ((VOID *)(UINTN)BaseAddress, Length);
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
/** /**
Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers. Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
@ -216,9 +212,9 @@ with default interrupt/exception handlers.
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuInterruptHandlers( InitializeCpuInterruptHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
// not needed, this is what the CPU driver is for // not needed, this is what the CPU driver is for
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@ -250,9 +246,9 @@ previously installed.
or this function is not supported. or this function is not supported.
**/ **/
RETURN_STATUS RETURN_STATUS
RegisterCpuInterruptHandler( RegisterCpuInterruptHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
) )
{ {
if (ExceptionType > gMaxExceptionNumber) { if (ExceptionType > gMaxExceptionNumber) {
@ -287,19 +283,19 @@ If this parameter is NULL, then the handler will be uninstalled.
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
RegisterExceptionHandler( RegisterExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
) )
{ {
return RegisterCpuInterruptHandler(ExceptionType, InterruptHandler); return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler);
} }
VOID VOID
EFIAPI EFIAPI
CommonCExceptionHandler( CommonCExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN OUT EFI_SYSTEM_CONTEXT SystemContext IN OUT EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
if (ExceptionType <= gMaxExceptionNumber) { if (ExceptionType <= gMaxExceptionNumber) {
@ -307,13 +303,12 @@ CommonCExceptionHandler(
gExceptionHandlers[ExceptionType](ExceptionType, SystemContext); gExceptionHandlers[ExceptionType](ExceptionType, SystemContext);
return; return;
} }
} } else {
else { DEBUG ((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType));
DEBUG((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType)); ASSERT (FALSE);
ASSERT(FALSE);
} }
DefaultExceptionHandler(ExceptionType, SystemContext); DefaultExceptionHandler (ExceptionType, SystemContext);
} }
/** /**
@ -341,8 +336,8 @@ CommonCExceptionHandler(
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlersEx ( InitializeCpuExceptionHandlersEx (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
) )
{ {
return InitializeCpuExceptionHandlers (VectorInfo); return InitializeCpuExceptionHandlers (VectorInfo);

15
ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c
View File

@ -16,9 +16,9 @@ ArmGenericTimerEnableTimer (
VOID VOID
) )
{ {
UINTN TimerCtrlReg; UINTN TimerCtrlReg;
TimerCtrlReg = ArmReadCntpCtl (); TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE; TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmWriteCntpCtl (TimerCtrlReg); ArmWriteCntpCtl (TimerCtrlReg);
} }
@ -37,9 +37,9 @@ ArmGenericTimerDisableTimer (
VOID VOID
) )
{ {
UINTN TimerCtrlReg; UINTN TimerCtrlReg;
TimerCtrlReg = ArmReadCntpCtl (); TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE; TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmWriteCntpCtl (TimerCtrlReg); ArmWriteCntpCtl (TimerCtrlReg);
} }
@ -71,11 +71,10 @@ ArmGenericTimerGetTimerVal (
return ArmReadCntpTval (); return ArmReadCntpTval ();
} }
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetTimerVal ( ArmGenericTimerSetTimerVal (
IN UINTN Value IN UINTN Value
) )
{ {
ArmWriteCntpTval (Value); ArmWriteCntpTval (Value);
@ -102,7 +101,7 @@ ArmGenericTimerGetTimerCtrlReg (
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetTimerCtrlReg ( ArmGenericTimerSetTimerCtrlReg (
UINTN Value UINTN Value
) )
{ {
ArmWriteCntpCtl (Value); ArmWriteCntpCtl (Value);
@ -120,7 +119,7 @@ ArmGenericTimerGetCompareVal (
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetCompareVal ( ArmGenericTimerSetCompareVal (
IN UINT64 Value IN UINT64 Value
) )
{ {
ArmWriteCntpCval (Value); ArmWriteCntpCval (Value);

15
ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c
View File

@ -16,9 +16,9 @@ ArmGenericTimerEnableTimer (
VOID VOID
) )
{ {
UINTN TimerCtrlReg; UINTN TimerCtrlReg;
TimerCtrlReg = ArmReadCntvCtl (); TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE; TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmWriteCntvCtl (TimerCtrlReg); ArmWriteCntvCtl (TimerCtrlReg);
} }
@ -37,9 +37,9 @@ ArmGenericTimerDisableTimer (
VOID VOID
) )
{ {
UINTN TimerCtrlReg; UINTN TimerCtrlReg;
TimerCtrlReg = ArmReadCntvCtl (); TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE; TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmWriteCntvCtl (TimerCtrlReg); ArmWriteCntvCtl (TimerCtrlReg);
} }
@ -71,11 +71,10 @@ ArmGenericTimerGetTimerVal (
return ArmReadCntvTval (); return ArmReadCntvTval ();
} }
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetTimerVal ( ArmGenericTimerSetTimerVal (
IN UINTN Value IN UINTN Value
) )
{ {
ArmWriteCntvTval (Value); ArmWriteCntvTval (Value);
@ -102,7 +101,7 @@ ArmGenericTimerGetTimerCtrlReg (
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetTimerCtrlReg ( ArmGenericTimerSetTimerCtrlReg (
UINTN Value UINTN Value
) )
{ {
ArmWriteCntvCtl (Value); ArmWriteCntvCtl (Value);
@ -120,7 +119,7 @@ ArmGenericTimerGetCompareVal (
VOID VOID
EFIAPI EFIAPI
ArmGenericTimerSetCompareVal ( ArmGenericTimerSetCompareVal (
IN UINT64 Value IN UINT64 Value
) )
{ {
ArmWriteCntvCval (Value); ArmWriteCntvCval (Value);

5
ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c
View File

@ -9,7 +9,7 @@
#include <Library/ArmLib.h> #include <Library/ArmLib.h>
#include <Library/ArmGicLib.h> #include <Library/ArmGicLib.h>
STATIC ARM_GIC_ARCH_REVISION mGicArchRevision; STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
@ -17,7 +17,7 @@ ArmGicArchLibInitialize (
VOID VOID
) )
{ {
UINT32 IccSre; UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but // Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily // this does not seem to be very reliable as the implementation could easily
@ -38,6 +38,7 @@ ArmGicArchLibInitialize (
ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE); ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable (); IccSre = ArmGicV3GetControlSystemRegisterEnable ();
} }
if (IccSre & ICC_SRE_EL2_SRE) { if (IccSre & ICC_SRE_EL2_SRE) {
mGicArchRevision = ARM_GIC_ARCH_REVISION_3; mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
goto Done; goto Done;

3
ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c
View File

@ -15,7 +15,7 @@ ArmGicGetSupportedArchRevision (
VOID VOID
) )
{ {
UINT32 IccSre; UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but // Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily // this does not seem to be very reliable as the implementation could easily
@ -36,6 +36,7 @@ ArmGicGetSupportedArchRevision (
ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE); ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable (); IccSre = ArmGicV3GetControlSystemRegisterEnable ();
} }
if (IccSre & ICC_SRE_EL2_SRE) { if (IccSre & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3; return ARM_GIC_ARCH_REVISION_3;
} }

6
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
View File

@ -23,10 +23,10 @@ AArch64DataCacheOperation (
IN AARCH64_CACHE_OPERATION DataCacheOperation IN AARCH64_CACHE_OPERATION DataCacheOperation
) )
{ {
UINTN SavedInterruptState; UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState (); SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts(); ArmDisableInterrupts ();
AArch64AllDataCachesOperation (DataCacheOperation); AArch64AllDataCachesOperation (DataCacheOperation);
@ -99,7 +99,7 @@ ArmHasCcidx (
VOID VOID
) )
{ {
UINTN Mmfr2; UINTN Mmfr2;
Mmfr2 = ArmReadIdAA64Mmfr2 (); Mmfr2 = ArmReadIdAA64Mmfr2 ();
return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE; return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;

7
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
View File

@ -11,7 +11,9 @@
#ifndef AARCH64_LIB_H_ #ifndef AARCH64_LIB_H_
#define AARCH64_LIB_H_ #define AARCH64_LIB_H_
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN); typedef VOID (*AARCH64_CACHE_OPERATION)(
UINTN
);
VOID VOID
AArch64AllDataCachesOperation ( AArch64AllDataCachesOperation (
@ -33,7 +35,7 @@ ArmCleanDataCacheEntryBySetWay (
VOID VOID
EFIAPI EFIAPI
ArmCleanInvalidateDataCacheEntryBySetWay ( ArmCleanInvalidateDataCacheEntryBySetWay (
IN UINTN SetWayFormat IN UINTN SetWayFormat
); );
UINTN UINTN
@ -53,4 +55,3 @@ ArmReadIdAA64Mmfr2 (
); );
#endif // AARCH64_LIB_H_ #endif // AARCH64_LIB_H_

4
ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c
View File

@ -23,7 +23,7 @@ ArmV7DataCacheOperation (
IN ARM_V7_CACHE_OPERATION DataCacheOperation IN ARM_V7_CACHE_OPERATION DataCacheOperation
) )
{ {
UINTN SavedInterruptState; UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState (); SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts (); ArmDisableInterrupts ();
@ -114,7 +114,7 @@ ArmHasCcidx (
VOID VOID
) )
{ {
UINTN Mmfr4; UINTN Mmfr4;
Mmfr4 = ArmReadIdMmfr4 (); Mmfr4 = ArmReadIdMmfr4 ();
return (((Mmfr4 >> 24) & 0xF) == 1) ? TRUE : FALSE; return (((Mmfr4 >> 24) & 0xF) == 1) ? TRUE : FALSE;

29
ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h
View File

@ -9,21 +9,23 @@
#ifndef ARM_V7_LIB_H_ #ifndef ARM_V7_LIB_H_
#define ARM_V7_LIB_H_ #define ARM_V7_LIB_H_
#define ID_MMFR0_SHARELVL_SHIFT 12 #define ID_MMFR0_SHARELVL_SHIFT 12
#define ID_MMFR0_SHARELVL_MASK 0xf #define ID_MMFR0_SHARELVL_MASK 0xf
#define ID_MMFR0_SHARELVL_ONE 0 #define ID_MMFR0_SHARELVL_ONE 0
#define ID_MMFR0_SHARELVL_TWO 1 #define ID_MMFR0_SHARELVL_TWO 1
#define ID_MMFR0_INNERSHR_SHIFT 28 #define ID_MMFR0_INNERSHR_SHIFT 28
#define ID_MMFR0_INNERSHR_MASK 0xf #define ID_MMFR0_INNERSHR_MASK 0xf
#define ID_MMFR0_OUTERSHR_SHIFT 8 #define ID_MMFR0_OUTERSHR_SHIFT 8
#define ID_MMFR0_OUTERSHR_MASK 0xf #define ID_MMFR0_OUTERSHR_MASK 0xf
#define ID_MMFR0_SHR_IMP_UNCACHED 0 #define ID_MMFR0_SHR_IMP_UNCACHED 0
#define ID_MMFR0_SHR_IMP_HW_COHERENT 1 #define ID_MMFR0_SHR_IMP_HW_COHERENT 1
#define ID_MMFR0_SHR_IGNORED 0xf #define ID_MMFR0_SHR_IGNORED 0xf
typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32); typedef VOID (*ARM_V7_CACHE_OPERATION)(
UINT32
);
VOID VOID
ArmV7AllDataCachesOperation ( ArmV7AllDataCachesOperation (
@ -45,7 +47,7 @@ ArmCleanDataCacheEntryBySetWay (
VOID VOID
EFIAPI EFIAPI
ArmCleanInvalidateDataCacheEntryBySetWay ( ArmCleanInvalidateDataCacheEntryBySetWay (
IN UINTN SetWayFormat IN UINTN SetWayFormat
); );
/** Reads the ID_MMFR4 register. /** Reads the ID_MMFR4 register.
@ -65,4 +67,3 @@ ArmReadIdPfr1 (
); );
#endif // ARM_V7_LIB_H_ #endif // ARM_V7_LIB_H_

14
ArmPkg/Library/ArmLib/ArmLib.c
View File

@ -16,19 +16,19 @@
VOID VOID
EFIAPI EFIAPI
ArmSetAuxCrBit ( ArmSetAuxCrBit (
IN UINT32 Bits IN UINT32 Bits
) )
{ {
ArmWriteAuxCr(ArmReadAuxCr() | Bits); ArmWriteAuxCr (ArmReadAuxCr () | Bits);
} }
VOID VOID
EFIAPI EFIAPI
ArmUnsetAuxCrBit ( ArmUnsetAuxCrBit (
IN UINT32 Bits IN UINT32 Bits
) )
{ {
ArmWriteAuxCr(ArmReadAuxCr() & ~Bits); ArmWriteAuxCr (ArmReadAuxCr () & ~Bits);
} }
// //
@ -38,7 +38,7 @@ ArmUnsetAuxCrBit (
VOID VOID
EFIAPI EFIAPI
ArmSetCpuActlrBit ( ArmSetCpuActlrBit (
IN UINTN Bits IN UINTN Bits
) )
{ {
ArmWriteCpuActlr (ArmReadCpuActlr () | Bits); ArmWriteCpuActlr (ArmReadCpuActlr () | Bits);
@ -47,7 +47,7 @@ ArmSetCpuActlrBit (
VOID VOID
EFIAPI EFIAPI
ArmUnsetCpuActlrBit ( ArmUnsetCpuActlrBit (
IN UINTN Bits IN UINTN Bits
) )
{ {
ArmWriteCpuActlr (ArmReadCpuActlr () & ~Bits); ArmWriteCpuActlr (ArmReadCpuActlr () & ~Bits);
@ -77,7 +77,7 @@ ArmCacheWritebackGranule (
VOID VOID
) )
{ {
UINTN CWG; UINTN CWG;
CWG = (ArmCacheInfo () >> 24) & 0xf; // CTR_EL0.CWG CWG = (ArmCacheInfo () >> 24) & 0xf; // CTR_EL0.CWG

46
ArmPkg/Library/ArmLib/ArmLibPrivate.h
View File

@ -11,19 +11,19 @@
#ifndef ARM_LIB_PRIVATE_H_ #ifndef ARM_LIB_PRIVATE_H_
#define ARM_LIB_PRIVATE_H_ #define ARM_LIB_PRIVATE_H_
#define CACHE_SIZE_4_KB (3UL) #define CACHE_SIZE_4_KB (3UL)
#define CACHE_SIZE_8_KB (4UL) #define CACHE_SIZE_8_KB (4UL)
#define CACHE_SIZE_16_KB (5UL) #define CACHE_SIZE_16_KB (5UL)
#define CACHE_SIZE_32_KB (6UL) #define CACHE_SIZE_32_KB (6UL)
#define CACHE_SIZE_64_KB (7UL) #define CACHE_SIZE_64_KB (7UL)
#define CACHE_SIZE_128_KB (8UL) #define CACHE_SIZE_128_KB (8UL)
#define CACHE_ASSOCIATIVITY_DIRECT (0UL) #define CACHE_ASSOCIATIVITY_DIRECT (0UL)
#define CACHE_ASSOCIATIVITY_4_WAY (2UL) #define CACHE_ASSOCIATIVITY_4_WAY (2UL)
#define CACHE_ASSOCIATIVITY_8_WAY (3UL) #define CACHE_ASSOCIATIVITY_8_WAY (3UL)
#define CACHE_PRESENT (0UL) #define CACHE_PRESENT (0UL)
#define CACHE_NOT_PRESENT (1UL) #define CACHE_NOT_PRESENT (1UL)
#define CACHE_LINE_LENGTH_32_BYTES (2UL) #define CACHE_LINE_LENGTH_32_BYTES (2UL)
@ -32,25 +32,25 @@
#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01) #define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03) #define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF) #define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF) #define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x))) #define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x))) #define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x))) #define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x))) #define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x))) #define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x))) #define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x))) #define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x))) #define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
#define CACHE_TYPE(x) (((x) >> 25) & 0x0F) #define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
#define CACHE_TYPE_WRITE_BACK (0x0EUL) #define CACHE_TYPE_WRITE_BACK (0x0EUL)
#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01) #define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
#define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_UNIFIED (0UL)
#define CACHE_ARCHITECTURE_SEPARATE (1UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL)
VOID VOID
CPSRMaskInsert ( CPSRMaskInsert (

319
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
View File

@ -26,31 +26,32 @@ ArmMemoryAttributeToPageAttribute (
) )
{ {
switch (Attributes) { switch (Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
return TT_ATTR_INDX_MEMORY_WRITE_BACK; return TT_ATTR_INDX_MEMORY_WRITE_BACK;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
// Uncached and device mappings are treated as outer shareable by default, // Uncached and device mappings are treated as outer shareable by default,
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
return TT_ATTR_INDX_MEMORY_NON_CACHEABLE; return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
default: default:
ASSERT (0); ASSERT (0);
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE: case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
if (ArmReadCurrentEL () == AARCH64_EL2) if (ArmReadCurrentEL () == AARCH64_EL2) {
return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK; return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
else } else {
return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK; return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
}
} }
} }
@ -61,7 +62,7 @@ ArmMemoryAttributeToPageAttribute (
STATIC STATIC
UINTN UINTN
GetRootTableEntryCount ( GetRootTableEntryCount (
IN UINTN T0SZ IN UINTN T0SZ
) )
{ {
return TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL; return TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
@ -70,7 +71,7 @@ GetRootTableEntryCount (
STATIC STATIC
UINTN UINTN
GetRootTableLevel ( GetRootTableLevel (
IN UINTN T0SZ IN UINTN T0SZ
) )
{ {
return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL; return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
@ -79,10 +80,10 @@ GetRootTableLevel (
STATIC STATIC
VOID VOID
ReplaceTableEntry ( ReplaceTableEntry (
IN UINT64 *Entry, IN UINT64 *Entry,
IN UINT64 Value, IN UINT64 Value,
IN UINT64 RegionStart, IN UINT64 RegionStart,
IN BOOLEAN IsLiveBlockMapping IN BOOLEAN IsLiveBlockMapping
) )
{ {
if (!ArmMmuEnabled () || !IsLiveBlockMapping) { if (!ArmMmuEnabled () || !IsLiveBlockMapping) {
@ -100,19 +101,22 @@ FreePageTablesRecursive (
IN UINTN Level IN UINTN Level
) )
{ {
UINTN Index; UINTN Index;
ASSERT (Level <= 3); ASSERT (Level <= 3);
if (Level < 3) { if (Level < 3) {
for (Index = 0; Index < TT_ENTRY_COUNT; Index++) { for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) { if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
FreePageTablesRecursive ((VOID *)(UINTN)(TranslationTable[Index] & FreePageTablesRecursive (
TT_ADDRESS_MASK_BLOCK_ENTRY), (VOID *)(UINTN)(TranslationTable[Index] &
Level + 1); TT_ADDRESS_MASK_BLOCK_ENTRY),
Level + 1
);
} }
} }
} }
FreePages (TranslationTable, 1); FreePages (TranslationTable, 1);
} }
@ -126,6 +130,7 @@ IsBlockEntry (
if (Level == 3) { if (Level == 3) {
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3; return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3;
} }
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY; return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY;
} }
@ -143,39 +148,48 @@ IsTableEntry (
// //
return FALSE; return FALSE;
} }
return (Entry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY; return (Entry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY;
} }
STATIC STATIC
EFI_STATUS EFI_STATUS
UpdateRegionMappingRecursive ( UpdateRegionMappingRecursive (
IN UINT64 RegionStart, IN UINT64 RegionStart,
IN UINT64 RegionEnd, IN UINT64 RegionEnd,
IN UINT64 AttributeSetMask, IN UINT64 AttributeSetMask,
IN UINT64 AttributeClearMask, IN UINT64 AttributeClearMask,
IN UINT64 *PageTable, IN UINT64 *PageTable,
IN UINTN Level IN UINTN Level
) )
{ {
UINTN BlockShift; UINTN BlockShift;
UINT64 BlockMask; UINT64 BlockMask;
UINT64 BlockEnd; UINT64 BlockEnd;
UINT64 *Entry; UINT64 *Entry;
UINT64 EntryValue; UINT64 EntryValue;
VOID *TranslationTable; VOID *TranslationTable;
EFI_STATUS Status; EFI_STATUS Status;
ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0); ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
BlockShift = (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ; BlockShift = (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ;
BlockMask = MAX_UINT64 >> BlockShift; BlockMask = MAX_UINT64 >> BlockShift;
DEBUG ((DEBUG_VERBOSE, "%a(%d): %llx - %llx set %lx clr %lx\n", __FUNCTION__, DEBUG ((
Level, RegionStart, RegionEnd, AttributeSetMask, AttributeClearMask)); DEBUG_VERBOSE,
"%a(%d): %llx - %llx set %lx clr %lx\n",
__FUNCTION__,
Level,
RegionStart,
RegionEnd,
AttributeSetMask,
AttributeClearMask
));
for (; RegionStart < RegionEnd; RegionStart = BlockEnd) { for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1); BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)]; Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];
// //
// If RegionStart or BlockEnd is not aligned to the block size at this // If RegionStart or BlockEnd is not aligned to the block size at this
@ -187,8 +201,9 @@ UpdateRegionMappingRecursive (
// we cannot replace it with a block entry without potentially losing // we cannot replace it with a block entry without potentially losing
// attribute information, so keep the table entry in that case. // attribute information, so keep the table entry in that case.
// //
if (Level == 0 || ((RegionStart | BlockEnd) & BlockMask) != 0 || if ((Level == 0) || (((RegionStart | BlockEnd) & BlockMask) != 0) ||
(IsTableEntry (*Entry, Level) && AttributeClearMask != 0)) { (IsTableEntry (*Entry, Level) && (AttributeClearMask != 0)))
{
ASSERT (Level < 3); ASSERT (Level < 3);
if (!IsTableEntry (*Entry, Level)) { if (!IsTableEntry (*Entry, Level)) {
@ -216,9 +231,14 @@ UpdateRegionMappingRecursive (
// We are splitting an existing block entry, so we have to populate // We are splitting an existing block entry, so we have to populate
// the new table with the attributes of the block entry it replaces. // the new table with the attributes of the block entry it replaces.
// //
Status = UpdateRegionMappingRecursive (RegionStart & ~BlockMask, Status = UpdateRegionMappingRecursive (
(RegionStart | BlockMask) + 1, *Entry & TT_ATTRIBUTES_MASK, RegionStart & ~BlockMask,
0, TranslationTable, Level + 1); (RegionStart | BlockMask) + 1,
*Entry & TT_ATTRIBUTES_MASK,
0,
TranslationTable,
Level + 1
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
// //
// The range we passed to UpdateRegionMappingRecursive () is block // The range we passed to UpdateRegionMappingRecursive () is block
@ -236,9 +256,14 @@ UpdateRegionMappingRecursive (
// //
// Recurse to the next level // Recurse to the next level
// //
Status = UpdateRegionMappingRecursive (RegionStart, BlockEnd, Status = UpdateRegionMappingRecursive (
AttributeSetMask, AttributeClearMask, TranslationTable, RegionStart,
Level + 1); BlockEnd,
AttributeSetMask,
AttributeClearMask,
TranslationTable,
Level + 1
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
if (!IsTableEntry (*Entry, Level)) { if (!IsTableEntry (*Entry, Level)) {
// //
@ -250,16 +275,21 @@ UpdateRegionMappingRecursive (
// //
FreePageTablesRecursive (TranslationTable, Level + 1); FreePageTablesRecursive (TranslationTable, Level + 1);
} }
return Status; return Status;
} }
if (!IsTableEntry (*Entry, Level)) { if (!IsTableEntry (*Entry, Level)) {
EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY; EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;
ReplaceTableEntry (Entry, EntryValue, RegionStart, ReplaceTableEntry (
IsBlockEntry (*Entry, Level)); Entry,
EntryValue,
RegionStart,
IsBlockEntry (*Entry, Level)
);
} }
} else { } else {
EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask; EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
EntryValue |= RegionStart; EntryValue |= RegionStart;
EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3 EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3
: TT_TYPE_BLOCK_ENTRY; : TT_TYPE_BLOCK_ENTRY;
@ -280,6 +310,7 @@ UpdateRegionMappingRecursive (
} }
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -292,7 +323,7 @@ UpdateRegionMapping (
IN UINT64 AttributeClearMask IN UINT64 AttributeClearMask
) )
{ {
UINTN T0SZ; UINTN T0SZ;
if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) { if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
@ -300,9 +331,14 @@ UpdateRegionMapping (
T0SZ = ArmGetTCR () & TCR_T0SZ_MASK; T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
return UpdateRegionMappingRecursive (RegionStart, RegionStart + RegionLength, return UpdateRegionMappingRecursive (
AttributeSetMask, AttributeClearMask, ArmGetTTBR0BaseAddress (), RegionStart,
GetRootTableLevel (T0SZ)); RegionStart + RegionLength,
AttributeSetMask,
AttributeClearMask,
ArmGetTTBR0BaseAddress (),
GetRootTableLevel (T0SZ)
);
} }
STATIC STATIC
@ -323,31 +359,32 @@ FillTranslationTable (
STATIC STATIC
UINT64 UINT64
GcdAttributeToPageAttribute ( GcdAttributeToPageAttribute (
IN UINT64 GcdAttributes IN UINT64 GcdAttributes
) )
{ {
UINT64 PageAttributes; UINT64 PageAttributes;
switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) { switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
case EFI_MEMORY_UC: case EFI_MEMORY_UC:
PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY; PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
break; break;
case EFI_MEMORY_WC: case EFI_MEMORY_WC:
PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
break; break;
case EFI_MEMORY_WT: case EFI_MEMORY_WT:
PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
break; break;
case EFI_MEMORY_WB: case EFI_MEMORY_WB:
PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
break; break;
default: default:
PageAttributes = TT_ATTR_INDX_MASK; PageAttributes = TT_ATTR_INDX_MASK;
break; break;
} }
if ((GcdAttributes & EFI_MEMORY_XP) != 0 || if (((GcdAttributes & EFI_MEMORY_XP) != 0) ||
(GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) { ((GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC))
{
if (ArmReadCurrentEL () == AARCH64_EL2) { if (ArmReadCurrentEL () == AARCH64_EL2) {
PageAttributes |= TT_XN_MASK; PageAttributes |= TT_XN_MASK;
} else { } else {
@ -364,15 +401,15 @@ GcdAttributeToPageAttribute (
EFI_STATUS EFI_STATUS
ArmSetMemoryAttributes ( ArmSetMemoryAttributes (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
) )
{ {
UINT64 PageAttributes; UINT64 PageAttributes;
UINT64 PageAttributeMask; UINT64 PageAttributeMask;
PageAttributes = GcdAttributeToPageAttribute (Attributes); PageAttributes = GcdAttributeToPageAttribute (Attributes);
PageAttributeMask = 0; PageAttributeMask = 0;
if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {
@ -380,22 +417,26 @@ ArmSetMemoryAttributes (
// No memory type was set in Attributes, so we are going to update the // No memory type was set in Attributes, so we are going to update the
// permissions only. // permissions only.
// //
PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK; PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK | PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |
TT_PXN_MASK | TT_XN_MASK); TT_PXN_MASK | TT_XN_MASK);
} }
return UpdateRegionMapping (BaseAddress, Length, PageAttributes, return UpdateRegionMapping (
PageAttributeMask); BaseAddress,
Length,
PageAttributes,
PageAttributeMask
);
} }
STATIC STATIC
EFI_STATUS EFI_STATUS
SetMemoryRegionAttribute ( SetMemoryRegionAttribute (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes, IN UINT64 Attributes,
IN UINT64 BlockEntryMask IN UINT64 BlockEntryMask
) )
{ {
return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryMask); return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryMask);
@ -403,11 +444,11 @@ SetMemoryRegionAttribute (
EFI_STATUS EFI_STATUS
ArmSetMemoryRegionNoExec ( ArmSetMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
) )
{ {
UINT64 Val; UINT64 Val;
if (ArmReadCurrentEL () == AARCH64_EL1) { if (ArmReadCurrentEL () == AARCH64_EL1) {
Val = TT_PXN_MASK | TT_UXN_MASK; Val = TT_PXN_MASK | TT_UXN_MASK;
@ -419,16 +460,17 @@ ArmSetMemoryRegionNoExec (
BaseAddress, BaseAddress,
Length, Length,
Val, Val,
~TT_ADDRESS_MASK_BLOCK_ENTRY); ~TT_ADDRESS_MASK_BLOCK_ENTRY
);
} }
EFI_STATUS EFI_STATUS
ArmClearMemoryRegionNoExec ( ArmClearMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
) )
{ {
UINT64 Mask; UINT64 Mask;
// XN maps to UXN in the EL1&0 translation regime // XN maps to UXN in the EL1&0 translation regime
Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK); Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
@ -437,50 +479,53 @@ ArmClearMemoryRegionNoExec (
BaseAddress, BaseAddress,
Length, Length,
0, 0,
Mask); Mask
);
} }
EFI_STATUS EFI_STATUS
ArmSetMemoryRegionReadOnly ( ArmSetMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
) )
{ {
return SetMemoryRegionAttribute ( return SetMemoryRegionAttribute (
BaseAddress, BaseAddress,
Length, Length,
TT_AP_RO_RO, TT_AP_RO_RO,
~TT_ADDRESS_MASK_BLOCK_ENTRY); ~TT_ADDRESS_MASK_BLOCK_ENTRY
);
} }
EFI_STATUS EFI_STATUS
ArmClearMemoryRegionReadOnly ( ArmClearMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
) )
{ {
return SetMemoryRegionAttribute ( return SetMemoryRegionAttribute (
BaseAddress, BaseAddress,
Length, Length,
TT_AP_RW_RW, TT_AP_RW_RW,
~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK)); ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK)
);
} }
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
ArmConfigureMmu ( ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL, OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL OUT UINTN *TranslationTableSize OPTIONAL
) )
{ {
VOID* TranslationTable; VOID *TranslationTable;
UINTN MaxAddressBits; UINTN MaxAddressBits;
UINT64 MaxAddress; UINT64 MaxAddress;
UINTN T0SZ; UINTN T0SZ;
UINTN RootTableEntryCount; UINTN RootTableEntryCount;
UINT64 TCR; UINT64 TCR;
EFI_STATUS Status; EFI_STATUS Status;
if (MemoryTable == NULL) { if (MemoryTable == NULL) {
ASSERT (MemoryTable != NULL); ASSERT (MemoryTable != NULL);
@ -495,9 +540,9 @@ ArmConfigureMmu (
// use of 4 KB pages. // use of 4 KB pages.
// //
MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS); MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS);
MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1; MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;
T0SZ = 64 - MaxAddressBits; T0SZ = 64 - MaxAddressBits;
RootTableEntryCount = GetRootTableEntryCount (T0SZ); RootTableEntryCount = GetRootTableEntryCount (T0SZ);
// //
@ -506,7 +551,7 @@ ArmConfigureMmu (
// Ideally we will be running at EL2, but should support EL1 as well. // Ideally we will be running at EL2, but should support EL1 as well.
// UEFI should not run at EL3. // UEFI should not run at EL3.
if (ArmReadCurrentEL () == AARCH64_EL2) { if (ArmReadCurrentEL () == AARCH64_EL2) {
//Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2 // Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB; TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
// Set the Physical Address Size using MaxAddress // Set the Physical Address Size using MaxAddress
@ -523,9 +568,11 @@ ArmConfigureMmu (
} else if (MaxAddress < SIZE_256TB) { } else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_PS_256TB; TCR |= TCR_PS_256TB;
} else { } else {
DEBUG ((DEBUG_ERROR, DEBUG ((
DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
MaxAddress)); MaxAddress
));
ASSERT (0); // Bigger than 48-bit memory space are not supported ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -547,9 +594,11 @@ ArmConfigureMmu (
} else if (MaxAddress < SIZE_256TB) { } else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_IPS_256TB; TCR |= TCR_IPS_256TB;
} else { } else {
DEBUG ((DEBUG_ERROR, DEBUG ((
DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
MaxAddress)); MaxAddress
));
ASSERT (0); // Bigger than 48-bit memory space are not supported ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -579,6 +628,7 @@ ArmConfigureMmu (
if (TranslationTable == NULL) { if (TranslationTable == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
// //
// We set TTBR0 just after allocating the table to retrieve its location from // We set TTBR0 just after allocating the table to retrieve its location from
// the subsequent functions without needing to pass this value across the // the subsequent functions without needing to pass this value across the
@ -599,8 +649,10 @@ ArmConfigureMmu (
// Make sure we are not inadvertently hitting in the caches // Make sure we are not inadvertently hitting in the caches
// when populating the page tables. // when populating the page tables.
// //
InvalidateDataCacheRange (TranslationTable, InvalidateDataCacheRange (
RootTableEntryCount * sizeof (UINT64)); TranslationTable,
RootTableEntryCount * sizeof (UINT64)
);
ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64)); ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));
while (MemoryTable->Length != 0) { while (MemoryTable->Length != 0) {
@ -608,6 +660,7 @@ ArmConfigureMmu (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
goto FreeTranslationTable; goto FreeTranslationTable;
} }
MemoryTable++; MemoryTable++;
} }
@ -618,10 +671,10 @@ ArmConfigureMmu (
// EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK // EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
// //
ArmSetMAIR ( ArmSetMAIR (
MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK) MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
); );
ArmDisableAlignmentCheck (); ArmDisableAlignmentCheck ();
@ -643,14 +696,16 @@ ArmMmuBaseLibConstructor (
VOID VOID
) )
{ {
extern UINT32 ArmReplaceLiveTranslationEntrySize; extern UINT32 ArmReplaceLiveTranslationEntrySize;
// //
// The ArmReplaceLiveTranslationEntry () helper function may be invoked // The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC // with the MMU off so we have to ensure that it gets cleaned to the PoC
// //
WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry, WriteBackDataCacheRange (
ArmReplaceLiveTranslationEntrySize); (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
ArmReplaceLiveTranslationEntrySize
);
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

21
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c
View File

@ -16,14 +16,14 @@
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
ArmMmuPeiLibConstructor ( ArmMmuPeiLibConstructor (
IN EFI_PEI_FILE_HANDLE FileHandle, IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
extern UINT32 ArmReplaceLiveTranslationEntrySize; extern UINT32 ArmReplaceLiveTranslationEntrySize;
EFI_FV_FILE_INFO FileInfo; EFI_FV_FILE_INFO FileInfo;
EFI_STATUS Status; EFI_STATUS Status;
ASSERT (FileHandle != NULL); ASSERT (FileHandle != NULL);
@ -37,9 +37,10 @@ ArmMmuPeiLibConstructor (
// is executing from DRAM, we only need to perform the cache maintenance // is executing from DRAM, we only need to perform the cache maintenance
// when not executing in place. // when not executing in place.
// //
if ((UINTN)FileInfo.Buffer <= (UINTN)ArmReplaceLiveTranslationEntry && if (((UINTN)FileInfo.Buffer <= (UINTN)ArmReplaceLiveTranslationEntry) &&
((UINTN)FileInfo.Buffer + FileInfo.BufferSize >= ((UINTN)FileInfo.Buffer + FileInfo.BufferSize >=
(UINTN)ArmReplaceLiveTranslationEntry + ArmReplaceLiveTranslationEntrySize)) { (UINTN)ArmReplaceLiveTranslationEntry + ArmReplaceLiveTranslationEntrySize))
{
DEBUG ((DEBUG_INFO, "ArmMmuLib: skipping cache maintenance on XIP PEIM\n")); DEBUG ((DEBUG_INFO, "ArmMmuLib: skipping cache maintenance on XIP PEIM\n"));
} else { } else {
DEBUG ((DEBUG_INFO, "ArmMmuLib: performing cache maintenance on shadowed PEIM\n")); DEBUG ((DEBUG_INFO, "ArmMmuLib: performing cache maintenance on shadowed PEIM\n"));
@ -47,8 +48,10 @@ ArmMmuPeiLibConstructor (
// The ArmReplaceLiveTranslationEntry () helper function may be invoked // The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC // with the MMU off so we have to ensure that it gets cleaned to the PoC
// //
WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry, WriteBackDataCacheRange (
ArmReplaceLiveTranslationEntrySize); (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
ArmReplaceLiveTranslationEntrySize
);
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;

4
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c
View File

@ -19,9 +19,9 @@ ConvertSectionAttributesToPageAttributes (
IN BOOLEAN IsLargePage IN BOOLEAN IsLargePage
) )
{ {
UINT32 PageAttributes; UINT32 PageAttributes;
PageAttributes = 0; PageAttributes = 0;
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage); PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes); PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage); PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);

210
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
View File

@ -17,19 +17,19 @@
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#define ID_MMFR0_SHARELVL_SHIFT 12 #define ID_MMFR0_SHARELVL_SHIFT 12
#define ID_MMFR0_SHARELVL_MASK 0xf #define ID_MMFR0_SHARELVL_MASK 0xf
#define ID_MMFR0_SHARELVL_ONE 0 #define ID_MMFR0_SHARELVL_ONE 0
#define ID_MMFR0_SHARELVL_TWO 1 #define ID_MMFR0_SHARELVL_TWO 1
#define ID_MMFR0_INNERSHR_SHIFT 28 #define ID_MMFR0_INNERSHR_SHIFT 28
#define ID_MMFR0_INNERSHR_MASK 0xf #define ID_MMFR0_INNERSHR_MASK 0xf
#define ID_MMFR0_OUTERSHR_SHIFT 8 #define ID_MMFR0_OUTERSHR_SHIFT 8
#define ID_MMFR0_OUTERSHR_MASK 0xf #define ID_MMFR0_OUTERSHR_MASK 0xf
#define ID_MMFR0_SHR_IMP_UNCACHED 0 #define ID_MMFR0_SHR_IMP_UNCACHED 0
#define ID_MMFR0_SHR_IMP_HW_COHERENT 1 #define ID_MMFR0_SHR_IMP_HW_COHERENT 1
#define ID_MMFR0_SHR_IGNORED 0xf #define ID_MMFR0_SHR_IGNORED 0xf
UINTN UINTN
EFIAPI EFIAPI
@ -49,8 +49,8 @@ PreferNonshareableMemory (
VOID VOID
) )
{ {
UINTN Mmfr; UINTN Mmfr;
UINTN Val; UINTN Val;
if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) { if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {
return TRUE; return TRUE;
@ -63,32 +63,33 @@ PreferNonshareableMemory (
// //
Mmfr = ArmReadIdMmfr0 (); Mmfr = ArmReadIdMmfr0 ();
switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) { switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {
case ID_MMFR0_SHARELVL_ONE: case ID_MMFR0_SHARELVL_ONE:
// one level of shareability // one level of shareability
Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK; Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;
break; break;
case ID_MMFR0_SHARELVL_TWO: case ID_MMFR0_SHARELVL_TWO:
// two levels of shareability // two levels of shareability
Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK; Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;
break; break;
default: default:
// unexpected value -> shareable is the safe option // unexpected value -> shareable is the safe option
ASSERT (FALSE); ASSERT (FALSE);
return FALSE; return FALSE;
} }
return Val != ID_MMFR0_SHR_IMP_HW_COHERENT; return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;
} }
STATIC STATIC
VOID VOID
PopulateLevel2PageTable ( PopulateLevel2PageTable (
IN UINT32 *SectionEntry, IN UINT32 *SectionEntry,
IN UINT32 PhysicalBase, IN UINT32 PhysicalBase,
IN UINT32 RemainLength, IN UINT32 RemainLength,
IN ARM_MEMORY_REGION_ATTRIBUTES Attributes IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
) )
{ {
UINT32* PageEntry; UINT32 *PageEntry;
UINT32 Pages; UINT32 Pages;
UINT32 Index; UINT32 Index;
UINT32 PageAttributes; UINT32 PageAttributes;
@ -104,7 +105,7 @@ PopulateLevel2PageTable (
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK; PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED; PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
@ -132,7 +133,7 @@ PopulateLevel2PageTable (
// Level 2 Translation Table to it // Level 2 Translation Table to it
if (*SectionEntry != 0) { if (*SectionEntry != 0) {
// The entry must be a page table. Otherwise it exists an overlapping in the memory map // The entry must be a page table. Otherwise it exists an overlapping in the memory map
if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) { if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (*SectionEntry)) {
TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK; TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;
} else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) { } else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
// Case where a virtual memory map descriptor overlapped a section entry // Case where a virtual memory map descriptor overlapped a section entry
@ -140,60 +141,66 @@ PopulateLevel2PageTable (
// Allocate a Level2 Page Table for this Section // Allocate a Level2 Page Table for this Section
TranslationTable = (UINTN)AllocateAlignedPages ( TranslationTable = (UINTN)AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE), EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),
TRANSLATION_TABLE_PAGE_ALIGNMENT); TRANSLATION_TABLE_PAGE_ALIGNMENT
);
// Translate the Section Descriptor into Page Descriptor // Translate the Section Descriptor into Page Descriptor
SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE); SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);
BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry); BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*SectionEntry);
// //
// Make sure we are not inadvertently hitting in the caches // Make sure we are not inadvertently hitting in the caches
// when populating the page tables // when populating the page tables
// //
InvalidateDataCacheRange ((VOID *)TranslationTable, InvalidateDataCacheRange (
TRANSLATION_TABLE_PAGE_SIZE); (VOID *)TranslationTable,
TRANSLATION_TABLE_PAGE_SIZE
);
// Populate the new Level2 Page Table for the section // Populate the new Level2 Page Table for the section
PageEntry = (UINT32*)TranslationTable; PageEntry = (UINT32 *)TranslationTable;
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor; PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseSectionAddress + (Index << 12)) | SectionDescriptor;
} }
// Overwrite the section entry to point to the new Level2 Translation Table // Overwrite the section entry to point to the new Level2 Translation Table
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
(IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) | (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |
TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
} else { } else {
// We do not support the other section type (16MB Section) // We do not support the other section type (16MB Section)
ASSERT(0); ASSERT (0);
return; return;
} }
} else { } else {
TranslationTable = (UINTN)AllocateAlignedPages ( TranslationTable = (UINTN)AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE), EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),
TRANSLATION_TABLE_PAGE_ALIGNMENT); TRANSLATION_TABLE_PAGE_ALIGNMENT
);
// //
// Make sure we are not inadvertently hitting in the caches // Make sure we are not inadvertently hitting in the caches
// when populating the page tables // when populating the page tables
// //
InvalidateDataCacheRange ((VOID *)TranslationTable, InvalidateDataCacheRange (
TRANSLATION_TABLE_PAGE_SIZE); (VOID *)TranslationTable,
TRANSLATION_TABLE_PAGE_SIZE
);
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE); ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
(IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) | (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |
TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
} }
FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
PageEntry = (UINT32 *)TranslationTable + FirstPageOffset; PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;
Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE; Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT); ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);
for (Index = 0; Index < Pages; Index++) { for (Index = 0; Index < Pages; Index++) {
*PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes; *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (PhysicalBase) | PageAttributes;
PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE; PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
} }
@ -202,8 +209,10 @@ PopulateLevel2PageTable (
// [speculatively] since the previous invalidate are evicted again. // [speculatively] since the previous invalidate are evicted again.
// //
ArmDataMemoryBarrier (); ArmDataMemoryBarrier ();
InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset, InvalidateDataCacheRange (
RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)); (UINT32 *)TranslationTable + FirstPageOffset,
RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)
);
} }
STATIC STATIC
@ -219,50 +228,50 @@ FillTranslationTable (
UINT64 RemainLength; UINT64 RemainLength;
UINT32 PageMapLength; UINT32 PageMapLength;
ASSERT(MemoryRegion->Length > 0); ASSERT (MemoryRegion->Length > 0);
if (MemoryRegion->PhysicalBase >= SIZE_4GB) { if (MemoryRegion->PhysicalBase >= SIZE_4GB) {
return; return;
} }
PhysicalBase = (UINT32)MemoryRegion->PhysicalBase; PhysicalBase = (UINT32)MemoryRegion->PhysicalBase;
RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase); RemainLength = MIN (MemoryRegion->Length, SIZE_4GB - PhysicalBase);
switch (MemoryRegion->Attributes) { switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0); Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0); Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED; Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (0);
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE: case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0); Attributes = TT_DESCRIPTOR_SECTION_DEVICE (0);
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED; Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1); Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (1);
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1); Attributes = TT_DESCRIPTOR_SECTION_DEVICE (1);
break; break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1); Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (1);
break; break;
default: default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);
break; break;
} }
@ -271,14 +280,15 @@ FillTranslationTable (
} }
// Get the first section entry for this mapping // Get the first section entry for this mapping
SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase); SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS (TranslationTable, MemoryRegion->VirtualBase);
while (RemainLength != 0) { while (RemainLength != 0) {
if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 && if ((PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) { (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE))
{
// Case: Physical address aligned on the Section Size (1MB) && the length // Case: Physical address aligned on the Section Size (1MB) && the length
// is greater than the Section Size // is greater than the Section Size
*SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes; *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (PhysicalBase) | Attributes;
// //
// Issue a DMB to ensure that the page table entry update made it to // Issue a DMB to ensure that the page table entry update made it to
@ -291,14 +301,21 @@ FillTranslationTable (
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE; PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
RemainLength -= TT_DESCRIPTOR_SECTION_SIZE; RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
} else { } else {
PageMapLength = MIN ((UINT32)RemainLength, TT_DESCRIPTOR_SECTION_SIZE - PageMapLength = MIN (
(PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE)); (UINT32)RemainLength,
TT_DESCRIPTOR_SECTION_SIZE -
(PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE)
);
// Case: Physical address aligned on the Section Size (1MB) && the length // Case: Physical address aligned on the Section Size (1MB) && the length
// does not fill a section // does not fill a section
// Case: Physical address NOT aligned on the Section Size (1MB) // Case: Physical address NOT aligned on the Section Size (1MB)
PopulateLevel2PageTable (SectionEntry, PhysicalBase, PageMapLength, PopulateLevel2PageTable (
MemoryRegion->Attributes); SectionEntry,
PhysicalBase,
PageMapLength,
MemoryRegion->Attributes
);
// //
// Issue a DMB to ensure that the page table entry update made it to // Issue a DMB to ensure that the page table entry update made it to
@ -323,16 +340,17 @@ RETURN_STATUS
EFIAPI EFIAPI
ArmConfigureMmu ( ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL, OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL OUT UINTN *TranslationTableSize OPTIONAL
) )
{ {
VOID *TranslationTable; VOID *TranslationTable;
UINT32 TTBRAttributes; UINT32 TTBRAttributes;
TranslationTable = AllocateAlignedPages ( TranslationTable = AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE), EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE),
TRANSLATION_TABLE_SECTION_ALIGNMENT); TRANSLATION_TABLE_SECTION_ALIGNMENT
);
if (TranslationTable == NULL) { if (TranslationTable == NULL) {
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
@ -389,25 +407,27 @@ ArmConfigureMmu (
// //
ArmSetTTBCR (0); ArmSetTTBCR (0);
ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) | ArmSetDomainAccessControl (
DOMAIN_ACCESS_CONTROL_NONE(14) | DOMAIN_ACCESS_CONTROL_NONE (15) |
DOMAIN_ACCESS_CONTROL_NONE(13) | DOMAIN_ACCESS_CONTROL_NONE (14) |
DOMAIN_ACCESS_CONTROL_NONE(12) | DOMAIN_ACCESS_CONTROL_NONE (13) |
DOMAIN_ACCESS_CONTROL_NONE(11) | DOMAIN_ACCESS_CONTROL_NONE (12) |
DOMAIN_ACCESS_CONTROL_NONE(10) | DOMAIN_ACCESS_CONTROL_NONE (11) |
DOMAIN_ACCESS_CONTROL_NONE( 9) | DOMAIN_ACCESS_CONTROL_NONE (10) |
DOMAIN_ACCESS_CONTROL_NONE( 8) | DOMAIN_ACCESS_CONTROL_NONE (9) |
DOMAIN_ACCESS_CONTROL_NONE( 7) | DOMAIN_ACCESS_CONTROL_NONE (8) |
DOMAIN_ACCESS_CONTROL_NONE( 6) | DOMAIN_ACCESS_CONTROL_NONE (7) |
DOMAIN_ACCESS_CONTROL_NONE( 5) | DOMAIN_ACCESS_CONTROL_NONE (6) |
DOMAIN_ACCESS_CONTROL_NONE( 4) | DOMAIN_ACCESS_CONTROL_NONE (5) |
DOMAIN_ACCESS_CONTROL_NONE( 3) | DOMAIN_ACCESS_CONTROL_NONE (4) |
DOMAIN_ACCESS_CONTROL_NONE( 2) | DOMAIN_ACCESS_CONTROL_NONE (3) |
DOMAIN_ACCESS_CONTROL_NONE( 1) | DOMAIN_ACCESS_CONTROL_NONE (2) |
DOMAIN_ACCESS_CONTROL_CLIENT(0)); DOMAIN_ACCESS_CONTROL_NONE (1) |
DOMAIN_ACCESS_CONTROL_CLIENT (0)
);
ArmEnableInstructionCache(); ArmEnableInstructionCache ();
ArmEnableDataCache(); ArmEnableDataCache ();
ArmEnableMmu(); ArmEnableMmu ();
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

168
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
View File

@ -18,9 +18,9 @@
#include <Chipset/ArmV7.h> #include <Chipset/ArmV7.h>
#define __EFI_MEMORY_RWX 0 // no restrictions #define __EFI_MEMORY_RWX 0 // no restrictions
#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \ #define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \
EFI_MEMORY_WC | \ EFI_MEMORY_WC | \
EFI_MEMORY_WT | \ EFI_MEMORY_WT | \
EFI_MEMORY_WB | \ EFI_MEMORY_WB | \
@ -33,14 +33,14 @@ ConvertSectionToPages (
IN EFI_PHYSICAL_ADDRESS BaseAddress IN EFI_PHYSICAL_ADDRESS BaseAddress
) )
{ {
UINT32 FirstLevelIdx; UINT32 FirstLevelIdx;
UINT32 SectionDescriptor; UINT32 SectionDescriptor;
UINT32 PageTableDescriptor; UINT32 PageTableDescriptor;
UINT32 PageDescriptor; UINT32 PageDescriptor;
UINT32 Index; UINT32 Index;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
volatile ARM_PAGE_TABLE_ENTRY *PageTable; volatile ARM_PAGE_TABLE_ENTRY *PageTable;
DEBUG ((DEBUG_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress)); DEBUG ((DEBUG_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
@ -48,12 +48,12 @@ ConvertSectionToPages (
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress (); FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
// Calculate index into first level translation table for start of modification // Calculate index into first level translation table for start of modification
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// Get section attributes and convert to page attributes // Get section attributes and convert to page attributes
SectionDescriptor = FirstLevelTable[FirstLevelIdx]; SectionDescriptor = FirstLevelTable[FirstLevelIdx];
PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE); PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);
// Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB) // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1); PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);
@ -63,7 +63,7 @@ ConvertSectionToPages (
// Write the page table entries out // Write the page table entries out
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor; PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseAddress + (Index << 12)) | PageDescriptor;
} }
// Formulate page table entry, Domain=0, NS=0 // Formulate page table entry, Domain=0, NS=0
@ -78,27 +78,27 @@ ConvertSectionToPages (
STATIC STATIC
EFI_STATUS EFI_STATUS
UpdatePageEntries ( UpdatePageEntries (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes, IN UINT64 Attributes,
OUT BOOLEAN *FlushTlbs OPTIONAL OUT BOOLEAN *FlushTlbs OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 EntryValue; UINT32 EntryValue;
UINT32 EntryMask; UINT32 EntryMask;
UINT32 FirstLevelIdx; UINT32 FirstLevelIdx;
UINT32 Offset; UINT32 Offset;
UINT32 NumPageEntries; UINT32 NumPageEntries;
UINT32 Descriptor; UINT32 Descriptor;
UINT32 p; UINT32 p;
UINT32 PageTableIndex; UINT32 PageTableIndex;
UINT32 PageTableEntry; UINT32 PageTableEntry;
UINT32 CurrentPageTableEntry; UINT32 CurrentPageTableEntry;
VOID *Mva; VOID *Mva;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
volatile ARM_PAGE_TABLE_ENTRY *PageTable; volatile ARM_PAGE_TABLE_ENTRY *PageTable;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@ -156,19 +156,19 @@ UpdatePageEntries (
// Iterate for the number of 4KB pages to change // Iterate for the number of 4KB pages to change
Offset = 0; Offset = 0;
for(p = 0; p < NumPageEntries; p++) { for (p = 0; p < NumPageEntries; p++) {
// Calculate index into first level translation table for page table value // Calculate index into first level translation table for page table value
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// Read the descriptor from the first level page table // Read the descriptor from the first level page table
Descriptor = FirstLevelTable[FirstLevelIdx]; Descriptor = FirstLevelTable[FirstLevelIdx];
// Does this descriptor need to be converted from section entry to 4K pages? // Does this descriptor need to be converted from section entry to 4K pages?
if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) { if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (Descriptor)) {
Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT); Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
if (EFI_ERROR(Status)) { if (EFI_ERROR (Status)) {
// Exit for loop // Exit for loop
break; break;
} }
@ -181,7 +181,7 @@ UpdatePageEntries (
} }
// Obtain page table base address // Obtain page table base address
PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor); PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS (Descriptor);
// Calculate index into the page table // Calculate index into the page table
PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
@ -204,9 +204,8 @@ UpdatePageEntries (
ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva); ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
} }
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
Offset += TT_DESCRIPTOR_PAGE_SIZE; Offset += TT_DESCRIPTOR_PAGE_SIZE;
} // End first level translation table loop } // End first level translation table loop
return Status; return Status;
@ -215,21 +214,21 @@ UpdatePageEntries (
STATIC STATIC
EFI_STATUS EFI_STATUS
UpdateSectionEntries ( UpdateSectionEntries (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 EntryMask; UINT32 EntryMask;
UINT32 EntryValue; UINT32 EntryValue;
UINT32 FirstLevelIdx; UINT32 FirstLevelIdx;
UINT32 NumSections; UINT32 NumSections;
UINT32 i; UINT32 i;
UINT32 CurrentDescriptor; UINT32 CurrentDescriptor;
UINT32 Descriptor; UINT32 Descriptor;
VOID *Mva; VOID *Mva;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@ -286,24 +285,25 @@ UpdateSectionEntries (
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress (); FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
// calculate index into first level translation table for start of modification // calculate index into first level translation table for start of modification
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// calculate number of 1MB first level entries this applies to // calculate number of 1MB first level entries this applies to
NumSections = (UINT32)(Length / TT_DESCRIPTOR_SECTION_SIZE); NumSections = (UINT32)(Length / TT_DESCRIPTOR_SECTION_SIZE);
// iterate through each descriptor // iterate through each descriptor
for(i=0; i<NumSections; i++) { for (i = 0; i < NumSections; i++) {
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i]; CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
// has this descriptor already been converted to pages? // has this descriptor already been converted to pages?
if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) { if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (CurrentDescriptor)) {
// forward this 1MB range to page table function instead // forward this 1MB range to page table function instead
Status = UpdatePageEntries ( Status = UpdatePageEntries (
(FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, (FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,
TT_DESCRIPTOR_SECTION_SIZE, TT_DESCRIPTOR_SECTION_SIZE,
Attributes, Attributes,
NULL); NULL
);
} else { } else {
// still a section entry // still a section entry
@ -334,14 +334,14 @@ UpdateSectionEntries (
EFI_STATUS EFI_STATUS
ArmSetMemoryAttributes ( ArmSetMemoryAttributes (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT64 ChunkLength; UINT64 ChunkLength;
BOOLEAN FlushTlbs; BOOLEAN FlushTlbs;
if (BaseAddress > (UINT64)MAX_ADDRESS) { if (BaseAddress > (UINT64)MAX_ADDRESS) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@ -355,19 +355,22 @@ ArmSetMemoryAttributes (
FlushTlbs = FALSE; FlushTlbs = FALSE;
while (Length > 0) { while (Length > 0) {
if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) && if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
Length >= TT_DESCRIPTOR_SECTION_SIZE) { (Length >= TT_DESCRIPTOR_SECTION_SIZE))
{
ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE; ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;
DEBUG ((DEBUG_PAGE, DEBUG ((
DEBUG_PAGE,
"SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n", "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",
BaseAddress, ChunkLength, Attributes)); BaseAddress,
ChunkLength,
Attributes
));
Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes); Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);
FlushTlbs = TRUE; FlushTlbs = TRUE;
} else { } else {
// //
// Process page by page until the next section boundary, but only if // Process page by page until the next section boundary, but only if
// we have more than a section's worth of area to deal with after that. // we have more than a section's worth of area to deal with after that.
@ -378,12 +381,20 @@ ArmSetMemoryAttributes (
ChunkLength = Length; ChunkLength = Length;
} }
DEBUG ((DEBUG_PAGE, DEBUG ((
DEBUG_PAGE,
"SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n", "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",
BaseAddress, ChunkLength, Attributes)); BaseAddress,
ChunkLength,
Attributes
));
Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes, Status = UpdatePageEntries (
&FlushTlbs); BaseAddress,
ChunkLength,
Attributes,
&FlushTlbs
);
} }
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -391,19 +402,20 @@ ArmSetMemoryAttributes (
} }
BaseAddress += ChunkLength; BaseAddress += ChunkLength;
Length -= ChunkLength; Length -= ChunkLength;
} }
if (FlushTlbs) { if (FlushTlbs) {
ArmInvalidateTlb (); ArmInvalidateTlb ();
} }
return Status; return Status;
} }
EFI_STATUS EFI_STATUS
ArmSetMemoryRegionNoExec ( ArmSetMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
) )
{ {
return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP); return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);
@ -411,8 +423,8 @@ ArmSetMemoryRegionNoExec (
EFI_STATUS EFI_STATUS
ArmClearMemoryRegionNoExec ( ArmClearMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
) )
{ {
return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
@ -420,8 +432,8 @@ ArmClearMemoryRegionNoExec (
EFI_STATUS EFI_STATUS
ArmSetMemoryRegionReadOnly ( ArmSetMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
) )
{ {
return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO); return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
@ -429,8 +441,8 @@ ArmSetMemoryRegionReadOnly (
EFI_STATUS EFI_STATUS
ArmClearMemoryRegionReadOnly ( ArmClearMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length IN UINT64 Length
) )
{ {
return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);

2
ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c
View File

@ -34,7 +34,7 @@ MtlWaitUntilChannelFree (
@retval UINT32* Pointer to the payload. @retval UINT32* Pointer to the payload.
**/ **/
UINT32* UINT32 *
MtlGetChannelPayload ( MtlGetChannelPayload (
IN MTL_CHANNEL *Channel IN MTL_CHANNEL *Channel
) )

36
ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
View File

@ -36,30 +36,30 @@
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LibResetSystem ( LibResetSystem (
IN EFI_RESET_TYPE ResetType, IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus, IN EFI_STATUS ResetStatus,
IN UINTN DataSize, IN UINTN DataSize,
IN CHAR16 *ResetData OPTIONAL IN CHAR16 *ResetData OPTIONAL
) )
{ {
ARM_SMC_ARGS ArmSmcArgs; ARM_SMC_ARGS ArmSmcArgs;
switch (ResetType) { switch (ResetType) {
case EfiResetPlatformSpecific: case EfiResetPlatformSpecific:
// Map the platform specific reset as reboot // Map the platform specific reset as reboot
case EfiResetWarm: case EfiResetWarm:
// Map a warm reset into a cold reset // Map a warm reset into a cold reset
case EfiResetCold: case EfiResetCold:
// Send a PSCI 0.2 SYSTEM_RESET command // Send a PSCI 0.2 SYSTEM_RESET command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET; ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
break; break;
case EfiResetShutdown: case EfiResetShutdown:
// Send a PSCI 0.2 SYSTEM_OFF command // Send a PSCI 0.2 SYSTEM_OFF command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF; ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
break; break;
default: default:
ASSERT (FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
ArmCallSmc (&ArmSmcArgs); ArmCallSmc (&ArmSmcArgs);

2
ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c
View File

@ -10,7 +10,7 @@
VOID VOID
ArmCallSmc ( ArmCallSmc (
IN OUT ARM_SMC_ARGS *Args IN OUT ARM_SMC_ARGS *Args
) )
{ {
} }

44
ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
View File

@ -31,7 +31,7 @@ ResetCold (
VOID VOID
) )
{ {
ARM_SMC_ARGS ArmSmcArgs; ARM_SMC_ARGS ArmSmcArgs;
// Send a PSCI 0.2 SYSTEM_RESET command // Send a PSCI 0.2 SYSTEM_RESET command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET; ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
@ -66,7 +66,7 @@ ResetShutdown (
VOID VOID
) )
{ {
ARM_SMC_ARGS ArmSmcArgs; ARM_SMC_ARGS ArmSmcArgs;
// Send a PSCI 0.2 SYSTEM_OFF command // Send a PSCI 0.2 SYSTEM_OFF command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF; ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
@ -87,8 +87,8 @@ ResetShutdown (
VOID VOID
EFIAPI EFIAPI
ResetPlatformSpecific ( ResetPlatformSpecific (
IN UINTN DataSize, IN UINTN DataSize,
IN VOID *ResetData IN VOID *ResetData
) )
{ {
// Map the platform specific reset as reboot // Map the platform specific reset as reboot
@ -110,30 +110,30 @@ ResetPlatformSpecific (
VOID VOID
EFIAPI EFIAPI
ResetSystem ( ResetSystem (
IN EFI_RESET_TYPE ResetType, IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus, IN EFI_STATUS ResetStatus,
IN UINTN DataSize, IN UINTN DataSize,
IN VOID *ResetData OPTIONAL IN VOID *ResetData OPTIONAL
) )
{ {
switch (ResetType) { switch (ResetType) {
case EfiResetWarm: case EfiResetWarm:
ResetWarm (); ResetWarm ();
break; break;
case EfiResetCold: case EfiResetCold:
ResetCold (); ResetCold ();
break; break;
case EfiResetShutdown: case EfiResetShutdown:
ResetShutdown (); ResetShutdown ();
return; return;
case EfiResetPlatformSpecific: case EfiResetPlatformSpecific:
ResetPlatformSpecific (DataSize, ResetData); ResetPlatformSpecific (DataSize, ResetData);
return; return;
default: default:
return; return;
} }
} }

322
ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c
View File

@ -18,35 +18,47 @@
* have been expected we use aeabi_float_t and aeabi_double_t respectively * have been expected we use aeabi_float_t and aeabi_double_t respectively
* instead. * instead.
*/ */
typedef uint32_t aeabi_float_t; typedef uint32_t aeabi_float_t;
typedef uint64_t aeabi_double_t; typedef uint64_t aeabi_double_t;
/* /*
* Helpers to convert between float32 and aeabi_float_t, and float64 and * Helpers to convert between float32 and aeabi_float_t, and float64 and
* aeabi_double_t used by the AEABI functions below. * aeabi_double_t used by the AEABI functions below.
*/ */
static aeabi_float_t f32_to_f(float32_t val) static aeabi_float_t
f32_to_f (
float32_t val
)
{ {
return val.v; return val.v;
} }
static float32_t f32_from_f(aeabi_float_t val) static float32_t
f32_from_f (
aeabi_float_t val
)
{ {
float32_t res; float32_t res;
res.v = val; res.v = val;
return res; return res;
} }
static aeabi_double_t f64_to_d(float64_t val) static aeabi_double_t
f64_to_d (
float64_t val
)
{ {
return val.v; return val.v;
} }
static float64_t f64_from_d(aeabi_double_t val) static float64_t
f64_from_d (
aeabi_double_t val
)
{ {
float64_t res; float64_t res;
res.v = val; res.v = val;
@ -64,220 +76,346 @@ static float64_t f64_from_d(aeabi_double_t val)
* Table 2, Standard aeabi_double_t precision floating-point arithmetic helper * Table 2, Standard aeabi_double_t precision floating-point arithmetic helper
* functions * functions
*/ */
aeabi_double_t
aeabi_double_t __aeabi_dadd(aeabi_double_t a, aeabi_double_t b) __aeabi_dadd (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_to_d(f64_add(f64_from_d(a), f64_from_d(b))); return f64_to_d (f64_add (f64_from_d (a), f64_from_d (b)));
} }
aeabi_double_t __aeabi_ddiv(aeabi_double_t a, aeabi_double_t b) aeabi_double_t
__aeabi_ddiv (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_to_d(f64_div(f64_from_d(a), f64_from_d(b))); return f64_to_d (f64_div (f64_from_d (a), f64_from_d (b)));
} }
aeabi_double_t __aeabi_dmul(aeabi_double_t a, aeabi_double_t b) aeabi_double_t
__aeabi_dmul (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_to_d(f64_mul(f64_from_d(a), f64_from_d(b))); return f64_to_d (f64_mul (f64_from_d (a), f64_from_d (b)));
} }
aeabi_double_t
aeabi_double_t __aeabi_drsub(aeabi_double_t a, aeabi_double_t b) __aeabi_drsub (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_to_d(f64_sub(f64_from_d(b), f64_from_d(a))); return f64_to_d (f64_sub (f64_from_d (b), f64_from_d (a)));
} }
aeabi_double_t __aeabi_dsub(aeabi_double_t a, aeabi_double_t b) aeabi_double_t
__aeabi_dsub (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_to_d(f64_sub(f64_from_d(a), f64_from_d(b))); return f64_to_d (f64_sub (f64_from_d (a), f64_from_d (b)));
} }
/* /*
* Table 3, double precision floating-point comparison helper functions * Table 3, double precision floating-point comparison helper functions
*/ */
int
int __aeabi_dcmpeq(aeabi_double_t a, aeabi_double_t b) __aeabi_dcmpeq (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_eq(f64_from_d(a), f64_from_d(b)); return f64_eq (f64_from_d (a), f64_from_d (b));
} }
int __aeabi_dcmplt(aeabi_double_t a, aeabi_double_t b) int
__aeabi_dcmplt (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_lt(f64_from_d(a), f64_from_d(b)); return f64_lt (f64_from_d (a), f64_from_d (b));
} }
int __aeabi_dcmple(aeabi_double_t a, aeabi_double_t b) int
__aeabi_dcmple (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_le(f64_from_d(a), f64_from_d(b)); return f64_le (f64_from_d (a), f64_from_d (b));
} }
int __aeabi_dcmpge(aeabi_double_t a, aeabi_double_t b) int
__aeabi_dcmpge (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_le(f64_from_d(b), f64_from_d(a)); return f64_le (f64_from_d (b), f64_from_d (a));
} }
int __aeabi_dcmpgt(aeabi_double_t a, aeabi_double_t b) int
__aeabi_dcmpgt (
aeabi_double_t a,
aeabi_double_t b
)
{ {
return f64_lt(f64_from_d(b), f64_from_d(a)); return f64_lt (f64_from_d (b), f64_from_d (a));
} }
/* /*
* Table 4, Standard single precision floating-point arithmetic helper * Table 4, Standard single precision floating-point arithmetic helper
* functions * functions
*/ */
aeabi_float_t
aeabi_float_t __aeabi_fadd(aeabi_float_t a, aeabi_float_t b) __aeabi_fadd (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_to_f(f32_add(f32_from_f(a), f32_from_f(b))); return f32_to_f (f32_add (f32_from_f (a), f32_from_f (b)));
} }
aeabi_float_t __aeabi_fdiv(aeabi_float_t a, aeabi_float_t b) aeabi_float_t
__aeabi_fdiv (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_to_f(f32_div(f32_from_f(a), f32_from_f(b))); return f32_to_f (f32_div (f32_from_f (a), f32_from_f (b)));
} }
aeabi_float_t __aeabi_fmul(aeabi_float_t a, aeabi_float_t b) aeabi_float_t
__aeabi_fmul (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_to_f(f32_mul(f32_from_f(a), f32_from_f(b))); return f32_to_f (f32_mul (f32_from_f (a), f32_from_f (b)));
} }
aeabi_float_t __aeabi_frsub(aeabi_float_t a, aeabi_float_t b) aeabi_float_t
__aeabi_frsub (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_to_f(f32_sub(f32_from_f(b), f32_from_f(a))); return f32_to_f (f32_sub (f32_from_f (b), f32_from_f (a)));
} }
aeabi_float_t __aeabi_fsub(aeabi_float_t a, aeabi_float_t b) aeabi_float_t
__aeabi_fsub (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_to_f(f32_sub(f32_from_f(a), f32_from_f(b))); return f32_to_f (f32_sub (f32_from_f (a), f32_from_f (b)));
} }
/* /*
* Table 5, Standard single precision floating-point comparison helper * Table 5, Standard single precision floating-point comparison helper
* functions * functions
*/ */
int
int __aeabi_fcmpeq(aeabi_float_t a, aeabi_float_t b) __aeabi_fcmpeq (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_eq(f32_from_f(a), f32_from_f(b)); return f32_eq (f32_from_f (a), f32_from_f (b));
} }
int __aeabi_fcmplt(aeabi_float_t a, aeabi_float_t b) int
__aeabi_fcmplt (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_lt(f32_from_f(a), f32_from_f(b)); return f32_lt (f32_from_f (a), f32_from_f (b));
} }
int __aeabi_fcmple(aeabi_float_t a, aeabi_float_t b) int
__aeabi_fcmple (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_le(f32_from_f(a), f32_from_f(b)); return f32_le (f32_from_f (a), f32_from_f (b));
} }
int __aeabi_fcmpge(aeabi_float_t a, aeabi_float_t b) int
__aeabi_fcmpge (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_le(f32_from_f(b), f32_from_f(a)); return f32_le (f32_from_f (b), f32_from_f (a));
} }
int __aeabi_fcmpgt(aeabi_float_t a, aeabi_float_t b) int
__aeabi_fcmpgt (
aeabi_float_t a,
aeabi_float_t b
)
{ {
return f32_lt(f32_from_f(b), f32_from_f(a)); return f32_lt (f32_from_f (b), f32_from_f (a));
} }
/* /*
* Table 6, Standard floating-point to integer conversions * Table 6, Standard floating-point to integer conversions
*/ */
int
int __aeabi_d2iz(aeabi_double_t a) __aeabi_d2iz (
aeabi_double_t a
)
{ {
return f64_to_i32_r_minMag(f64_from_d(a), false); return f64_to_i32_r_minMag (f64_from_d (a), false);
} }
unsigned __aeabi_d2uiz(aeabi_double_t a) unsigned
__aeabi_d2uiz (
aeabi_double_t a
)
{ {
return f64_to_ui32_r_minMag(f64_from_d(a), false); return f64_to_ui32_r_minMag (f64_from_d (a), false);
} }
long long __aeabi_d2lz(aeabi_double_t a) long long
__aeabi_d2lz (
aeabi_double_t a
)
{ {
return f64_to_i64_r_minMag(f64_from_d(a), false); return f64_to_i64_r_minMag (f64_from_d (a), false);
} }
unsigned long long __aeabi_d2ulz(aeabi_double_t a) unsigned long long
__aeabi_d2ulz (
aeabi_double_t a
)
{ {
return f64_to_ui64_r_minMag(f64_from_d(a), false); return f64_to_ui64_r_minMag (f64_from_d (a), false);
} }
int __aeabi_f2iz(aeabi_float_t a) int
__aeabi_f2iz (
aeabi_float_t a
)
{ {
return f32_to_i32_r_minMag(f32_from_f(a), false); return f32_to_i32_r_minMag (f32_from_f (a), false);
} }
unsigned __aeabi_f2uiz(aeabi_float_t a) unsigned
__aeabi_f2uiz (
aeabi_float_t a
)
{ {
return f32_to_ui32_r_minMag(f32_from_f(a), false); return f32_to_ui32_r_minMag (f32_from_f (a), false);
} }
long long __aeabi_f2lz(aeabi_float_t a) long long
__aeabi_f2lz (
aeabi_float_t a
)
{ {
return f32_to_i64_r_minMag(f32_from_f(a), false); return f32_to_i64_r_minMag (f32_from_f (a), false);
} }
unsigned long long __aeabi_f2ulz(aeabi_float_t a) unsigned long long
__aeabi_f2ulz (
aeabi_float_t a
)
{ {
return f32_to_ui64_r_minMag(f32_from_f(a), false); return f32_to_ui64_r_minMag (f32_from_f (a), false);
} }
/* /*
* Table 7, Standard conversions between floating types * Table 7, Standard conversions between floating types
*/ */
aeabi_float_t
aeabi_float_t __aeabi_d2f(aeabi_double_t a) __aeabi_d2f (
aeabi_double_t a
)
{ {
return f32_to_f(f64_to_f32(f64_from_d(a))); return f32_to_f (f64_to_f32 (f64_from_d (a)));
} }
aeabi_double_t __aeabi_f2d(aeabi_float_t a) aeabi_double_t
__aeabi_f2d (
aeabi_float_t a
)
{ {
return f64_to_d(f32_to_f64(f32_from_f(a))); return f64_to_d (f32_to_f64 (f32_from_f (a)));
} }
/* /*
* Table 8, Standard integer to floating-point conversions * Table 8, Standard integer to floating-point conversions
*/ */
aeabi_double_t
aeabi_double_t __aeabi_i2d(int a) __aeabi_i2d (
int a
)
{ {
return f64_to_d(i32_to_f64(a)); return f64_to_d (i32_to_f64 (a));
} }
aeabi_double_t __aeabi_ui2d(unsigned a) aeabi_double_t
__aeabi_ui2d (
unsigned a
)
{ {
return f64_to_d(ui32_to_f64(a)); return f64_to_d (ui32_to_f64 (a));
} }
aeabi_double_t __aeabi_l2d(long long a) aeabi_double_t
__aeabi_l2d (
long long a
)
{ {
return f64_to_d(i64_to_f64(a)); return f64_to_d (i64_to_f64 (a));
} }
aeabi_double_t __aeabi_ul2d(unsigned long long a) aeabi_double_t
__aeabi_ul2d (
unsigned long long a
)
{ {
return f64_to_d(ui64_to_f64(a)); return f64_to_d (ui64_to_f64 (a));
} }
aeabi_float_t __aeabi_i2f(int a) aeabi_float_t
__aeabi_i2f (
int a
)
{ {
return f32_to_f(i32_to_f32(a)); return f32_to_f (i32_to_f32 (a));
} }
aeabi_float_t __aeabi_ui2f(unsigned a) aeabi_float_t
__aeabi_ui2f (
unsigned a
)
{ {
return f32_to_f(ui32_to_f32(a)); return f32_to_f (ui32_to_f32 (a));
} }
aeabi_float_t __aeabi_l2f(long long a) aeabi_float_t
__aeabi_l2f (
long long a
)
{ {
return f32_to_f(i64_to_f32(a)); return f32_to_f (i64_to_f32 (a));
} }
aeabi_float_t __aeabi_ul2f(unsigned long long a) aeabi_float_t
__aeabi_ul2f (
unsigned long long a
)
{ {
return f32_to_f(ui64_to_f32(a)); return f32_to_f (ui64_to_f32 (a));
} }

6
ArmPkg/Library/ArmSoftFloatLib/platform.h
View File

@ -8,9 +8,9 @@
#ifndef ARM_SOFT_FLOAT_LIB_H_ #ifndef ARM_SOFT_FLOAT_LIB_H_
#define ARM_SOFT_FLOAT_LIB_H_ #define ARM_SOFT_FLOAT_LIB_H_
#define LITTLEENDIAN 1 #define LITTLEENDIAN 1
#define INLINE static inline #define INLINE static inline
#define SOFTFLOAT_BUILTIN_CLZ 1 #define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_FAST_INT64 #define SOFTFLOAT_FAST_INT64
#include "opts-GCC.h" #include "opts-GCC.h"

33
ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c
View File

@ -1,32 +1,45 @@
//------------------------------------------------------------------------------ // ------------------------------------------------------------------------------
// //
// Copyright (c) 2019, Pete Batard. All rights reserved. // Copyright (c) 2019, Pete Batard. All rights reserved.
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR> // Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
// //
// SPDX-License-Identifier: BSD-2-Clause-Patent // SPDX-License-Identifier: BSD-2-Clause-Patent
// //
//------------------------------------------------------------------------------ // ------------------------------------------------------------------------------
#if defined(_M_ARM64) #if defined (_M_ARM64)
typedef unsigned __int64 size_t; typedef unsigned __int64 size_t;
#else #else
typedef unsigned __int32 size_t; typedef unsigned __int32 size_t;
#endif #endif
int memcmp(void *, void *, size_t); int
memcmp (
void *,
void *,
size_t
);
#pragma intrinsic(memcmp) #pragma intrinsic(memcmp)
#pragma function(memcmp) #pragma function(memcmp)
int memcmp(const void *s1, const void *s2, size_t n) int
memcmp (
const void *s1,
const void *s2,
size_t n
)
{ {
unsigned char const *t1; unsigned char const *t1;
unsigned char const *t2; unsigned char const *t2;
t1 = s1; t1 = s1;
t2 = s2; t2 = s2;
while (n-- != 0) { while (n-- != 0) {
if (*t1 != *t2) if (*t1 != *t2) {
return (int)*t1 - (int)*t2; return (int)*t1 - (int)*t2;
}
t1++; t1++;
t2++; t2++;
} }

Some files were not shown because too many files have changed in this diff Show More