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Added DebugAgentTimerLib. Cleaned up .h files and other code.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10332 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2010-04-03 00:34:19 +00:00
parent 1f44ee1077
commit 43263288dd
35 changed files with 558 additions and 308 deletions
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10
Omap35xxPkg/Include/Omap3530/Omap3530.h
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@@ -28,11 +28,11 @@
//CONTROL_PBIAS_LITE
#define CONTROL_PBIAS_LITE 0x48002520
#define PBIASLITEVMODE0 (0x1UL << 0)
#define PBIASLITEPWRDNZ0 (0x1UL << 1)
#define PBIASSPEEDCTRL0 (0x1UL << 2)
#define PBIASLITEVMODE1 (0x1UL << 8)
#define PBIASLITEWRDNZ1 (0x1UL << 9)
#define PBIASLITEVMODE0 BIT0
#define PBIASLITEPWRDNZ0 BIT1
#define PBIASSPEEDCTRL0 BIT2
#define PBIASLITEVMODE1 BIT8
#define PBIASLITEWRDNZ1 BIT9
#endif // __OMAP3530_H__

24
Omap35xxPkg/Include/Omap3530/Omap3530Gpio.h
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@@ -50,21 +50,21 @@
#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_NONE (1UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3
#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
#define GPIO_SYSCONFIG_ENAWAKEUP_MASK (1UL << 2)
#define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2
#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2)
#define GPIO_SYSCONFIG_SOFTRESET_MASK (1UL << 1)
#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
#define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1
#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
#define GPIO_SYSCONFIG_SOFTRESET_RESET (1UL << 1)
#define GPIO_SYSCONFIG_AUTOIDLE_MASK (1UL << 0)
#define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1
#define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0
#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
#define GPIO_SYSCONFIG_AUTOIDLE_ON (1UL << 0)
#define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0
#define GPIO_SYSSTATUS_RESETDONE_MASK (1UL << 0)
#define GPIO_SYSSTATUS_RESETDONE_MASK BIT0
#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE (1UL << 0)
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0
#define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
@@ -81,12 +81,12 @@
#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_2 (1UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1
#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
#define GPIO_CTRL_DISABLEMODULE_MASK (1UL << 0)
#define GPIO_CTRL_DISABLEMODULE_MASK BIT0
#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
#define GPIO_CTRL_DISABLEMODULE_DISABLE (1UL << 0)
#define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0
#define GPIO_OE_MASK(x) (1UL << (x))
#define GPIO_OE_OUTPUT(x) (0UL << (x))

26
Omap35xxPkg/Include/Omap3530/Omap3530Gpmc.h
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@@ -26,14 +26,14 @@
#define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
#define TIMEOUTENABLE (0x1UL << 0)
#define TIMEOUTENABLE BIT0
#define TIMEOUTDISABLE (0x0UL << 0)
#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
#define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
#define GPMC_CONFIG (GPMC_BASE + 0x50)
#define WRITEPROTECT_HIGH (0x1UL << 4)
#define WRITEPROTECT_HIGH BIT4
#define WRITEPROTECT_LOW (0x0UL << 4)
#define GPMC_STATUS (GPMC_BASE + 0x54)
@@ -42,7 +42,7 @@
#define DEVICETYPE_NOR (0x0UL << 10)
#define DEVICETYPE_NAND (0x2UL << 10)
#define DEVICESIZE_X8 (0x0UL << 12)
#define DEVICESIZE_X16 (0x1UL << 12)
#define DEVICESIZE_X16 BIT12
#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
#define CSONTIME (0x0UL << 0)
@@ -54,26 +54,26 @@
#define ADVWROFFTIME (0x14UL << 16)
#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
#define OEONTIME (0x1UL << 0)
#define OEONTIME BIT0
#define OEOFFTIME (0xFUL << 8)
#define WEONTIME (0x1UL << 16)
#define WEONTIME BIT16
#define WEOFFTIME (0xFUL << 24)
#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
#define RDCYCLETIME (0x14UL << 0)
#define WRCYCLETIME (0x14UL << 8)
#define RDACCESSTIME (0xCUL << 16)
#define PAGEBURSTACCESSTIME (0x1UL << 24)
#define PAGEBURSTACCESSTIME BIT24
#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
#define CYCLE2CYCLESAMECSEN (0x1UL << 7)
#define CYCLE2CYCLESAMECSEN BIT7
#define CYCLE2CYCLEDELAY (0xAUL << 8)
#define WRDATAONADMUXBUS (0xFUL << 16)
#define WRACCESSTIME (0x1FUL << 24)
#define WRACCESSTIME BIT24
#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
#define BASEADDRESS (0x30UL << 0)
#define CSVALID (0x1UL << 6)
#define CSVALID BIT6
#define MASKADDRESS_128MB (0x8UL << 8)
#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
@@ -81,14 +81,14 @@
#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
#define ECCENABLE (0x1UL << 0)
#define ECCENABLE BIT0
#define ECCDISABLE (0x0UL << 0)
#define ECCCS_0 (0x0UL << 1)
#define ECC16B (0x1UL << 7)
#define ECC16B BIT7
#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
#define ECCPOINTER_REG1 (0x1UL << 0)
#define ECCCLEAR (0x1UL << 8)
#define ECCPOINTER_REG1 BIT0
#define ECCCLEAR BIT8
#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
#define ECCSIZE0_512BYTES (0xFFUL << 12)

30
Omap35xxPkg/Include/Omap3530/Omap3530I2c.h
View File

@@ -19,17 +19,17 @@
#define I2C1BASE 0x48070000
#define I2C_IE (I2C1BASE + 0x4)
#define XRDY_IE (0x1UL << 4)
#define RRDY_IE (0x1UL << 3)
#define ARDY_IE (0x1UL << 2)
#define NACK_IE (0x1UL << 1)
#define XRDY_IE BIT4
#define RRDY_IE BIT3
#define ARDY_IE BIT2
#define NACK_IE BIT1
#define I2C_STAT (I2C1BASE + 0x8)
#define BB (0x1UL << 12)
#define XRDY (0x1UL << 4)
#define RRDY (0x1UL << 3)
#define ARDY (0x1UL << 2)
#define NACK (0x1UL << 1)
#define BB BIT12
#define XRDY BIT4
#define RRDY BIT3
#define ARDY BIT2
#define NACK BIT1
#define I2C_WE (I2C1BASE + 0xC)
#define I2C_SYSS (I2C1BASE + 0x10)
@@ -39,12 +39,12 @@
#define I2C_SYSC (I2C1BASE + 0x20)
#define I2C_CON (I2C1BASE + 0x24)
#define STT (0x1UL << 0)
#define STP (0x1UL << 1)
#define XSA (0x1UL << 8)
#define TRX (0x1UL << 9)
#define MST (0x1UL << 10)
#define I2C_EN (0x1UL << 15)
#define STT BIT0
#define STP BIT1
#define XSA BIT8
#define TRX BIT9
#define MST BIT10
#define I2C_EN BIT15
#define I2C_OA0 (I2C1BASE + 0x28)
#define I2C_SA (I2C1BASE + 0x2C)

3
Omap35xxPkg/Include/Omap3530/Omap3530Interrupt.h
View File

@@ -40,7 +40,8 @@
#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
#define INTCPS_SIR_IRQ_MASK (0x7F)
#define INTCPS_CONTROL_NEWIRQAGR (1UL << 0)
#define INTCPS_CONTROL_NEWIRQAGR BIT0
#define INTCPS_CONTROL_NEWFIQAGR BIT1
#endif // __OMAP3530INTERRUPT_H__

156
Omap35xxPkg/Include/Omap3530/Omap3530MMCHS.h
View File

@@ -20,31 +20,31 @@
#define MMC_REFERENCE_CLK (96000000)
#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
#define SOFTRESET (0x1UL << 1)
#define ENAWAKEUP (0x1UL << 2)
#define SOFTRESET BIT1
#define ENAWAKEUP BIT2
#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
#define RESETDONE_MASK (0x1UL << 0)
#define RESETDONE (0x1UL << 0)
#define RESETDONE_MASK BIT0
#define RESETDONE BIT0
#define MMCHS_CSRE (MMCHS1BASE + 0x24)
#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
#define MMCHS_CON (MMCHS1BASE + 0x2C)
#define OD (0x1UL << 0)
#define OD BIT0
#define NOINIT (0x0UL << 1)
#define INIT (0x1UL << 1)
#define HR (0x1UL << 2)
#define STR (0x1UL << 3)
#define MODE (0x1UL << 4)
#define INIT BIT1
#define HR BIT2
#define STR BIT3
#define MODE BIT4
#define DW8_1_4_BIT (0x0UL << 5)
#define DW8_8_BIT (0x1UL << 5)
#define MIT (0x1UL << 6)
#define CDP (0x1UL << 7)
#define WPP (0x1UL << 8)
#define CTPL (0x1UL << 11)
#define DW8_8_BIT BIT5
#define MIT BIT6
#define CDP BIT7
#define WPP BIT8
#define CTPL BIT11
#define CEATA_OFF (0x0UL << 12)
#define CEATA_ON (0x1UL << 12)
#define CEATA_ON BIT12
#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
@@ -54,19 +54,19 @@
#define MMCHS_ARG (MMCHS1BASE + 0x108)
#define MMCHS_CMD (MMCHS1BASE + 0x10C)
#define DE_ENABLE (0x1UL << 0)
#define BCE_ENABLE (0x1UL << 1)
#define ACEN_ENABLE (0x1UL << 2)
#define DDIR_READ (0x1UL << 4)
#define DE_ENABLE BIT0
#define BCE_ENABLE BIT1
#define ACEN_ENABLE BIT2
#define DDIR_READ BIT4
#define DDIR_WRITE (0x0UL << 4)
#define MSBS_SGLEBLK (0x0UL << 5)
#define MSBS_MULTBLK (0x1UL << 5)
#define MSBS_MULTBLK BIT5
#define RSP_TYPE_MASK (0x3UL << 16)
#define RSP_TYPE_136BITS (0x1UL << 16)
#define RSP_TYPE_136BITS BIT16
#define RSP_TYPE_48BITS (0x2UL << 16)
#define CCCE_ENABLE (0x1UL << 19)
#define CICE_ENABLE (0x1UL << 20)
#define DP_ENABLE (0x1UL << 21)
#define CCCE_ENABLE BIT19
#define CICE_ENABLE BIT20
#define DP_ENABLE BIT21
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
@@ -76,84 +76,84 @@
#define MMCHS_DATA (MMCHS1BASE + 0x120)
#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
#define CMDI_MASK (0x1UL << 0)
#define CMDI_MASK BIT0
#define CMDI_ALLOWED (0x0UL << 0)
#define CMDI_NOT_ALLOWED (0x1UL << 0)
#define DATI_MASK (0x1UL << 1)
#define CMDI_NOT_ALLOWED BIT0
#define DATI_MASK BIT1
#define DATI_ALLOWED (0x0UL << 1)
#define DATI_NOT_ALLOWED (0x1UL << 1)
#define DATI_NOT_ALLOWED BIT1
#define MMCHS_HCTL (MMCHS1BASE + 0x128)
#define DTW_1_BIT (0x0UL << 1)
#define DTW_4_BIT (0x1UL << 1)
#define SDBP_MASK (0x1UL << 8)
#define DTW_4_BIT BIT1
#define SDBP_MASK BIT8
#define SDBP_OFF (0x0UL << 8)
#define SDBP_ON (0x1UL << 8)
#define SDBP_ON BIT8
#define SDVS_1_8_V (0x5UL << 9)
#define SDVS_3_0_V (0x6UL << 9)
#define IWE (0x1UL << 24)
#define IWE BIT24
#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
#define ICE (0x1UL << 0)
#define ICS_MASK (0x1UL << 1)
#define ICS (0x1UL << 1)
#define CEN (0x1UL << 2)
#define ICE BIT0
#define ICS_MASK BIT1
#define ICS BIT1
#define CEN BIT2
#define CLKD_MASK (0x3FFUL << 6)
#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
#define CLKD_400KHZ (0xF0UL)
#define DTO_MASK (0xFUL << 16)
#define DTO_VAL (0xEUL << 16)
#define SRA (0x1UL << 24)
#define SRC_MASK (0x1UL << 25)
#define SRC (0x1UL << 25)
#define SRD (0x1UL << 26)
#define SRA BIT24
#define SRC_MASK BIT25
#define SRC BIT25
#define SRD BIT26
#define MMCHS_STAT (MMCHS1BASE + 0x130)
#define CC (0x1UL << 0)
#define TC (0x1UL << 1)
#define BWR (0x1UL << 4)
#define BRR (0x1UL << 5)
#define ERRI (0x1UL << 15)
#define CTO (0x1UL << 16)
#define DTO (0x1UL << 20)
#define DCRC (0x1UL << 21)
#define DEB (0x1UL << 22)
#define CC BIT0
#define TC BIT1
#define BWR BIT4
#define BRR BIT5
#define ERRI BIT15
#define CTO BIT16
#define DTO BIT20
#define DCRC BIT21
#define DEB BIT22
#define MMCHS_IE (MMCHS1BASE + 0x134)
#define CC_EN (0x1UL << 0)
#define TC_EN (0x1UL << 1)
#define BWR_EN (0x1UL << 4)
#define BRR_EN (0x1UL << 5)
#define CTO_EN (0x1UL << 16)
#define CCRC_EN (0x1UL << 17)
#define CEB_EN (0x1UL << 18)
#define CIE_EN (0x1UL << 19)
#define DTO_EN (0x1UL << 20)
#define DCRC_EN (0x1UL << 21)
#define DEB_EN (0x1UL << 22)
#define CERR_EN (0x1UL << 28)
#define BADA_EN (0x1UL << 29)
#define CC_EN BIT0
#define TC_EN BIT1
#define BWR_EN BIT4
#define BRR_EN BIT5
#define CTO_EN BIT16
#define CCRC_EN BIT17
#define CEB_EN BIT18
#define CIE_EN BIT19
#define DTO_EN BIT20
#define DCRC_EN BIT21
#define DEB_EN BIT22
#define CERR_EN BIT28
#define BADA_EN BIT29
#define MMCHS_ISE (MMCHS1BASE + 0x138)
#define CC_SIGEN (0x1UL << 0)
#define TC_SIGEN (0x1UL << 1)
#define BWR_SIGEN (0x1UL << 4)
#define BRR_SIGEN (0x1UL << 5)
#define CTO_SIGEN (0x1UL << 16)
#define CCRC_SIGEN (0x1UL << 17)
#define CEB_SIGEN (0x1UL << 18)
#define CIE_SIGEN (0x1UL << 19)
#define DTO_SIGEN (0x1UL << 20)
#define DCRC_SIGEN (0x1UL << 21)
#define DEB_SIGEN (0x1UL << 22)
#define CERR_SIGEN (0x1UL << 28)
#define BADA_SIGEN (0x1UL << 29)
#define CC_SIGEN BIT0
#define TC_SIGEN BIT1
#define BWR_SIGEN BIT4
#define BRR_SIGEN BIT5
#define CTO_SIGEN BIT16
#define CCRC_SIGEN BIT17
#define CEB_SIGEN BIT18
#define CIE_SIGEN BIT19
#define DTO_SIGEN BIT20
#define DCRC_SIGEN BIT21
#define DEB_SIGEN BIT22
#define CERR_SIGEN BIT28
#define BADA_SIGEN BIT29
#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
#define MMCHS_CAPA (MMCHS1BASE + 0x140)
#define VS30 (0x1UL << 25)
#define VS18 (0x1UL << 26)
#define VS30 BIT25
#define VS18 BIT26
#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
#define MMCHS_REV (MMCHS1BASE + 0x1FC)
@@ -179,7 +179,7 @@
#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
#define CMD8_ARG (0x0UL << 12 | 0x1UL << 8 | 0xCEUL << 0)
#define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)

4
Omap35xxPkg/Include/Omap3530/Omap3530PadConfiguration.h
View File

@@ -281,9 +281,9 @@
#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
#define PULLUDDISABLE (0x0UL << 0)
#define PULLUDENABLE (0x1UL << 0)
#define PULLUDENABLE BIT0
#define PULLTYPENOSELECT (0x0UL << 1)
#define PULLTYPESELECT (0x1UL << 1)
#define PULLTYPESELECT BIT1
#define OUTPUT (0x0UL) //Pin is configured in output only mode.
#define INPUT (0x1UL) //Pin is configured in bi-directional mode.

86
Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h
View File

@@ -40,29 +40,29 @@
#define PRM_RSTST (0x48307258)
//CORE clock
#define CM_FCLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
#define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
#define CM_ICLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
#define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
#define CM_FCLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
#define CM_FCLKEN1_CORE_EN_MMC1_MASK BIT24
#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE BIT24
#define CM_FCLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
#define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
#define CM_ICLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
#define CM_ICLKEN1_CORE_EN_MMC1_MASK BIT24
#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE BIT24
#define CM_ICLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
#define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
#define CM_CLKEN_ENABLE (7UL << 0)
@@ -72,93 +72,93 @@
#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK (1UL << 1)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT1
#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE (1UL << 1)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK (1UL << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK BIT0
#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE (1UL << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE BIT0
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK (1UL << 0)
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK BIT0
#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE (1UL << 0)
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE BIT0
//Wakeup functional clock
#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE BIT3
#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE BIT5
//Wakeup interface clock
#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE BIT3
#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE BIT5
//Peripheral functional clock
#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
#define CM_FCLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
#define CM_FCLKEN_PER_EN_GPT3_ENABLE BIT4
#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
#define CM_FCLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
#define CM_FCLKEN_PER_EN_GPT4_ENABLE BIT5
#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
#define CM_FCLKEN_PER_EN_UART3_ENABLE (1UL << 11)
#define CM_FCLKEN_PER_EN_UART3_ENABLE BIT11
#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
#define CM_FCLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
#define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13
#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
#define CM_FCLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
#define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14
#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
#define CM_FCLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
#define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
#define CM_FCLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
#define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16
#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
#define CM_FCLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
#define CM_FCLKEN_PER_EN_GPIO6_ENABLE BIT17
//Peripheral interface clock
#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
#define CM_ICLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
#define CM_ICLKEN_PER_EN_GPT3_ENABLE BIT4
#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
#define CM_ICLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
#define CM_ICLKEN_PER_EN_GPT4_ENABLE BIT5
#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
#define CM_ICLKEN_PER_EN_UART3_ENABLE (1UL << 11)
#define CM_ICLKEN_PER_EN_UART3_ENABLE BIT11
#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
#define CM_ICLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
#define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13
#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
#define CM_ICLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
#define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14
#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
#define CM_ICLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
#define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
#define CM_ICLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
#define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16
#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
#define CM_ICLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
#define CM_ICLKEN_PER_EN_GPIO6_ENABLE BIT17
//Timer source clock selection
#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS (1UL << 1)
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1
#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS (1UL << 2)
#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
//Reset management (Global and Cold reset)
#define RST_GS (0x1UL << 1)
#define RST_DPLL3 (0x1UL << 2)
#define GLOBAL_SW_RST (0x1UL << 1)
#define RST_GS BIT1
#define RST_DPLL3 BIT2
#define GLOBAL_SW_RST BIT1
#define GLOBAL_COLD_RST (0x0UL << 0)
#endif // __OMAP3530PRCM_H__

22
Omap35xxPkg/Include/Omap3530/Omap3530Timer.h
View File

@@ -51,9 +51,9 @@
#define WSPR (0x048)
#define TISR_TCAR_IT_FLAG_MASK (1UL << 2)
#define TISR_OVF_IT_FLAG_MASK (1UL << 1)
#define TISR_MAT_IT_FLAG_MASK (1UL << 0)
#define TISR_TCAR_IT_FLAG_MASK BIT2
#define TISR_OVF_IT_FLAG_MASK BIT1
#define TISR_MAT_IT_FLAG_MASK BIT0
#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
@@ -61,21 +61,21 @@
#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
#define TISR_TCAR_IT_FLAG_CLEAR (1UL << 2)
#define TISR_OVF_IT_FLAG_CLEAR (1UL << 1)
#define TISR_MAT_IT_FLAG_CLEAR (1UL << 0)
#define TISR_TCAR_IT_FLAG_CLEAR BIT2
#define TISR_OVF_IT_FLAG_CLEAR BIT1
#define TISR_MAT_IT_FLAG_CLEAR BIT0
#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
#define TCLR_AR_AUTORELOAD (1UL << 1)
#define TCLR_AR_AUTORELOAD BIT1
#define TCLR_AR_ONESHOT (0UL << 1)
#define TCLR_ST_ON (1UL << 0)
#define TCLR_ST_ON BIT0
#define TCLR_ST_OFF (0UL << 0)
#define TIER_TCAR_IT_ENABLE (1UL << 2)
#define TIER_TCAR_IT_ENABLE (BIT2
#define TIER_TCAR_IT_DISABLE (0UL << 2)
#define TIER_OVF_IT_ENABLE (1UL << 1)
#define TIER_OVF_IT_ENABLE BIT1
#define TIER_OVF_IT_DISABLE (0UL << 1)
#define TIER_MAT_IT_ENABLE (1UL << 0)
#define TIER_MAT_IT_ENABLE BIT0
#define TIER_MAT_IT_DISABLE (0UL << 0)
#endif // __OMAP3530TIMER_H__

27
Omap35xxPkg/Include/Omap3530/Omap3530Uart.h
View File

@@ -29,25 +29,26 @@
#define UART_LSR_REG (0x0014)
#define UART_MDR1_REG (0x0020)
#define UART_FCR_TX_FIFO_CLEAR (1UL << 3)
#define UART_FCR_RX_FIFO_CLEAR (1UL << 3)
#define UART_FCR_FIFO_ENABLE (1UL << 3)
#define UART_FCR_TX_FIFO_CLEAR BIT2
#define UART_FCR_RX_FIFO_CLEAR BIT1
#define UART_FCR_FIFO_ENABLE BIT0
#define UART_LCR_DIV_EN_ENABLE (1UL << 7)
#define UART_LCR_DIV_EN_ENABLE BIT7
#define UART_LCR_DIV_EN_DISABLE (0UL << 7)
#define UART_LCR_CHAR_LENGTH_8 (3UL << 0)
#define UART_LCR_CHAR_LENGTH_8 (BIT1 | BIT0)
#define UART_MCR_RTS_FORCE_ACTIVE (1UL << 1)
#define UART_MCR_DTR_FORCE_ACTIVE (1UL << 0)
#define UART_MCR_RTS_FORCE_ACTIVE BIT1
#define UART_MCR_DTR_FORCE_ACTIVE BIT0
#define UART_LSR_TX_FIFO_E_MASK (1UL << 5)
#define UART_LSR_TX_FIFO_E_MASK BIT5
#define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5)
#define UART_LSR_TX_FIFO_E_EMPTY (1UL << 5)
#define UART_LSR_RX_FIFO_E_MASK (1UL << 0)
#define UART_LSR_RX_FIFO_E_NOT_EMPTY (1UL << 0)
#define UART_LSR_TX_FIFO_E_EMPTY BIT5
#define UART_LSR_RX_FIFO_E_MASK BIT0
#define UART_LSR_RX_FIFO_E_NOT_EMPTY BIT0
#define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0)
#define UART_MDR1_MODE_SELECT_DISABLE (7UL << 0)
#define UART_MDR1_MODE_SELECT_UART_16X (0UL << 0)
// BIT2:BIT0
#define UART_MDR1_MODE_SELECT_DISABLE (7UL)
#define UART_MDR1_MODE_SELECT_UART_16X (0UL)
#endif // __OMAP3530UART_H__

23
Omap35xxPkg/Include/Omap3530/Omap3530Usb.h
View File

@@ -23,20 +23,25 @@
#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY (1UL << 12)
#define UHH_SYSCONFIG_CLOCKACTIVITY_ON (1UL << 8)
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY (1UL << 3)
#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2)
#define UHH_SYSCONFIG_SOFTRESET (1UL << 1)
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY BIT12
#define UHH_SYSCONFIG_CLOCKACTIVITY_ON BIT8
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY BIT3
#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
#define UHH_SYSCONFIG_SOFTRESET BIT1
#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE (1UL << 4)
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE (1UL << 3)
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE (1UL << 2)
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9)
#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8)
#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5)
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE BIT4
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE BIT3
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2
#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1)
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0)
#define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
#endif // __OMAP3530USB_H__