Added DebugAgentTimerLib. Cleaned up .h files and other code.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10332 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
@@ -20,31 +20,31 @@
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#define MMC_REFERENCE_CLK (96000000)
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#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
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#define SOFTRESET (0x1UL << 1)
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#define ENAWAKEUP (0x1UL << 2)
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#define SOFTRESET BIT1
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#define ENAWAKEUP BIT2
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#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
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#define RESETDONE_MASK (0x1UL << 0)
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#define RESETDONE (0x1UL << 0)
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#define RESETDONE_MASK BIT0
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#define RESETDONE BIT0
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#define MMCHS_CSRE (MMCHS1BASE + 0x24)
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#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
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#define MMCHS_CON (MMCHS1BASE + 0x2C)
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#define OD (0x1UL << 0)
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#define OD BIT0
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#define NOINIT (0x0UL << 1)
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#define INIT (0x1UL << 1)
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#define HR (0x1UL << 2)
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#define STR (0x1UL << 3)
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#define MODE (0x1UL << 4)
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#define INIT BIT1
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#define HR BIT2
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#define STR BIT3
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#define MODE BIT4
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#define DW8_1_4_BIT (0x0UL << 5)
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#define DW8_8_BIT (0x1UL << 5)
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#define MIT (0x1UL << 6)
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#define CDP (0x1UL << 7)
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#define WPP (0x1UL << 8)
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#define CTPL (0x1UL << 11)
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#define DW8_8_BIT BIT5
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#define MIT BIT6
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#define CDP BIT7
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#define WPP BIT8
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#define CTPL BIT11
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#define CEATA_OFF (0x0UL << 12)
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#define CEATA_ON (0x1UL << 12)
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#define CEATA_ON BIT12
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#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
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@@ -54,19 +54,19 @@
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#define MMCHS_ARG (MMCHS1BASE + 0x108)
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#define MMCHS_CMD (MMCHS1BASE + 0x10C)
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#define DE_ENABLE (0x1UL << 0)
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#define BCE_ENABLE (0x1UL << 1)
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#define ACEN_ENABLE (0x1UL << 2)
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#define DDIR_READ (0x1UL << 4)
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#define DE_ENABLE BIT0
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#define BCE_ENABLE BIT1
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#define ACEN_ENABLE BIT2
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#define DDIR_READ BIT4
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#define DDIR_WRITE (0x0UL << 4)
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#define MSBS_SGLEBLK (0x0UL << 5)
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#define MSBS_MULTBLK (0x1UL << 5)
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#define MSBS_MULTBLK BIT5
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#define RSP_TYPE_MASK (0x3UL << 16)
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#define RSP_TYPE_136BITS (0x1UL << 16)
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#define RSP_TYPE_136BITS BIT16
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#define RSP_TYPE_48BITS (0x2UL << 16)
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#define CCCE_ENABLE (0x1UL << 19)
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#define CICE_ENABLE (0x1UL << 20)
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#define DP_ENABLE (0x1UL << 21)
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#define CCCE_ENABLE BIT19
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#define CICE_ENABLE BIT20
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#define DP_ENABLE BIT21
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#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
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#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
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@@ -76,84 +76,84 @@
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#define MMCHS_DATA (MMCHS1BASE + 0x120)
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#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
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#define CMDI_MASK (0x1UL << 0)
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#define CMDI_MASK BIT0
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#define CMDI_ALLOWED (0x0UL << 0)
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#define CMDI_NOT_ALLOWED (0x1UL << 0)
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#define DATI_MASK (0x1UL << 1)
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#define CMDI_NOT_ALLOWED BIT0
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#define DATI_MASK BIT1
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#define DATI_ALLOWED (0x0UL << 1)
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#define DATI_NOT_ALLOWED (0x1UL << 1)
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#define DATI_NOT_ALLOWED BIT1
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#define MMCHS_HCTL (MMCHS1BASE + 0x128)
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#define DTW_1_BIT (0x0UL << 1)
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#define DTW_4_BIT (0x1UL << 1)
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#define SDBP_MASK (0x1UL << 8)
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#define DTW_4_BIT BIT1
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#define SDBP_MASK BIT8
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#define SDBP_OFF (0x0UL << 8)
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#define SDBP_ON (0x1UL << 8)
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#define SDBP_ON BIT8
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#define SDVS_1_8_V (0x5UL << 9)
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#define SDVS_3_0_V (0x6UL << 9)
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#define IWE (0x1UL << 24)
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#define IWE BIT24
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#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
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#define ICE (0x1UL << 0)
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#define ICS_MASK (0x1UL << 1)
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#define ICS (0x1UL << 1)
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#define CEN (0x1UL << 2)
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#define ICE BIT0
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#define ICS_MASK BIT1
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#define ICS BIT1
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#define CEN BIT2
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#define CLKD_MASK (0x3FFUL << 6)
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#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
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#define CLKD_400KHZ (0xF0UL)
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#define DTO_MASK (0xFUL << 16)
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#define DTO_VAL (0xEUL << 16)
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#define SRA (0x1UL << 24)
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#define SRC_MASK (0x1UL << 25)
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#define SRC (0x1UL << 25)
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#define SRD (0x1UL << 26)
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#define SRA BIT24
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#define SRC_MASK BIT25
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#define SRC BIT25
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#define SRD BIT26
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#define MMCHS_STAT (MMCHS1BASE + 0x130)
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#define CC (0x1UL << 0)
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#define TC (0x1UL << 1)
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#define BWR (0x1UL << 4)
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#define BRR (0x1UL << 5)
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#define ERRI (0x1UL << 15)
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#define CTO (0x1UL << 16)
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#define DTO (0x1UL << 20)
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#define DCRC (0x1UL << 21)
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#define DEB (0x1UL << 22)
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#define CC BIT0
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#define TC BIT1
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#define BWR BIT4
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#define BRR BIT5
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#define ERRI BIT15
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#define CTO BIT16
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#define DTO BIT20
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#define DCRC BIT21
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#define DEB BIT22
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#define MMCHS_IE (MMCHS1BASE + 0x134)
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#define CC_EN (0x1UL << 0)
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#define TC_EN (0x1UL << 1)
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#define BWR_EN (0x1UL << 4)
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#define BRR_EN (0x1UL << 5)
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#define CTO_EN (0x1UL << 16)
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#define CCRC_EN (0x1UL << 17)
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#define CEB_EN (0x1UL << 18)
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#define CIE_EN (0x1UL << 19)
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#define DTO_EN (0x1UL << 20)
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#define DCRC_EN (0x1UL << 21)
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#define DEB_EN (0x1UL << 22)
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#define CERR_EN (0x1UL << 28)
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#define BADA_EN (0x1UL << 29)
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#define CC_EN BIT0
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#define TC_EN BIT1
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#define BWR_EN BIT4
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#define BRR_EN BIT5
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#define CTO_EN BIT16
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#define CCRC_EN BIT17
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#define CEB_EN BIT18
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#define CIE_EN BIT19
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#define DTO_EN BIT20
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#define DCRC_EN BIT21
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#define DEB_EN BIT22
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#define CERR_EN BIT28
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#define BADA_EN BIT29
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#define MMCHS_ISE (MMCHS1BASE + 0x138)
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#define CC_SIGEN (0x1UL << 0)
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#define TC_SIGEN (0x1UL << 1)
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#define BWR_SIGEN (0x1UL << 4)
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#define BRR_SIGEN (0x1UL << 5)
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#define CTO_SIGEN (0x1UL << 16)
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#define CCRC_SIGEN (0x1UL << 17)
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#define CEB_SIGEN (0x1UL << 18)
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#define CIE_SIGEN (0x1UL << 19)
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#define DTO_SIGEN (0x1UL << 20)
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#define DCRC_SIGEN (0x1UL << 21)
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#define DEB_SIGEN (0x1UL << 22)
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#define CERR_SIGEN (0x1UL << 28)
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#define BADA_SIGEN (0x1UL << 29)
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#define CC_SIGEN BIT0
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#define TC_SIGEN BIT1
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#define BWR_SIGEN BIT4
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#define BRR_SIGEN BIT5
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#define CTO_SIGEN BIT16
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#define CCRC_SIGEN BIT17
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#define CEB_SIGEN BIT18
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#define CIE_SIGEN BIT19
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#define DTO_SIGEN BIT20
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#define DCRC_SIGEN BIT21
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#define DEB_SIGEN BIT22
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#define CERR_SIGEN BIT28
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#define BADA_SIGEN BIT29
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#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
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#define MMCHS_CAPA (MMCHS1BASE + 0x140)
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#define VS30 (0x1UL << 25)
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#define VS18 (0x1UL << 26)
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#define VS30 BIT25
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#define VS18 BIT26
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#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
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#define MMCHS_REV (MMCHS1BASE + 0x1FC)
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@@ -179,7 +179,7 @@
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#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
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#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
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//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
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#define CMD8_ARG (0x0UL << 12 | 0x1UL << 8 | 0xCEUL << 0)
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#define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
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#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
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#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
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