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ArmPlatformPkg/ArmiVExpressPkg: Introduce 'ArmVExpress.dsc.inc' to avoid duplication of library and PCD defintions around ARM Versatile Express Boards

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12428 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-09-22 23:21:02 +00:00
parent f4ee7a8234
commit 4463f70698
7 changed files with 356 additions and 269 deletions
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18
ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h
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@@ -68,6 +68,7 @@
// PL111 Colour LCD Controller - core tile
#define PL111_CLCD_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x20000)
#define PL111_CLCD_SITE ARM_VE_DAUGHTERBOARD_1_SITE
// PL341 Dynamic Memory Controller Base
#define ARM_VE_DMC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)
@@ -76,13 +77,12 @@
#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
// System Configuration Controller register Base addresses
//#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
#define ARM_VE_SCC_BASE ARM_VE_SYS_CFG_CTRL_BASE
#define ARM_VE_SYS_CFGRW0_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
#define ARM_VE_SYS_CFGRW1_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)
#define ARM_VE_SYS_CFGRW2_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)
#define ARM_PLATFORM_SCC_BASE ARM_VE_SYS_CFGRW0_REG
// SP805 Watchdog on Cortex A9 core tile
#define SP805_WDOG_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)
@@ -118,16 +118,4 @@
#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)
#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)
/***********************************************************************************
// EFI Memory Map in Permanent Memory (DRAM)
************************************************************************************/
// This region is allocated at the bottom of the DRAM. It will be used
// for fixed address allocations such as Vector Table
#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB
// This region is the memory declared to PEI as permanent memory for PEI
// and DXE. EFI stacks and heaps will be declared in this region.
#define ARM_VE_EFI_MEMORY_REGION_SZ SIZE_256MB
#endif

16
ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h
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@@ -23,6 +23,7 @@
************************************************************************************/
// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
@@ -40,21 +41,6 @@
// SP810 Controller
#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
// Uart0
#define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)
// SP805 Watchdog on motherboard
#define SP805_WDOG_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x0F000)
// SP804 Timer Bases
#define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)
#define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)
#define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)
#define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)
// PL031 Real Time Clock
#define PL031_RTC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x17000)
// PL111 Colour LCD Controller - motherboard
#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)
#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1