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ArmPkg: Create MpCoreInfo PPI and HOB to describe CPU Cores on a MPCore platform

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These info are:
- ClusterId, CoreId
- MailBox Set/Get/Clear address



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12423 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-09-22 23:14:01 +00:00
parent 77de7e5372
commit 44788bae6f
23 changed files with 496 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
View File

@@ -452,6 +452,7 @@
}
ArmPlatformPkg/PlatformPei/PlatformPeim.inf
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
Nt32Pkg/BootModePei/BootModePei.inf
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
View File

@@ -460,6 +460,7 @@
}
ArmPlatformPkg/PlatformPei/PlatformPeim.inf
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
Nt32Pkg/BootModePei/BootModePei.inf
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf
View File

@@ -194,6 +194,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Core/Pei/PeiMain.inf
INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
INF ArmPkg/Drivers/CpuPei/CpuPei.inf
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf
View File

@@ -194,6 +194,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Core/Pei/PeiMain.inf
INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
INF ArmPkg/Drivers/CpuPei/CpuPei.inf
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf

3
ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h
View File

@@ -119,6 +119,9 @@
// L2x0 Cache Controller Base Address
//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/
#define ARM_EB_SYS_PROC_ID_MASK (0xFF << 24)
#define ARM_EB_SYS_PROC_ID_CORTEX_A8 (0x0E << 24)
#define ARM_EB_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)
/*******************************************
// EFI Memory Map in Permanent Memory (DRAM)

57
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c
View File

@@ -20,8 +20,33 @@
#include <Drivers/PL341Dmc.h>
#include <Drivers/SP804Timer.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <ArmPlatform.h>
ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = {
{
// Cluster 0, Core 0
0x0, 0x0,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 1
0x0, 0x1,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
}
};
/**
Return if Trustzone is supported by your platform
@@ -107,13 +132,41 @@ ArmPlatformInitializeSystemMemory (
{
// We do not need to initialize the System Memory on RTSM
}
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
)
{
if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) {
*CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
*ArmCoreTable = mRealViewEbMpCoreInfoTable;
return EFI_SUCCESS;
} else {
return EFI_UNSUPPORTED;
}
}
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&mArmMpCoreInfoPpiGuid,
&mMpCoreInfoPpi
}
};
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
*PpiListSize = 0;
*PpiList = NULL;
*PpiListSize = sizeof(gPlatformPpiTable);
*PpiList = gPlatformPpiTable;
}

1
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
View File

@@ -506,6 +506,7 @@
}
ArmPlatformPkg/PlatformPei/PlatformPeim.inf
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
Nt32Pkg/BootModePei/BootModePei.inf
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf

1
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
View File

@@ -226,6 +226,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Core/Pei/PeiMain.inf
INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
INF ArmPkg/Drivers/CpuPei/CpuPei.inf
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf

7
ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h
View File

@@ -62,8 +62,11 @@
// VRAM offset for the PL111 Colour LCD Controller on the motherboard
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
#define SYS_PROC_ID_UNSUPPORTED 0xFF
#define SYS_PROC_ID_CORTEX_A9 0x0C
#define ARM_VE_SYS_PROC_ID_MASK (0xFF << 24)
#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (0xFF << 24)
#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)
#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (0x12 << 24)
#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (0x14 << 24)
//
// Sites where the peripheral is fitted

74
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
View File

@@ -23,10 +23,55 @@
#include <Drivers/PL301Axi.h>
#include <Drivers/SP804Timer.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <ArmPlatform.h>
#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {
{
// Cluster 0, Core 0
0x0, 0x0,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 1
0x0, 0x1,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 2
0x0, 0x2,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 3
0x0, 0x3,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
}
};
// DDR2 timings
PL341_DMC_CONFIG DDRTimings = {
.MaxChip = 1,
@@ -154,13 +199,38 @@ ArmPlatformInitializeSystemMemory (
PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);
PL301AxiInit(ARM_VE_FAXI_BASE);
}
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
)
{
*CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);
*ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;
return EFI_SUCCESS;
}
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&mArmMpCoreInfoPpiGuid,
&mMpCoreInfoPpi
}
};
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
*PpiListSize = 0;
*PpiList = NULL;
*PpiListSize = sizeof(gPlatformPpiTable);
*PpiList = gPlatformPpiTable;
}

2
ArmPlatformPkg/PlatformPei/PlatformPeiLib.c
View File

@@ -27,8 +27,6 @@ PlatformPeim (
// Initialize the platform specific controllers
ArmPlatformNormalInitialize ();
BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));
BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize));
return EFI_SUCCESS;

62
ArmPlatformPkg/PrePeiCore/MainMPCore.c
View File

@@ -13,7 +13,9 @@
**/
#include <Library/ArmGicLib.h>
#include <Library/ArmMPCoreMailBoxLib.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <Chipset/ArmV7.h>
#include "PrePeiCore.h"
@@ -33,23 +35,63 @@ SecondaryMain (
IN UINTN MpId
)
{
// Function pointer to Secondary Core entry point
VOID (*secondary_start)(VOID);
UINTN secondary_entry_addr=0;
EFI_STATUS Status;
UINTN PpiListSize;
UINTN PpiListCount;
EFI_PEI_PPI_DESCRIPTOR *PpiList;
ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN Index;
UINTN ArmCoreCount;
ARM_CORE_INFO *ArmCoreInfoTable;
UINT32 ClusterId;
UINT32 CoreId;
VOID (*SecondaryStart)(VOID);
UINTN SecondaryEntryAddr;
ClusterId = GET_CLUSTER_ID(MpId);
CoreId = GET_CORE_ID(MpId);
// Get the gArmMpCoreInfoPpiGuid
PpiListSize = 0;
ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
break;
}
}
// On MP Core Platform we must implement the ARM MP Core Info PPI
ASSERT (Index != PpiListCount);
ArmMpCoreInfoPpi = PpiList->Ppi;
ArmCoreCount = 0;
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
ASSERT_EFI_ERROR (Status);
// Find the core in the ArmCoreTable
for (Index = 0; Index < ArmCoreCount; Index++) {
if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
break;
}
}
// The ARM Core Info Table must define every core
ASSERT (Index != ArmCoreCount);
// Clear Secondary cores MailBox
ArmClearMPCoreMailbox();
MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
ArmCallWFI();
SecondaryEntryAddr = 0;
while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {
ArmCallWFI ();
// Acknowledge the interrupt and send End of Interrupt signal.
ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
}
secondary_start = (VOID (*)())secondary_entry_addr;
// Jump to secondary core entry point.
secondary_start();
SecondaryStart = (VOID (*)())SecondaryEntryAddr;
SecondaryStart();
// The secondaries shouldn't reach here
ASSERT(FALSE);

1
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
View File

@@ -51,6 +51,7 @@
[Ppis]
gEfiTemporaryRamSupportPpiGuid
gArmGlobalVariablePpiGuid
gArmMpCoreInfoPpiGuid
[FeaturePcd]
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores

3
ArmPlatformPkg/PrePi/PrePi.c
View File

@@ -131,6 +131,9 @@ PrePiMain (
// Declare the Global Variable HOB
BuildGlobalVariableHob (GlobalVariableBase, FixedPcdGet32 (PcdPeiGlobalVariableSize));
//TODO: Call CpuPei as a library
BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));
// Set the Boot Mode
SetBootMode (ArmPlatformGetBootMode ());