ArmPkg: Create MpCoreInfo PPI and HOB to describe CPU Cores on a MPCore platform

These info are:
- ClusterId, CoreId
- MailBox Set/Get/Clear address



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12423 6f19259b-4bc3-4df7-8a09-765794883524

ArmPlatformPkg/PrePeiCore/MainMPCore.c

@@ -13,7 +13,9 @@
 **/
 
 #include <Library/ArmGicLib.h>
-#include <Library/ArmMPCoreMailBoxLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
 #include <Chipset/ArmV7.h>
 
 #include "PrePeiCore.h"
@@ -33,23 +35,63 @@ SecondaryMain (
   IN UINTN MpId
   )
 {
-  // Function pointer to Secondary Core entry point
-  VOID (*secondary_start)(VOID);
-  UINTN secondary_entry_addr=0;
+  EFI_STATUS              Status;
+  UINTN                   PpiListSize;
+  UINTN                   PpiListCount;
+  EFI_PEI_PPI_DESCRIPTOR  *PpiList;
+  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
+  UINTN                   Index;
+  UINTN                   ArmCoreCount;
+  ARM_CORE_INFO           *ArmCoreInfoTable;
+  UINT32                  ClusterId;
+  UINT32                  CoreId;
+  VOID                    (*SecondaryStart)(VOID);
+  UINTN                   SecondaryEntryAddr;
+
+  ClusterId = GET_CLUSTER_ID(MpId);
+  CoreId    = GET_CORE_ID(MpId);
+
+  // Get the gArmMpCoreInfoPpiGuid
+  PpiListSize = 0;
+  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
+  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
+  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
+    if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
+      break;
+    }
+  }
+
+  // On MP Core Platform we must implement the ARM MP Core Info PPI
+  ASSERT (Index != PpiListCount);
+
+  ArmMpCoreInfoPpi = PpiList->Ppi;
+  ArmCoreCount = 0;
+  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
+  ASSERT_EFI_ERROR (Status);
+
+  // Find the core in the ArmCoreTable
+  for (Index = 0; Index < ArmCoreCount; Index++) {
+    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
+      break;
+    }
+  }
+
+  // The ARM Core Info Table must define every core
+  ASSERT (Index != ArmCoreCount);
 
   // Clear Secondary cores MailBox
-  ArmClearMPCoreMailbox();
+  MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
 
-  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
-    ArmCallWFI();
+  SecondaryEntryAddr = 0;
+  while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {
+    ArmCallWFI ();
     // Acknowledge the interrupt and send End of Interrupt signal.
     ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
   }
 
-  secondary_start = (VOID (*)())secondary_entry_addr;
-
   // Jump to secondary core entry point.
-  secondary_start();
+  SecondaryStart = (VOID (*)())SecondaryEntryAddr;
+  SecondaryStart();
 
   // The secondaries shouldn't reach here
   ASSERT(FALSE);