UefiCpuPkg/SmmCpuFeaturesLib: Remove .S files for IA32 and X64 arch
.nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Shenglei Zhang
committed by
Liming Gao
Liming Gao
parent
a8ac75b8ee
commit
475a4317c0
@@ -1,278 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# SmiEntry.S
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#
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# Abstract:
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#
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# Code template of the SMI handler for a particular processor
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(gcStmSmiHandlerTemplate)
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ASM_GLOBAL ASM_PFX(gcStmSmiHandlerSize)
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ASM_GLOBAL ASM_PFX(gcStmSmiHandlerOffset)
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ASM_GLOBAL ASM_PFX(gStmSmiCr3)
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ASM_GLOBAL ASM_PFX(gStmSmiStack)
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ASM_GLOBAL ASM_PFX(gStmSmbase)
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ASM_GLOBAL ASM_PFX(gStmXdSupported)
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ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
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ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
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.equ MSR_IA32_MISC_ENABLE, 0x1A0
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.equ MSR_EFER, 0xc0000080
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.equ MSR_EFER_XD, 0x800
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#
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# Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
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#
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.equ DSC_OFFSET, 0xfb00
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.equ DSC_GDTPTR, 0x48
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.equ DSC_GDTSIZ, 0x50
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.equ DSC_CS, 0x14
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.equ DSC_DS, 0x16
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.equ DSC_SS, 0x18
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.equ DSC_OTHERSEG, 0x1A
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.equ PROTECT_MODE_CS, 0x08
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.equ PROTECT_MODE_DS, 0x20
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.equ TSS_SEGMENT, 0x40
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.text
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ASM_PFX(gcStmSmiHandlerTemplate):
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_StmSmiEntryPoint:
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.byte 0xbb # mov bx, imm16
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.word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
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.byte 0x2e,0xa1 # mov ax, cs:[offset16]
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.word DSC_OFFSET + DSC_GDTSIZ
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decl %eax
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movl %eax, %cs:(%edi) # mov cs:[bx], ax
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.byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
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.word DSC_OFFSET + DSC_GDTPTR
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movw %ax, %cs:2(%edi)
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movw %ax, %bp # ebp = GDT base
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.byte 0x66
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lgdt %cs:(%edi)
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# Patch ProtectedMode Segment
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.byte 0xb8 # mov ax, imm16
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.word PROTECT_MODE_CS # set AX for segment directly
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movl %eax, %cs:-2(%edi) # mov cs:[bx - 2], ax
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# Patch ProtectedMode entry
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.byte 0x66, 0xbf # mov edi, SMBASE
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ASM_PFX(gStmSmbase): .space 4
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.byte 0x67
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lea ((Start32bit - _StmSmiEntryPoint) + 0x8000)(%edi), %ax
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movw %ax, %cs:-6(%edi)
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movl %cr0, %ebx
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.byte 0x66
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andl $0x9ffafff3, %ebx
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.byte 0x66
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orl $0x23, %ebx
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movl %ebx, %cr0
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.byte 0x66,0xea
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.space 4
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.space 2
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_StmGdtDesc: .space 4
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.space 2
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Start32bit:
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movw $PROTECT_MODE_DS, %ax
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movl %eax,%ds
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movl %eax,%es
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movl %eax,%fs
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movl %eax,%gs
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movl %eax,%ss
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.byte 0xbc # mov esp, imm32
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ASM_PFX(gStmSmiStack): .space 4
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movl $ASM_PFX(gStmSmiHandlerIdtr), %eax
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lidt (%eax)
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jmp ProtFlatMode
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ProtFlatMode:
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.byte 0xb8 # mov eax, imm32
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ASM_PFX(gStmSmiCr3): .space 4
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movl %eax, %cr3
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#
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# Need to test for CR4 specific bit support
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#
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movl $1, %eax
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cpuid # use CPUID to determine if specific CR4 bits are supported
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xorl %eax, %eax # Clear EAX
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testl $BIT2, %edx # Check for DE capabilities
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jz L8
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orl $BIT3, %eax
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L8:
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testl $BIT6, %edx # Check for PAE capabilities
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jz L9
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orl $BIT5, %eax
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L9:
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testl $BIT7, %edx # Check for MCE capabilities
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jz L10
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orl $BIT6, %eax
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L10:
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testl $BIT24, %edx # Check for FXSR capabilities
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jz L11
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orl $BIT9, %eax
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L11:
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testl $BIT25, %edx # Check for SSE capabilities
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jz L12
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orl $BIT10, %eax
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L12: # as cr4.PGE is not set here, refresh cr3
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movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
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cmpb $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
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jz L5
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# Load TSS
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movb $0x89, (TSS_SEGMENT + 5)(%ebp) # clear busy flag
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movl $TSS_SEGMENT, %eax
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ltrw %ax
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L5:
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# enable NXE if supported
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.byte 0xb0 # mov al, imm8
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ASM_PFX(gStmXdSupported): .byte 1
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cmpb $0, %al
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jz SkipXd
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#
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# Check XD disable bit
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#
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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pushl %edx # save MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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jz L13
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andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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wrmsr
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L13:
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movl $MSR_EFER, %ecx
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rdmsr
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orw $MSR_EFER_XD,%ax # enable NXE
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wrmsr
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jmp XdDone
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SkipXd:
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subl $4, %esp
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XdDone:
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movl %cr0, %ebx
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orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
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movl %ebx, %cr0
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leal DSC_OFFSET(%edi),%ebx
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movw DSC_DS(%ebx),%ax
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movl %eax, %ds
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movw DSC_OTHERSEG(%ebx),%ax
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movl %eax, %es
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movl %eax, %fs
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movl %eax, %gs
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movw DSC_SS(%ebx),%ax
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movl %eax, %ss
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CommonHandler:
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movl 4(%esp), %ebx
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pushl %ebx
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movl $ASM_PFX(CpuSmmDebugEntry), %eax
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call *%eax
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addl $4, %esp
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pushl %ebx
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movl $ASM_PFX(SmiRendezvous), %eax
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call *%eax
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addl $4, %esp
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pushl %ebx
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movl $ASM_PFX(CpuSmmDebugExit), %eax
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call *%eax
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addl $4, %esp
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movl $ASM_PFX(gStmXdSupported), %eax
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movb (%eax), %al
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cmpb $0, %al
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jz L16
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popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx
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jz L16
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
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wrmsr
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L16:
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rsm
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_StmSmiHandler:
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#
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# Check XD disable bit
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#
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xorl %esi, %esi
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movl $ASM_PFX(gStmXdSupported), %eax
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movb (%eax), %al
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cmpb $0, %al
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jz StmXdDone
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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jz L14
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andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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wrmsr
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L14:
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movl $MSR_EFER, %ecx
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rdmsr
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orw $MSR_EFER_XD,%ax # enable NXE
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wrmsr
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StmXdDone:
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push %esi
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# below step is needed, because STM does not run above code.
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# we have to run below code to set IDT/CR0/CR4
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movl $ASM_PFX(gStmSmiHandlerIdtr), %eax
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lidt (%eax)
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movl %cr0, %eax
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orl $0x80010023, %eax # enable paging + WP + NE + MP + PE
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movl %eax, %cr0
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#
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# Need to test for CR4 specific bit support
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#
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movl $1, %eax
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cpuid # use CPUID to determine if specific CR4 bits are supported
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movl %cr4, %eax # init EAX
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testl $BIT2, %edx # Check for DE capabilities
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jz L28
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orl $BIT3, %eax
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L28:
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testl $BIT6, %edx # Check for PAE capabilities
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jz L29
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orl $BIT5, %eax
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L29:
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testl $BIT7, %edx # Check for MCE capabilities
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jz L30
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orl $BIT6, %eax
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L30:
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testl $BIT24, %edx # Check for FXSR capabilities
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jz L31
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orl $BIT9, %eax
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L31:
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testl $BIT25, %edx # Check for SSE capabilities
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jz L32
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orl $BIT10, %eax
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L32: # as cr4.PGE is not set here, refresh cr3
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movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
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# STM init finish
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jmp CommonHandler
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ASM_PFX(gcStmSmiHandlerSize) : .word . - _StmSmiEntryPoint
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ASM_PFX(gcStmSmiHandlerOffset): .word _StmSmiHandler - _StmSmiEntryPoint
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@@ -1,174 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# SmiException.S
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#
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# Abstract:
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#
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# Exception handlers used in SM mode
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(gcStmPsd)
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ASM_GLOBAL ASM_PFX(SmmStmExceptionHandler)
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ASM_GLOBAL ASM_PFX(SmmStmSetup)
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ASM_GLOBAL ASM_PFX(SmmStmTeardown)
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.equ MSR_IA32_MISC_ENABLE, 0x1A0
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.equ MSR_EFER, 0xc0000080
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.equ MSR_EFER_XD, 0x800
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.equ CODE_SEL, 0x08
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.equ DATA_SEL, 0x20
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.equ TSS_SEL, 0x40
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.data
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ASM_PFX(gcStmPsd):
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.ascii "TXTPSSIG"
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.word PSD_SIZE
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.word 1 # Version
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.long 0 # LocalApicId
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.byte 0x5 # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
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.byte 0 # BIOS to STM
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.byte 0 # STM to BIOS
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.byte 0
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.word CODE_SEL
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.word DATA_SEL
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.word DATA_SEL
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.word DATA_SEL
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.word TSS_SEL
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.word 0
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.quad 0 # SmmCr3
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.long ASM_PFX(_OnStmSetup)
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.long 0
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.long ASM_PFX(_OnStmTeardown)
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.long 0
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.quad 0 # SmmSmiHandlerRip - SMM guest entrypoint
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.quad 0 # SmmSmiHandlerRsp
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.quad 0
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.long 0
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.long 0x80010100 # RequiredStmSmmRevId
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.long ASM_PFX(_OnException)
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.long 0
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.quad 0 # ExceptionStack
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.word DATA_SEL
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.word 0x1F # ExceptionFilter
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.long 0
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.quad 0
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.quad 0 # BiosHwResourceRequirementsPtr
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.quad 0 # AcpiRsdp
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.byte 0 # PhysicalAddressBits
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.equ PSD_SIZE, . - ASM_PFX(gcStmPsd)
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.text
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#------------------------------------------------------------------------------
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# SMM Exception handlers
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(_OnException)
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ASM_PFX(_OnException):
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movl %esp, %ecx
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pushl %ecx
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call ASM_PFX(SmmStmExceptionHandler)
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addl $4, %esp
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movl %eax, %ebx
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movl $4, %eax
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.byte 0xf, 0x1, 0xc1 # VMCALL
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jmp .
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ASM_GLOBAL ASM_PFX(_OnStmSetup)
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ASM_PFX(_OnStmSetup):
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#
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# Check XD disable bit
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#
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xorl %esi, %esi
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movl $ASM_PFX(gStmXdSupported), %eax
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movb (%eax), %al
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cmpb $0, %al
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jz StmXdDone1
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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jz L13
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andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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wrmsr
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L13:
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movl $MSR_EFER, %ecx
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rdmsr
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orw $MSR_EFER_XD,%ax # enable NXE
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wrmsr
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StmXdDone1:
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push %esi
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call ASM_PFX(SmmStmSetup)
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movl $ASM_PFX(gStmXdSupported), %eax
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movb (%eax), %al
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cmpb $0, %al
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jz L14
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popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx
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jz L14
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
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wrmsr
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L14:
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rsm
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ASM_GLOBAL ASM_PFX(_OnStmTeardown)
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ASM_PFX(_OnStmTeardown):
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#
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# Check XD disable bit
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#
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xorl %esi, %esi
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movl $ASM_PFX(gStmXdSupported), %eax
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movb (%eax), %al
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cmpb $0, %al
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jz StmXdDone2
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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jz L15
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andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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wrmsr
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L15:
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movl $MSR_EFER, %ecx
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rdmsr
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orw $MSR_EFER_XD,%ax # enable NXE
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wrmsr
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StmXdDone2:
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push %esi
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call ASM_PFX(SmmStmTeardown)
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movl $ASM_PFX(gStmXdSupported), %eax
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movb (%eax), %al
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cmpb $0, %al
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jz L16
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popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx
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jz L16
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
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wrmsr
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L16:
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rsm
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Reference in New Issue
Block a user