IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Add FSP-I API entry point for SMM support. Also update 64bit API entry code to assign ApiIdx to RAX to avoid confusion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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Hongbin1 Zhang
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mergify[bot]
mergify[bot]
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24eac4caf3
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4824924377
@@ -614,4 +614,23 @@ EFI_STATUS
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IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr
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);
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/**
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This FSP API initializes SMM and provide any OS runtime silicon services,
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including Reliability, Availability, and Serviceability (RAS) features implemented by the CPU.
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@param[in] FspiUpdDataPtr Pointer to the FSPI_UPD data structure.
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If NULL, FSP will use the default parameters.
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@retval EFI_SUCCESS FSP execution environment was initialized successfully.
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@retval EFI_INVALID_PARAMETER Input parameters are invalid.
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@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
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@retval EFI_DEVICE_ERROR FSP initialization failed.
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@retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *FSP_SMM_INIT)(
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IN VOID *FspiUpdDataPtr
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);
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#endif
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@@ -10,9 +10,9 @@
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#include <FspEas.h>
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#define FSP_IN_API_MODE 0
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#define FSP_IN_DISPATCH_MODE 1
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#define FSP_GLOBAL_DATA_VERSION 1
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#define FSP_IN_API_MODE 0
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#define FSP_IN_DISPATCH_MODE 1
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#define FSP_GLOBAL_DATA_VERSION 1
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#pragma pack(1)
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@@ -24,16 +24,17 @@ typedef enum {
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TempRamExitApiIndex,
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FspSiliconInitApiIndex,
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FspMultiPhaseSiInitApiIndex,
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FspSmmInitApiIndex,
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FspApiIndexMax
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} FSP_API_INDEX;
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typedef struct {
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VOID *DataPtr;
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UINTN MicrocodeRegionBase;
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UINTN MicrocodeRegionSize;
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UINTN CodeRegionBase;
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UINTN CodeRegionSize;
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UINTN Reserved;
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VOID *DataPtr;
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UINTN MicrocodeRegionBase;
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UINTN MicrocodeRegionSize;
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UINTN CodeRegionBase;
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UINTN CodeRegionSize;
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UINTN Reserved;
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} FSP_PLAT_DATA;
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#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
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@@ -41,28 +42,28 @@ typedef struct {
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#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
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typedef struct {
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UINT32 Signature;
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UINT8 Version;
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UINT8 Reserved1[3];
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UINT32 Signature;
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UINT8 Version;
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UINT8 Reserved1[3];
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///
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/// Offset 0x08
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///
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UINTN CoreStack;
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UINTN Reserved2;
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UINTN CoreStack;
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UINTN Reserved2;
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///
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/// IA32: Offset 0x10; X64: Offset 0x18
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///
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UINT32 StatusCode;
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UINT8 ApiIdx;
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UINT32 StatusCode;
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UINT8 ApiIdx;
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///
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/// 0: FSP in API mode; 1: FSP in DISPATCH mode
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///
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UINT8 FspMode;
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UINT8 OnSeparateStack;
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UINT8 Reserved3;
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UINT32 NumberOfPhases;
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UINT32 PhasesExecuted;
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UINT32 Reserved4[8];
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UINT8 FspMode;
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UINT8 OnSeparateStack;
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UINT8 Reserved3;
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UINT32 NumberOfPhases;
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UINT32 PhasesExecuted;
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UINT32 Reserved4[8];
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///
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/// IA32: Offset 0x40; X64: Offset 0x48
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/// Start of UINTN and pointer section
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@@ -75,21 +76,23 @@ typedef struct {
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VOID *TempRamInitUpdPtr;
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VOID *MemoryInitUpdPtr;
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VOID *SiliconInitUpdPtr;
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VOID *SmmInitUpdPtr;
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///
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/// IA32: Offset 0x64; X64: Offset 0x90
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/// IA32: Offset 0x68; X64: Offset 0x98
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/// To store function parameters pointer
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/// so it can be retrieved after stack switched.
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///
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VOID *FunctionParameterPtr;
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FSP_INFO_HEADER *FspInfoHeader;
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VOID *UpdDataPtr;
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UINTN Reserved5;
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///
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/// End of UINTN and pointer section
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///
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UINT8 Reserved5[16];
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UINT8 Reserved6[16];
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UINT32 PerfSig;
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UINT16 PerfLen;
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UINT16 Reserved6;
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UINT16 Reserved7;
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UINT32 PerfIdx;
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UINT64 PerfData[32];
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} FSP_GLOBAL_DATA;
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@@ -26,13 +26,13 @@
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#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
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#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0
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#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
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#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2
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#define FSP_IA32 0
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#define FSP_X64 1
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#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0
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#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
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#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2
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#define FSP_IA32 0
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#define FSP_X64 1
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#pragma pack(1)
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#pragma pack(1)
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///
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/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.
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@@ -159,6 +159,14 @@ typedef struct {
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/// Byte 0x4E: Reserved4.
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///
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UINT16 Reserved4;
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///
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/// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.
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///
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UINT32 FspMultiPhaseMemInitEntryOffset;
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///
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/// Byte 0x54: Offset for the API to initialize SMM.
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///
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UINT32 FspSmmInitEntryOffset;
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} FSP_INFO_HEADER;
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///
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@@ -240,7 +248,7 @@ typedef struct {
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// UINT32 PatchData[];
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} FSP_PATCH_TABLE;
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#pragma pack()
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#pragma pack()
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extern EFI_GUID gFspHeaderFileGuid;
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