IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Add FSP-I API entry point for SMM support. Also update 64bit API entry code to assign ApiIdx to RAX to avoid confusion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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@@ -26,13 +26,13 @@
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#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
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#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0
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#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
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#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2
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#define FSP_IA32 0
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#define FSP_X64 1
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#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0
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#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
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#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2
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#define FSP_IA32 0
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#define FSP_X64 1
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#pragma pack(1)
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#pragma pack(1)
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///
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/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.
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@@ -159,6 +159,14 @@ typedef struct {
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/// Byte 0x4E: Reserved4.
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///
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UINT16 Reserved4;
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///
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/// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.
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///
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UINT32 FspMultiPhaseMemInitEntryOffset;
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///
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/// Byte 0x54: Offset for the API to initialize SMM.
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///
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UINT32 FspSmmInitEntryOffset;
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} FSP_INFO_HEADER;
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///
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@@ -240,7 +248,7 @@ typedef struct {
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// UINT32 PatchData[];
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} FSP_PATCH_TABLE;
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#pragma pack()
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#pragma pack()
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extern EFI_GUID gFspHeaderFileGuid;
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