MdeModulePkg/SdMmc: Add EDKII SD/MMC stack
This stack includes:
1. Dxe phase support by:
1) SdMmcPciHcDxe driver to consume PciIo and produce
SdMmcPassThru.
2) SdDxe driver to consume SdMmcPassThru to produce
BlkIo1/BlkIo2.
3) EmmcDxe driver to consume SdMmcPassThru to produce
BlkIo1/BlkIo2/SSP.
2. Pei phase support
1) SdBlockIoPei driver to consume SdMmcHostController
Ppi and produce VirutalBlkIo1&2.
2) EmmcBlockIoPei driver to consume SdMmcHostController
Ppi and produce VirutalBlkIo1&2.
3) SdMmcPciHcPei driver to produce SdMmcHostController
Ppi.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Feng Tian
354
MdeModulePkg/Bus/Sd/SdBlockIoPei/SdHci.h
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354
MdeModulePkg/Bus/Sd/SdBlockIoPei/SdHci.h
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/** @file
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Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _SD_HCI_H_
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#define _SD_HCI_H_
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//
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// SD Host Controller MMIO Register Offset
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//
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#define SD_HC_SDMA_ADDR 0x00
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#define SD_HC_ARG2 0x00
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#define SD_HC_BLK_SIZE 0x04
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#define SD_HC_BLK_COUNT 0x06
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#define SD_HC_ARG1 0x08
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#define SD_HC_TRANS_MOD 0x0C
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#define SD_HC_COMMAND 0x0E
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#define SD_HC_RESPONSE 0x10
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#define SD_HC_BUF_DAT_PORT 0x20
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#define SD_HC_PRESENT_STATE 0x24
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#define SD_HC_HOST_CTRL1 0x28
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#define SD_HC_POWER_CTRL 0x29
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#define SD_HC_BLK_GAP_CTRL 0x2A
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#define SD_HC_WAKEUP_CTRL 0x2B
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#define SD_HC_CLOCK_CTRL 0x2C
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#define SD_HC_TIMEOUT_CTRL 0x2E
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#define SD_HC_SW_RST 0x2F
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#define SD_HC_NOR_INT_STS 0x30
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#define SD_HC_ERR_INT_STS 0x32
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#define SD_HC_NOR_INT_STS_EN 0x34
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#define SD_HC_ERR_INT_STS_EN 0x36
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#define SD_HC_NOR_INT_SIG_EN 0x38
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#define SD_HC_ERR_INT_SIG_EN 0x3A
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#define SD_HC_AUTO_CMD_ERR_STS 0x3C
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#define SD_HC_HOST_CTRL2 0x3E
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#define SD_HC_CAP 0x40
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#define SD_HC_MAX_CURRENT_CAP 0x48
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#define SD_HC_FORCE_EVT_AUTO_CMD 0x50
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#define SD_HC_FORCE_EVT_ERR_INT 0x52
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#define SD_HC_ADMA_ERR_STS 0x54
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#define SD_HC_ADMA_SYS_ADDR 0x58
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#define SD_HC_PRESET_VAL 0x60
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#define SD_HC_SHARED_BUS_CTRL 0xE0
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#define SD_HC_SLOT_INT_STS 0xFC
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#define SD_HC_CTRL_VER 0xFE
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//
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// The transfer modes supported by SD Host Controller
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// Simplified Spec 3.0 Table 1-2
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//
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typedef enum {
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SdNoData,
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SdPioMode,
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SdSdmaMode,
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SdAdmaMode
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} SD_HC_TRANSFER_MODE;
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//
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// The maximum data length of each descriptor line
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//
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#define ADMA_MAX_DATA_PER_LINE 0x10000
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#define SD_SDMA_BOUNDARY 512 * 1024
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#define SD_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
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typedef enum {
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SdCommandTypeBc, // Broadcast commands, no response
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SdCommandTypeBcr, // Broadcast commands with response
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SdCommandTypeAc, // Addressed(point-to-point) commands
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SdCommandTypeAdtc // Addressed(point-to-point) data transfer commands
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} SD_COMMAND_TYPE;
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typedef enum {
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SdResponseTypeR1,
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SdResponseTypeR1b,
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SdResponseTypeR2,
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SdResponseTypeR3,
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SdResponseTypeR4,
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SdResponseTypeR5,
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SdResponseTypeR5b,
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SdResponseTypeR6,
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SdResponseTypeR7
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} SD_RESPONSE_TYPE;
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typedef struct _SD_COMMAND_BLOCK {
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UINT16 CommandIndex;
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UINT32 CommandArgument;
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UINT32 CommandType; // One of the SD_COMMAND_TYPE values
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UINT32 ResponseType; // One of the SD_RESPONSE_TYPE values
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} SD_COMMAND_BLOCK;
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typedef struct _SD_STATUS_BLOCK {
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UINT32 Resp0;
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UINT32 Resp1;
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UINT32 Resp2;
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UINT32 Resp3;
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} SD_STATUS_BLOCK;
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typedef struct _SD_COMMAND_PACKET {
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UINT64 Timeout;
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SD_COMMAND_BLOCK *SdCmdBlk;
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SD_STATUS_BLOCK *SdStatusBlk;
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VOID *InDataBuffer;
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VOID *OutDataBuffer;
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UINT32 InTransferLength;
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UINT32 OutTransferLength;
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} SD_COMMAND_PACKET;
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#pragma pack(1)
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typedef struct {
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UINT32 Valid:1;
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UINT32 End:1;
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UINT32 Int:1;
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UINT32 Reserved:1;
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UINT32 Act:2;
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UINT32 Reserved1:10;
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UINT32 Length:16;
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UINT32 Address;
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} SD_HC_ADMA_DESC_LINE;
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typedef struct {
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UINT32 TimeoutFreq:6; // bit 0:5
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UINT32 Reserved:1; // bit 6
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UINT32 TimeoutUnit:1; // bit 7
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UINT32 BaseClkFreq:8; // bit 8:15
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UINT32 MaxBlkLen:2; // bit 16:17
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UINT32 BusWidth8:1; // bit 18
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UINT32 Adma2:1; // bit 19
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UINT32 Reserved2:1; // bit 20
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UINT32 HighSpeed:1; // bit 21
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UINT32 Sdma:1; // bit 22
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UINT32 SuspRes:1; // bit 23
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UINT32 Voltage33:1; // bit 24
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UINT32 Voltage30:1; // bit 25
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UINT32 Voltage18:1; // bit 26
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UINT32 Reserved3:1; // bit 27
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UINT32 SysBus64:1; // bit 28
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UINT32 AsyncInt:1; // bit 29
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UINT32 SlotType:2; // bit 30:31
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UINT32 Sdr50:1; // bit 32
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UINT32 Sdr104:1; // bit 33
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UINT32 Ddr50:1; // bit 34
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UINT32 Reserved4:1; // bit 35
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UINT32 DriverTypeA:1; // bit 36
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UINT32 DriverTypeC:1; // bit 37
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UINT32 DriverTypeD:1; // bit 38
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UINT32 DriverType4:1; // bit 39
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UINT32 TimerCount:4; // bit 40:43
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UINT32 Reserved5:1; // bit 44
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UINT32 TuningSDR50:1; // bit 45
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UINT32 RetuningMod:2; // bit 46:47
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UINT32 ClkMultiplier:8; // bit 48:55
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UINT32 Reserved6:7; // bit 56:62
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UINT32 Hs400:1; // bit 63
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} SD_HC_SLOT_CAP;
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#pragma pack()
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/**
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Software reset the specified SD host controller and enable all interrupts.
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@param[in] Bar The mmio base address of the slot to be accessed.
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@retval EFI_SUCCESS The software reset executes successfully.
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@retval Others The software reset fails.
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**/
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EFI_STATUS
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SdPeimHcReset (
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IN UINTN Bar
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);
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/**
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Set all interrupt status bits in Normal and Error Interrupt Status Enable
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register.
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@param[in] Bar The mmio base address of the slot to be accessed.
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@retval EFI_SUCCESS The operation executes successfully.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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SdPeimHcEnableInterrupt (
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IN UINTN Bar
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);
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/**
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Get the capability data from the specified slot.
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@param[in] Bar The mmio base address of the slot to be accessed.
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@param[out] Capability The buffer to store the capability data.
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@retval EFI_SUCCESS The operation executes successfully.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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SdPeimHcGetCapability (
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IN UINTN Bar,
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OUT SD_HC_SLOT_CAP *Capability
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);
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/**
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Detect whether there is a SD card attached at the specified SD host controller
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slot.
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Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
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@param[in] Bar The mmio base address of the slot to be accessed.
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@retval EFI_SUCCESS There is a SD card attached.
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@retval EFI_NO_MEDIA There is not a SD card attached.
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@retval Others The detection fails.
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**/
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EFI_STATUS
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SdPeimHcCardDetect (
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IN UINTN Bar
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);
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/**
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Initial SD host controller with lowest clock frequency, max power and max timeout value
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at initialization.
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@param[in] Bar The mmio base address of the slot to be accessed.
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@retval EFI_SUCCESS The host controller is initialized successfully.
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@retval Others The host controller isn't initialized successfully.
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**/
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EFI_STATUS
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SdPeimHcInitHost (
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IN UINTN Bar
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);
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/**
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Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.
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Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
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@param[in] Slot The slot number of the SD card to send the command to.
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@param[in] AccessMode The value for access mode group.
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@param[in] CommandSystem The value for command set group.
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@param[in] DriveStrength The value for drive length group.
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@param[in] PowerLimit The value for power limit group.
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@param[in] Mode Switch or check function.
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@retval EFI_SUCCESS The operation is done correctly.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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SdPeimSwitch (
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IN SD_PEIM_HC_SLOT *Slot,
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IN UINT8 AccessMode,
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IN UINT8 CommandSystem,
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IN UINT8 DriveStrength,
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IN UINT8 PowerLimit,
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IN BOOLEAN Mode
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);
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/**
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Send command READ_SINGLE_BLOCK/WRITE_SINGLE_BLOCK to the addressed SD device
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to read/write the specified number of blocks.
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Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
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@param[in] Slot The slot number of the SD card to send the command to.
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@param[in] Lba The logical block address of starting access.
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@param[in] BlockSize The block size of specified SD device partition.
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@param[in] Buffer The pointer to the transfer buffer.
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@param[in] BufferSize The size of transfer buffer.
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@param[in] IsRead Boolean to show the operation direction.
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@retval EFI_SUCCESS The operation is done correctly.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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SdPeimRwSingleBlock (
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IN SD_PEIM_HC_SLOT *Slot,
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IN EFI_LBA Lba,
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IN UINT32 BlockSize,
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IN VOID *Buffer,
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IN UINTN BufferSize,
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IN BOOLEAN IsRead
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);
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/**
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Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed SD device
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to read/write the specified number of blocks.
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Refer to SD Electrical Standard Spec 5.1 Section 6.10.4 for details.
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@param[in] Slot The slot number of the Sd card to send the command to.
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@param[in] Lba The logical block address of starting access.
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@param[in] BlockSize The block size of specified SD device partition.
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@param[in] Buffer The pointer to the transfer buffer.
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@param[in] BufferSize The size of transfer buffer.
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@param[in] IsRead Boolean to show the operation direction.
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@retval EFI_SUCCESS The operation is done correctly.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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SdPeimRwMultiBlocks (
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IN SD_PEIM_HC_SLOT *Slot,
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IN EFI_LBA Lba,
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IN UINT32 BlockSize,
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IN VOID *Buffer,
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IN UINTN BufferSize,
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IN BOOLEAN IsRead
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);
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/**
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Execute SD device identification procedure.
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Refer to SD Electrical Standard Spec 5.1 Section 6.4 for details.
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@param[in] Slot The slot number of the Sd card to send the command to.
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@retval EFI_SUCCESS There is a SD card.
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@retval Others There is not a SD card.
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**/
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EFI_STATUS
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SdPeimIdentification (
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IN SD_PEIM_HC_SLOT *Slot
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);
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/**
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Free the resource used by the TRB.
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@param[in] Trb The pointer to the SD_TRB instance.
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**/
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VOID
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SdPeimFreeTrb (
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IN SD_TRB *Trb
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);
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#endif
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