Add initial version of Open Virtual Machine Firmware (OVMF) platform.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8398 6f19259b-4bc3-4df7-8a09-765794883524

OvmfPkg/ResetVector/Bin/ResetVector.inf

@@ -0,0 +1,35 @@
+#/** @file
+#  Reset Vector binary
+#
+#  Copyright (c) 2006 - 2009, Intel Corporation.
+#
+#  All rights reserved. This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ResetVector
+  FILE_GUID                      = 1BA0062E-C779-4582-8566-336AE8F78F09
+  MODULE_TYPE                    = SEC
+  VERSION_STRING                 = 1.1
+  EDK_RELEASE_VERSION            = 0x00020000
+  EFI_SPECIFICATION_VERSION      = 0x00020000
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+[Binaries.Ia32]
+  RAW|ResetVector.ia32.raw|*
+
+[Binaries.X64]
+  RAW|ResetVector.x64.raw|*
+

OvmfPkg/ResetVector/CommonMacros.inc

@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   CommonMacros.inc
+;
+; Abstract:
+;
+;   Common macros used in the ResetVector VTF module.
+;
+;------------------------------------------------------------------------------
+
+%define ADDR16_OF(x) (0x10000 - fourGigabytes + x)
+%define ADDR_OF(x) (0x100000000 - fourGigabytes + x)
+
+%macro  callEdx 1
+    mov     edx, ADDR_OF(%%returnLabel)
+    jmp     %1
+%%returnLabel:
+%endmacro
+
+%macro  OneTimeCall 1
+    jmp     %1
+%1 %+ OneTimerCallReturn:
+%endmacro
+
+%macro  OneTimeCallRet 1
+    jmp     %1 %+ OneTimerCallReturn
+%endmacro
+
+StartOfResetVectorCode:
+
+%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode)
+

OvmfPkg/ResetVector/Ia16/16RealTo32Flat.asm

@@ -0,0 +1,151 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   16RealTo32Flat.asm
+;
+; Abstract:
+;
+;   Transition from 16 bit real mode into 32 bit flat protected mode
+;
+;------------------------------------------------------------------------------
+
+%define SEC_DEFAULT_CR0  0x40000023
+%define SEC_DEFAULT_CR4  0x640
+
+BITS    16
+
+to32BitFlat:
+
+    writeToSerialPort '1'
+    writeToSerialPort '6'
+    writeToSerialPort ' '
+
+    cli
+
+    mov     bx, 0xf000
+    mov     ds, bx
+
+    mov     bx, ADDR16_OF(gdtr)
+
+o32 lgdt    [bx]
+
+    mov     eax, SEC_DEFAULT_CR0
+    mov     cr0, eax
+
+;    mov     eax, cr0
+;    or      al, 1
+;    mov     cr0, eax
+
+    jmp     LINEAR_CODE_SEL:dword ADDR_OF(jumpTo32BitAndLandHere)
+BITS    32
+jumpTo32BitAndLandHere:
+
+    mov     eax, SEC_DEFAULT_CR4
+    mov     cr4, eax
+
+    writeToSerialPort '3'
+    writeToSerialPort '2'
+    writeToSerialPort ' '
+
+    mov ax, LINEAR_SEL
+    mov ds, ax
+    mov es, ax
+    mov fs, ax
+    mov gs, ax
+    mov ss, ax
+
+    jmp     TransitionFrom16RealTo32FlatComplete
+
+ALIGN   2
+
+gdtr:
+    dw      GDT_END - GDT_BASE - 1   ; GDT limit
+    dd      ADDR_OF(GDT_BASE)
+
+ALIGN   16
+
+GDT_BASE:
+; null descriptor
+NULL_SEL            equ $-GDT_BASE
+        dw 0            ; limit 15:0
+        dw 0            ; base 15:0
+        db 0            ; base 23:16
+        db 0            ; type
+        db 0            ; limit 19:16, flags
+        db 0            ; base 31:24
+
+; linear data segment descriptor
+LINEAR_SEL      equ $-GDT_BASE
+        dw 0FFFFh       ; limit 0xFFFFF
+        dw 0            ; base 0
+        db 0
+        db 092h         ; present, ring 0, data, expand-up, writable
+        db 0CFh                 ; page-granular, 32-bit
+        db 0
+
+; linear code segment descriptor
+LINEAR_CODE_SEL equ $-GDT_BASE
+        dw 0FFFFh       ; limit 0xFFFFF
+        dw 0            ; base 0
+        db 0
+        db 09Ah         ; present, ring 0, data, expand-up, writable
+        db 0CFh                 ; page-granular, 32-bit
+        db 0
+
+; system data segment descriptor
+SYS_DATA_SEL    equ $-GDT_BASE
+        dw 0FFFFh       ; limit 0xFFFFF
+        dw 0            ; base 0
+        db 0
+        db 092h         ; present, ring 0, data, expand-up, writable
+        db 0CFh                 ; page-granular, 32-bit
+        db 0
+
+; system code segment descriptor
+SYS_CODE_SEL    equ $-GDT_BASE
+        dw 0FFFFh       ; limit 0xFFFFF
+        dw 0            ; base 0
+        db 0
+        db 09Ah         ; present, ring 0, data, expand-up, writable
+        db 0CFh                 ; page-granular, 32-bit
+        db 0
+
+; spare segment descriptor
+LINEAR_CODE64_SEL  equ $-GDT_BASE
+    DW      -1                  ; LimitLow
+    DW      0                   ; BaseLow
+    DB      0                   ; BaseMid
+    DB      9bh
+    DB      0afh                ; LimitHigh   (CS.L=1, CS.D=0)
+    DB      0                   ; BaseHigh
+
+; spare segment descriptor
+SPARE4_SEL  equ $-GDT_BASE
+        dw 0            ; limit 0xFFFFF
+        dw 0            ; base 0
+        db 0
+        db 0            ; present, ring 0, data, expand-up, writable
+        db 0            ; page-granular, 32-bit
+        db 0
+
+; spare segment descriptor
+SPARE5_SEL  equ $-GDT_BASE
+        dw 0            ; limit 0xFFFFF
+        dw 0            ; base 0
+        db 0
+        db 0            ; present, ring 0, data, expand-up, writable
+        db 0            ; page-granular, 32-bit
+        db 0
+
+GDT_END:
+

OvmfPkg/ResetVector/Ia16/ResetVectorOldTools.asm

@@ -0,0 +1,51 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   Reset-16Bit-old-tools.asm
+;
+; Abstract:
+;
+;   First code exectuted by processor after resetting.
+;
+;------------------------------------------------------------------------------
+
+BITS	16
+
+earlyInit_Real16:
+
+	jmp	real16InitSerialPort
+real16SerialPortInitReturn:
+
+	jmp	to32BitFlat
+
+ALIGN	16
+
+;
+; Junk data.  Old GenFv tool will modify data here.
+;
+	DQ	0, 0
+
+;
+; Reset Vector
+;
+; This is where the processor will begin execution
+;
+	jmp	short earlyInit_Real16
+
+;
+; Junk data.  Old GenFv tool will modify data here.
+;
+ALIGN	16
+
+fourGigabytes:
+

OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm

@@ -0,0 +1,54 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   Reset-16Bit-vft0.asm
+;
+; Abstract:
+;
+;   First code exectuted by processor after resetting.
+;
+;------------------------------------------------------------------------------
+
+BITS	16
+
+earlyInit_Real16:
+
+	jmp	real16InitSerialPort
+real16SerialPortInitReturn:
+
+	jmp	to32BitFlat
+
+ALIGN	16
+
+	DD	0, 0, 0
+
+;
+; The VTF signature
+;
+; VTF-0 means that the VTF (Volume Top File) code does not require
+; any fixups.
+;
+vtfSignature:
+	DB	'V', 'T', 'F', 0
+
+;
+; Reset Vector
+;
+; This is where the processor will begin execution
+;
+	jmp	short earlyInit_Real16
+
+ALIGN	16
+
+fourGigabytes:
+

OvmfPkg/ResetVector/Ia32/32FlatTo64Flat.asm

@@ -0,0 +1,51 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   32FlatTo64Flat.asm
+;
+; Abstract:
+;
+;   Transition from 32 bit flat protected mode into 64 bit flat protected mode
+;
+;------------------------------------------------------------------------------
+
+BITS    32
+
+Transition32FlatTo64Flat:
+
+    mov     eax, ((ADDR_OF_START_OF_RESET_CODE & ~0xfff) - 0x1000)
+    mov     cr3, eax
+
+    mov     eax, cr4
+    bts     eax, 5                      ; enable PAE
+    mov     cr4, eax                    
+
+    mov     ecx, 0xc0000080
+    rdmsr
+    bts     eax, 8                      ; set LME
+    wrmsr
+
+    mov     eax, cr0
+    bts     eax, 31                     ; set PG
+    mov     cr0, eax                    ; enable paging
+
+    jmp     LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere)
+BITS    64
+jumpTo64BitAndLandHere:
+
+    writeToSerialPort '6'
+    writeToSerialPort '4'
+    writeToSerialPort ' '
+
+    OneTimeCallRet Transition32FlatTo64Flat
+

OvmfPkg/ResetVector/Ia32/SearchForBfvBase.asm

@@ -0,0 +1,88 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   SearchForBfvBase.asm
+;
+; Abstract:
+;
+;   Search for the Boot FV Base Address
+;
+;------------------------------------------------------------------------------
+
+;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \
+;  { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }
+%define FFS_GUID_DWORD0 0x8c8ce578
+%define FFS_GUID_DWORD1 0x4f1c8a3d
+%define FFS_GUID_DWORD2 0x61893599
+%define FFS_GUID_DWORD3 0xd32dc385
+
+BITS    32
+
+;
+; Input:
+;   None
+;
+; Output:
+;   EBP - BFV Base Address
+;
+; Modified:
+;   EAX, EBX
+;
+Flat32SearchForBfvBase:
+
+    xor     eax, eax
+searchingForBfvHeaderLoop:
+    sub     eax, 0x1000
+    cmp     eax, 0xff800000
+    jb      searchedForBfvHeaderButNotFound
+
+    ;
+    ; Check FFS GUID
+    ;
+    cmp     dword [eax + 0x10], FFS_GUID_DWORD0
+    jne     searchingForBfvHeaderLoop
+    cmp     dword [eax + 0x14], FFS_GUID_DWORD1
+    jne     searchingForBfvHeaderLoop
+    cmp     dword [eax + 0x18], FFS_GUID_DWORD2
+    jne     searchingForBfvHeaderLoop
+    cmp     dword [eax + 0x1c], FFS_GUID_DWORD3
+    jne     searchingForBfvHeaderLoop
+
+    ;
+    ; Check FV Length
+    ;
+    cmp     dword [eax + 0x24], 0
+    jne     searchingForBfvHeaderLoop
+    mov     ebx, eax
+    add     ebx, dword [eax + 0x20]
+    jnz     searchingForBfvHeaderLoop
+
+    jmp     searchedForBfvHeaderAndItWasFound
+
+searchedForBfvHeaderButNotFound:
+    writeToSerialPort '!'
+    xor     eax, eax
+
+searchedForBfvHeaderAndItWasFound:
+    mov     ebp, eax
+
+    writeToSerialPort 'B'
+    writeToSerialPort 'F'
+    writeToSerialPort 'V'
+    writeToSerialPort ' '
+
+    or      ebp, ebp
+    jz      $
+
+    OneTimeCallRet Flat32SearchForBfvBase
+

OvmfPkg/ResetVector/Ia32/SearchForSecAndPeiEntries.asm

@@ -0,0 +1,199 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   SearchForSecAndPeiEntry.asm
+;
+; Abstract:
+;
+;   Search for the SEC Core and PEI Core entry points
+;
+;------------------------------------------------------------------------------
+
+BITS    32
+
+%define EFI_FV_FILETYPE_SECURITY_CORE         0x03
+%define EFI_FV_FILETYPE_PEI_CORE              0x04
+
+;
+; Input:
+;   EBP - BFV Base Address
+;
+; Output:
+;   ESI - SEC Core Entry Point Address (or 0 if not found)
+;   EDI - PEI Core Entry Point Address (or 0 if not found)
+;
+; Modified:
+;   EAX, EBX, ECX
+;
+Flat32SearchForSecAndPeiEntries:
+
+    ;
+    ; Initialize EBP and ESI to 0
+    ;
+    xor     ebx, ebx
+    mov     esi, ebx
+    mov     edi, ebx
+
+    ;
+    ; Pass over the BFV header
+    ;
+    mov     eax, ebp
+    mov     bx, [ebp + 0x30]
+    add     eax, ebx
+    jc      doneSeachingForSecAndPeiEntries
+
+    jmp     searchingForFfsFileHeaderLoop
+
+moveForwardWhileSearchingForFfsFileHeaderLoop:
+    ;
+    ; Make forward progress in the search
+    ;
+    inc     eax
+    jc      doneSeachingForSecAndPeiEntries
+
+searchingForFfsFileHeaderLoop:
+    test    eax, eax
+    jz      doneSeachingForSecAndPeiEntries
+
+    ;
+    ; Ensure 8 byte alignment
+    ;
+    add     eax, 7
+    jc      doneSeachingForSecAndPeiEntries
+    and     al, 0xf8
+
+    ;
+    ; Look to see if there is an FFS file at eax
+    ;
+    mov     bl, [eax + 0x17]
+    test    bl, 0x20
+    jz      moveForwardWhileSearchingForFfsFileHeaderLoop
+    mov     ecx, [eax + 0x14]
+    and     ecx, 0x00ffffff
+    or      ecx, ecx
+    jz      moveForwardWhileSearchingForFfsFileHeaderLoop
+;    jmp     $
+    add     ecx, eax
+    jz      jumpSinceWeFoundTheLastFfsFile
+    jc      moveForwardWhileSearchingForFfsFileHeaderLoop
+jumpSinceWeFoundTheLastFfsFile:
+
+    ;
+    ; There seems to be a valid file at eax
+    ;
+    mov     bl, [eax + 0x12] ; BL - File Type
+    cmp     bl, EFI_FV_FILETYPE_PEI_CORE
+    je      fileTypeIsPeiCore
+    cmp     bl, EFI_FV_FILETYPE_SECURITY_CORE
+    jne     readyToTryFfsFileAtEcx
+
+fileTypeIsSecCore:
+    callEdx GetEntryPointOfFfsFileReturnEdx
+    test    eax, eax
+    jz      readyToTryFfsFileAtEcx
+
+    mov     esi, eax
+    jmp     readyToTryFfsFileAtEcx
+
+fileTypeIsPeiCore:
+    callEdx GetEntryPointOfFfsFileReturnEdx
+    test    eax, eax
+    jz      readyToTryFfsFileAtEcx
+
+    mov     edi, eax
+
+readyToTryFfsFileAtEcx:
+    mov     eax, ecx
+    jmp     searchingForFfsFileHeaderLoop
+
+doneSeachingForSecAndPeiEntries:
+
+    test    esi, esi
+    jnz     secCoreEntryPointWasFound
+    writeToSerialPort '!'
+secCoreEntryPointWasFound:
+    writeToSerialPort 'S'
+    writeToSerialPort 'E'
+    writeToSerialPort 'C'
+    writeToSerialPort ' '
+
+    test    edi, edi
+    jnz     peiCoreEntryPointWasFound
+    writeToSerialPort '!'
+peiCoreEntryPointWasFound:
+    writeToSerialPort 'P'
+    writeToSerialPort 'E'
+    writeToSerialPort 'I'
+    writeToSerialPort ' '
+
+    OneTimeCallRet Flat32SearchForSecAndPeiEntries
+
+
+%define EFI_SECTION_PE32                  0x10
+
+;
+; Input:
+;   EAX - Start of FFS file
+;
+; Output:
+;   EAX - Entry point of PE32 (or 0 if not found)
+;
+; Modified:
+;   EBX
+;
+GetEntryPointOfFfsFileReturnEdx:
+    test    eax, eax
+    jz      getEntryPointOfFfsFileErrorReturn
+
+    cmp     byte [eax + 0x1b], EFI_SECTION_PE32
+    jne     getEntryPointOfFfsFileErrorReturn
+
+    add     eax, 0x1c       ; EAX = Start of PE32 image
+
+    mov     ebx, eax
+    cmp     word [eax], 'MZ'
+    jne     thereIsNotAnMzSignature
+    movzx   ebx, word [eax + 0x3c]
+    add     ebx, eax
+thereIsNotAnMzSignature:
+
+    ; if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE)
+    cmp     word [ebx], 'VZ'
+    jne     thereIsNoVzSignature
+    ; *EntryPoint = (VOID *)((UINTN)Pe32Data +
+    ;   (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) +
+    ;   sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize);
+    add     eax, [ebx + 0x8]
+    add     eax, 0x28
+    movzx   ebx, word [ebx + 0x6]
+    sub     eax, ebx
+    jmp     getEntryPointOfFfsFileReturn
+
+thereIsNoVzSignature:
+
+    ; if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE)
+    cmp     dword [ebx], `PE\x00\x00`
+    jne     getEntryPointOfFfsFileErrorReturn
+
+    ; *EntryPoint = (VOID *)((UINTN)Pe32Data +
+    ;   (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff));
+    add     eax, [ebx + 0x4 + 0x14 + 0x10]
+    jmp     getEntryPointOfFfsFileReturn
+
+getEntryPointOfFfsFileErrorReturn:
+    mov     eax, 0
+
+getEntryPointOfFfsFileReturn:
+    jmp     edx
+
+

OvmfPkg/ResetVector/JumpToSec.asm

@@ -0,0 +1,63 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   JumpToSec.asm
+;
+; Abstract:
+;
+;   Jump from the reset vector binary to SEC
+;
+;------------------------------------------------------------------------------
+
+BITS    32
+
+TransitionFrom16RealTo32FlatComplete:
+
+    OneTimeCall Flat32SearchForBfvBase
+
+    OneTimeCall Flat32SearchForSecAndPeiEntries
+
+    ;
+    ; ESI - SEC Core entry point
+    ; EDI - PEI Core entry point
+    ; EBP - Start of BFV
+    ;
+    ; Jump to SEC Core entry point
+    ;
+
+%ifdef ARCH_IA32
+
+    jmp     esi
+
+%else
+
+    OneTimeCall Transition32FlatTo64Flat
+BITS    64
+
+    mov     rax, 0x00000000ffffffff
+    and     rsi, rax
+    and     rdi, rax
+    and     rbp, rax
+    ;
+    ; RSI - SEC Core entry point
+    ; RDI - PEI Core entry point
+    ; RBP - Start of BFV
+    ;
+    ; Jump to SEC Core entry point
+    ;
+
+    jmp     rsi
+
+%endif
+
+

OvmfPkg/ResetVector/Makefile

@@ -0,0 +1,42 @@
+## @file
+#  Makefile to create FFS Raw sections for VTF images.
+#
+#  Copyright (c) 2008, Intel Corporation
+#
+#  All rights reserved. This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+TARGETS = Bin/ResetVector.ia32.raw Bin/ResetVector.x64.raw
+ASM = nasm
+
+COMMON_DEPS = \
+  Ia16/16RealTo32Flat.asm \
+  Ia32/32FlatTo64Flat.asm \
+  JumpToSec.asm \
+  Ia16/ResetVectorVtf0.asm \
+  Ia32/SearchForBfvBase.asm \
+  Ia32/SearchForSecAndPeiEntries.asm \
+  SerialDebug.asm \
+  Makefile \
+  Tools/FixupForRawSection.py
+
+.PHONY: all
+all: $(TARGETS)
+
+Bin/ResetVector.ia32.raw: $(COMMON_DEPS) ResetVectorCode.asm
+	nasm -D ARCH_IA32 -o $@ ResetVectorCode.asm
+	python Tools/FixupForRawSection.py $@
+
+Bin/ResetVector.x64.raw: $(COMMON_DEPS) ResetVectorCode.asm
+	nasm -D ARCH_X64 -o $@ ResetVectorCode.asm
+	python Tools/FixupForRawSection.py $@
+
+clean:
+	-rm $(TARGETS)
+

OvmfPkg/ResetVector/ResetVectorCode.asm

@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   ResetVectorCode.asm
+;
+; Abstract:
+;
+;   Create code for VTF raw section.
+;
+;------------------------------------------------------------------------------
+
+%ifdef ARCH_IA32
+  %ifdef ARCH_X64
+    %error "Only one of ARCH_IA32 or ARCH_X64 can be defined."
+  %endif
+%elifdef ARCH_X64
+%else
+  %error "Either ARCH_IA32 or ARCH_X64 must be defined."
+%endif
+
+%include "CommonMacros.inc"
+%include "SerialDebug.asm"
+%include "Ia32/SearchForBfvBase.asm"
+%include "Ia32/SearchForSecAndPeiEntries.asm"
+%include "JumpToSec.asm"
+%include "Ia16/16RealTo32Flat.asm"
+
+%ifdef ARCH_X64
+%include "Ia32/32FlatTo64Flat.asm"
+%endif
+
+%include "Ia16/ResetVectorVtf0.asm"
+

OvmfPkg/ResetVector/SerialDebug.asm

@@ -0,0 +1,114 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2008, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   SerialDebug.asm
+;
+; Abstract:
+;
+;   Serial port support macros
+;
+;------------------------------------------------------------------------------
+
+BITS    16
+
+;//---------------------------------------------
+;// UART Register Offsets
+;//---------------------------------------------
+%define BAUD_LOW_OFFSET         0x00
+%define BAUD_HIGH_OFFSET        0x01
+%define IER_OFFSET              0x01
+%define LCR_SHADOW_OFFSET       0x01
+%define FCR_SHADOW_OFFSET       0x02
+%define IR_CONTROL_OFFSET       0x02
+%define FCR_OFFSET              0x02
+%define EIR_OFFSET              0x02
+%define BSR_OFFSET              0x03
+%define LCR_OFFSET              0x03
+%define MCR_OFFSET              0x04
+%define LSR_OFFSET              0x05
+%define MSR_OFFSET              0x06
+
+;//---------------------------------------------
+;// UART Register Bit Defines
+;//---------------------------------------------
+%define LSR_TXRDY               0x20
+%define LSR_RXDA                0x01
+%define DLAB                    0x01
+
+; UINT16  gComBase = 0x3f8;
+; UINTN   gBps = 115200;
+; UINT8   gData = 8;
+; UINT8   gStop = 1;
+; UINT8   gParity = 0;
+; UINT8   gBreakSet = 0;
+
+%define DEFAULT_COM_BASE 0x3f8
+%define DEFAULT_BPS 115200
+%define DEFAULT_DATA 8
+%define DEFAULT_STOP 1
+%define DEFAULT_PARITY 0
+%define DEFAULT_BREAK_SET 0
+
+%define SERIAL_DEFAULT_LCR ( \
+     (DEFAULT_BREAK_SET << 6) | \
+     (DEFAULT_PARITY << 3) | \
+     (DEFAULT_STOP << 2) | \
+     (DEFAULT_DATA - 5) \
+    )
+
+%define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE
+
+%macro  inFromSerialPort 1
+    mov     dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)
+    in      al, dx
+%endmacro
+
+%macro  waitForSerialTxReady 0
+
+%%waitingForTx:
+    inFromSerialPort LSR_OFFSET
+    test    al, LSR_TXRDY
+    jz      %%waitingForTx
+
+%endmacro
+
+%macro  outToSerialPort 2
+    mov     dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)
+    mov     al, %2
+    out     dx, al
+%endmacro
+
+%macro  writeToSerialPort 1
+    waitForSerialTxReady
+    outToSerialPort 0, %1
+%endmacro
+
+real16InitSerialPort:
+    ;
+    ; Set communications format
+    ;
+    outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR)
+
+    ;
+    ; Configure baud rate
+    ;
+    outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8)
+    outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff)
+
+    ;
+    ; Switch back to bank 0
+    ;
+    outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR
+
+    jmp     real16SerialPortInitReturn
+

OvmfPkg/ResetVector/Tools/FixupForRawSection.py

@@ -0,0 +1,110 @@
+## @file
+#  Apply fixup to VTF binary image for FFS Raw section
+#
+#  Copyright (c) 2008, Intel Corporation
+#
+#  All rights reserved. This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+import sys
+
+filename = sys.argv[1]
+
+if filename.lower().find('ia32') >= 0:
+    d = open(sys.argv[1], 'rb').read()
+    c = ((len(d) + 4 + 7) & ~7) - 4
+    if c > len(d):
+        c -= len(d)
+        f = open(sys.argv[1], 'wb')
+        f.write('\x90' * c)
+        f.write(d)
+        f.close()
+else:
+    from struct import pack
+
+    PAGE_PRESENT             =     0x01
+    PAGE_READ_WRITE          =     0x02
+    PAGE_USER_SUPERVISOR     =     0x04
+    PAGE_WRITE_THROUGH       =     0x08
+    PAGE_CACHE_DISABLE       =    0x010
+    PAGE_ACCESSED            =    0x020
+    PAGE_DIRTY               =    0x040
+    PAGE_PAT                 =    0x080
+    PAGE_GLOBAL              =   0x0100
+    PAGE_2M_MBO              =    0x080
+    PAGE_2M_PAT              =  0x01000
+
+    def NopAlign4k(s):
+        c = ((len(s) + 0xfff) & ~0xfff) - len(s)
+        return ('\x90' * c) + s
+
+    def PageDirectoryEntries4GbOf2MbPages(baseAddress):
+
+        s = ''
+        for i in range(0x800):
+            i = (
+                    baseAddress + long(i << 21) +
+                    PAGE_2M_MBO +
+                    PAGE_CACHE_DISABLE +
+                    PAGE_ACCESSED +
+                    PAGE_DIRTY +
+                    PAGE_READ_WRITE +
+                    PAGE_PRESENT
+                )
+            s += pack('Q', i)
+        return s
+
+    def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
+        s = ''
+        for i in range(0x200):
+            i = (
+                    pdeBase +
+                    (min(i, 3) << 12) +
+                    PAGE_CACHE_DISABLE +
+                    PAGE_ACCESSED +
+                    PAGE_READ_WRITE +
+                    PAGE_PRESENT
+                )
+            s += pack('Q', i)
+        return s
+
+    def PageMapLevel4Table4GbOf2MbPages(pdptBase):
+        s = ''
+        for i in range(0x200):
+            i = (
+                    pdptBase +
+                    (min(i, 0) << 12) +
+                    PAGE_CACHE_DISABLE +
+                    PAGE_ACCESSED +
+                    PAGE_READ_WRITE +
+                    PAGE_PRESENT
+                )
+            s += pack('Q', i)
+        return s
+
+    def First4GbPageEntries(topAddress):
+        PDE = PageDirectoryEntries4GbOf2MbPages(0L)
+        pml4tBase = topAddress - 0x1000
+        pdptBase = pml4tBase - 0x1000
+        pdeBase = pdptBase - len(PDE)
+        PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
+        PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
+        return PDE + PDPT + PML4T
+
+    def AlignAndAddPageTables():
+        d = open(sys.argv[1], 'rb').read()
+        code = NopAlign4k(d)
+        topAddress = 0x100000000 - len(code)
+        d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
+        f = open(sys.argv[1], 'wb')
+        f.write(d)
+        f.close()
+
+    AlignAndAddPageTables()
+