Sync BaseTool trunk (version r2599) into EDKII BaseTools.
Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Heshen Chen <chen.heshen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14591 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Liming Gao
lgao4
@@ -1,6 +1,7 @@
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/** @file
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Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
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Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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@@ -146,8 +147,8 @@ InitializeElf64 (
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Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
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return FALSE;
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}
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if (!((mEhdr->e_machine == EM_X86_64))) {
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Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64");
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if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64))) {
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Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64 or EM_AARCH64");
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return FALSE;
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}
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if (mEhdr->e_version != EV_CURRENT) {
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@@ -269,6 +270,7 @@ ScanSections64 (
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switch (mEhdr->e_machine) {
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case EM_X86_64:
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case EM_IA_64:
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case EM_AARCH64:
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mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
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break;
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default:
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@@ -412,6 +414,10 @@ ScanSections64 (
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NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_IPF;
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NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
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break;
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case EM_AARCH64:
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NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_AARCH64;
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NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
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break;
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default:
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VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
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NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
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@@ -542,22 +548,55 @@ WriteSections64 (
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//
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VerboseMsg ("Applying Relocations...");
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for (Idx = 0; Idx < mEhdr->e_shnum; Idx++) {
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//
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// Determine if this is a relocation section.
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//
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Elf_Shdr *RelShdr = GetShdrByIndex(Idx);
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if ((RelShdr->sh_type != SHT_REL) && (RelShdr->sh_type != SHT_RELA)) {
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continue;
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}
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//
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// Relocation section found. Now extract section information that the relocations
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// apply to in the ELF data and the new COFF data.
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//
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SecShdr = GetShdrByIndex(RelShdr->sh_info);
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SecOffset = mCoffSectionsOffset[RelShdr->sh_info];
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//
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// Only process relocations for the current filter type.
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//
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if (RelShdr->sh_type == SHT_RELA && (*Filter)(SecShdr)) {
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UINT64 RelIdx;
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//
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// Determine the symbol table referenced by the relocation data.
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//
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Elf_Shdr *SymtabShdr = GetShdrByIndex(RelShdr->sh_link);
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UINT8 *Symtab = (UINT8*)mEhdr + SymtabShdr->sh_offset;
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//
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// Process all relocation entries for this section.
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//
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for (RelIdx = 0; RelIdx < RelShdr->sh_size; RelIdx += (UINT32) RelShdr->sh_entsize) {
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//
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// Set pointer to relocation entry
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//
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Elf_Rela *Rel = (Elf_Rela *)((UINT8*)mEhdr + RelShdr->sh_offset + RelIdx);
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//
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// Set pointer to symbol table entry associated with the relocation entry.
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//
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Elf_Sym *Sym = (Elf_Sym *)(Symtab + ELF_R_SYM(Rel->r_info) * SymtabShdr->sh_entsize);
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Elf_Shdr *SymShdr;
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UINT8 *Targ;
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//
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// Check section header index found in symbol table and get the section
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// header location.
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//
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if (Sym->st_shndx == SHN_UNDEF
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|| Sym->st_shndx == SHN_ABS
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|| Sym->st_shndx > mEhdr->e_shnum) {
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@@ -566,11 +605,20 @@ WriteSections64 (
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SymShdr = GetShdrByIndex(Sym->st_shndx);
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//
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// Note: r_offset in a memory address.
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// Convert it to a pointer in the coff file.
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// Convert the relocation data to a pointer into the coff file.
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//
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// Note:
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// r_offset is the virtual address of the storage unit to be relocated.
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// sh_addr is the virtual address for the base of the section.
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//
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// r_offset in a memory address.
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// Convert it to a pointer in the coff file.
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//
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Targ = mCoffFile + SecOffset + (Rel->r_offset - SecShdr->sh_addr);
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//
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// Determine how to handle each relocation type based on the machine type.
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//
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if (mEhdr->e_machine == EM_X86_64) {
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switch (ELF_R_TYPE(Rel->r_info)) {
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case R_X86_64_NONE:
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@@ -618,8 +666,51 @@ WriteSections64 (
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default:
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Error (NULL, 0, 3000, "Invalid", "%s unsupported ELF EM_X86_64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
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}
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} else if (mEhdr->e_machine == EM_AARCH64) {
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// AARCH64 GCC uses RELA relocation, so all relocations have to be fixed up.
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// As opposed to ARM32 using REL.
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switch (ELF_R_TYPE(Rel->r_info)) {
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case R_AARCH64_LD_PREL_LO19:
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if (Rel->r_addend != 0 ) { /* TODO */
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Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_LD_PREL_LO19 Need to fixup with addend!.");
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}
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break;
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case R_AARCH64_CALL26:
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if (Rel->r_addend != 0 ) { /* TODO */
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Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CALL26 Need to fixup with addend!.");
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}
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break;
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case R_AARCH64_JUMP26:
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if (Rel->r_addend != 0 ) { /* TODO : AArch64 '-O2' optimisation. */
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Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_JUMP26 Need to fixup with addend!.");
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}
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break;
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case R_AARCH64_ADR_PREL_PG_HI21:
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// TODO : AArch64 'small' memory model.
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Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);
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break;
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case R_AARCH64_ADD_ABS_LO12_NC:
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// TODO : AArch64 'small' memory model.
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Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);
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break;
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// Absolute relocations.
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case R_AARCH64_ABS64:
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*(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
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break;
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default:
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Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
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}
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} else {
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Error (NULL, 0, 3000, "Invalid", "Not EM_X86_X64");
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Error (NULL, 0, 3000, "Invalid", "Not a supported machine type");
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}
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}
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}
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@@ -673,6 +764,45 @@ WriteRelocations64 (
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default:
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Error (NULL, 0, 3000, "Invalid", "%s unsupported ELF EM_X86_64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
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}
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} else if (mEhdr->e_machine == EM_AARCH64) {
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// AArch64 GCC uses RELA relocation, so all relocations has to be fixed up. ARM32 uses REL.
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switch (ELF_R_TYPE(Rel->r_info)) {
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case R_AARCH64_LD_PREL_LO19:
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break;
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case R_AARCH64_CALL26:
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break;
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case R_AARCH64_JUMP26:
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break;
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case R_AARCH64_ADR_PREL_PG_HI21:
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// TODO : AArch64 'small' memory model.
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Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);
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break;
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case R_AARCH64_ADD_ABS_LO12_NC:
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// TODO : AArch64 'small' memory model.
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Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);
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break;
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case R_AARCH64_ABS64:
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CoffAddFixup(
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(UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
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+ (Rel->r_offset - SecShdr->sh_addr)),
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EFI_IMAGE_REL_BASED_DIR64);
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break;
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case R_AARCH64_ABS32:
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CoffAddFixup(
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(UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
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+ (Rel->r_offset - SecShdr->sh_addr)),
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EFI_IMAGE_REL_BASED_HIGHLOW);
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break;
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default:
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Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
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}
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} else {
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Error (NULL, 0, 3000, "Not Supported", "This tool does not support relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr->e_machine);
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}
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@@ -1,5 +1,5 @@
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## @file
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# Windows makefile for 'GenFw' module build.
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# GNU/Linux makefile for 'GenFw' module build.
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#
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# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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@@ -2,6 +2,7 @@
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Ported ELF include files from FreeBSD
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Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -183,6 +184,7 @@ typedef struct {
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#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ processor. */
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#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
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#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */
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#define EM_AARCH64 183 /* ARM 64bit Architecture */
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/* Non-standard or deprecated. */
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#define EM_486 6 /* Intel i486. */
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@@ -543,6 +545,135 @@ typedef struct {
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#define R_386_TLS_DTPOFF32 36 /* GOT entry containing TLS offset */
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#define R_386_TLS_TPOFF32 37 /* GOT entry of -ve static TLS offset */
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/* Null relocation */
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#define R_AARCH64_NONE 256 /* No relocation */
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/* Static AArch64 relocations */
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/* Static data relocations */
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#define R_AARCH64_ABS64 257 /* S + A */
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#define R_AARCH64_ABS32 258 /* S + A */
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#define R_AARCH64_ABS16 259 /* S + A */
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#define R_AARCH64_PREL64 260 /* S + A - P */
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#define R_AARCH64_PREL32 261 /* S + A - P */
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#define R_AARCH64_PREL16 262 /* S + A - P */
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/* Group relocations to create a 16, 32, 48, or 64 bit unsigned data value or address inline */
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#define R_AARCH64_MOVW_UABS_G0 263 /* S + A */
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#define R_AARCH64_MOVW_UABS_G0_NC 264 /* S + A */
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#define R_AARCH64_MOVW_UABS_G1 265 /* S + A */
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#define R_AARCH64_MOVW_UABS_G1_NC 266 /* S + A */
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#define R_AARCH64_MOVW_UABS_G2 267 /* S + A */
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#define R_AARCH64_MOVW_UABS_G2_NC 268 /* S + A */
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#define R_AARCH64_MOVW_UABS_G3 269 /* S + A */
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/* Group relocations to create a 16, 32, 48, or 64 bit signed data or offset value inline */
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#define R_AARCH64_MOVW_SABS_G0 270 /* S + A */
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#define R_AARCH64_MOVW_SABS_G1 271 /* S + A */
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#define R_AARCH64_MOVW_SABS_G2 272 /* S + A */
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/* Relocations to generate 19, 21 and 33 bit PC-relative addresses */
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#define R_AARCH64_LD_PREL_LO19 273 /* S + A - P */
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#define R_AARCH64_ADR_PREL_LO21 274 /* S + A - P */
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#define R_AARCH64_ADR_PREL_PG_HI21 275 /* Page(S+A) - Page(P) */
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#define R_AARCH64_ADR_PREL_PG_HI21_NC 276 /* Page(S+A) - Page(P) */
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#define R_AARCH64_ADD_ABS_LO12_NC 277 /* S + A */
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#define R_AARCH64_LDST8_ABS_LO12_NC 278 /* S + A */
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#define R_AARCH64_LDST16_ABS_LO12_NC 284 /* S + A */
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#define R_AARCH64_LDST32_ABS_LO12_NC 285 /* S + A */
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#define R_AARCH64_LDST64_ABS_LO12_NC 286 /* S + A */
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#define R_AARCH64_LDST128_ABS_LO12_NC 299 /* S + A */
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/* Relocations for control-flow instructions - all offsets are a multiple of 4 */
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#define R_AARCH64_TSTBR14 279 /* S+A-P */
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#define R_AARCH64_CONDBR19 280 /* S+A-P */
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#define R_AARCH64_JUMP26 282 /* S+A-P */
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#define R_AARCH64_CALL26 283 /* S+A-P */
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/* Group relocations to create a 16, 32, 48, or 64 bit PC-relative offset inline */
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#define R_AARCH64_MOVW_PREL_G0 287 /* S+A-P */
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#define R_AARCH64_MOVW_PREL_G0_NC 288 /* S+A-P */
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#define R_AARCH64_MOVW_PREL_G1 289 /* S+A-P */
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#define R_AARCH64_MOVW_PREL_G1_NC 290 /* S+A-P */
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#define R_AARCH64_MOVW_PREL_G2 291 /* S+A-P */
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#define R_AARCH64_MOVW_PREL_G2_NC 292 /* S+A-P */
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#define R_AARCH64_MOVW_PREL_G3 293 /* S+A-P */
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/* Group relocations to create a 16, 32, 48, or 64 bit GOT-relative offsets inline */
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#define R_AARCH64_MOVW_GOTOFF_G0 300 /* G(S)-GOT */
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#define R_AARCH64_MOVW_GOTOFF_G0_NC 301 /* G(S)-GOT */
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#define R_AARCH64_MOVW_GOTOFF_G1 302 /* G(S)-GOT */
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#define R_AARCH64_MOVW_GOTOFF_G1_NC 303 /* G(S)-GOT */
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#define R_AARCH64_MOVW_GOTOFF_G2 304 /* G(S)-GOT */
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#define R_AARCH64_MOVW_GOTOFF_G2_NC 305 /* G(S)-GOT */
|
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#define R_AARCH64_MOVW_GOTOFF_G3 306 /* G(S)-GOT */
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||||
/* GOT-relative data relocations */
|
||||
#define R_AARCH64_GOTREL64 307 /* S+A-GOT */
|
||||
#define R_AARCH64_GOTREL32 308 /* S+A-GOT */
|
||||
/* GOT-relative instruction relocations */
|
||||
#define R_AARCH64_GOT_LD_PREL19 309 /* G(S)-P */
|
||||
#define R_AARCH64_LD64_GOTOFF_LO15 310 /* G(S)-GOT */
|
||||
#define R_AARCH64_ADR_GOT_PAGE 311 /* Page(G(S))-Page(P) */
|
||||
#define R_AARCH64_LD64_GOT_LO12_NC 312 /* G(S) */
|
||||
#define R_AARCH64_LD64_GOTPAGE_LO15 313 /* G(S)-Page(GOT) */
|
||||
/* Relocations for thread-local storage */
|
||||
/* General Dynamic TLS relocations */
|
||||
#define R_AARCH64_TLSGD_ADR_PREL21 512 /* G(TLSIDX(S+A)) - P */
|
||||
#define R_AARCH64_TLSGD_ADR_PAGE21 513 /* Page(G(TLSIDX(S+A))) - Page(P) */
|
||||
#define R_AARCH64_TLSGD_ADD_LO12_NC 514 /* G(TLSIDX(S+A)) */
|
||||
#define R_AARCH64_TLSGD_MOVW_G1 515 /* G(TLSIDX(S+A)) - GOT */
|
||||
#define R_AARCH64_TLSGD_MOVW_G0_NC 516 /* G(TLSIDX(S+A)) - GOT */
|
||||
/* Local Dynamic TLS relocations */
|
||||
#define R_AARCH64_TLSLD_ADR_PREL21 517 /* G(LDM(S))) - P */
|
||||
#define R_AARCH64_TLSLD_ADR_PAGE21 518 /* Page(G(LDM(S)))-Page(P) */
|
||||
#define R_AARCH64_TLSLD_ADD_LO12_NC 519 /* G(LDM(S)) */
|
||||
#define R_AARCH64_TLSLD_MOVW_G1 520 /* G(LDM(S)) - GOT */
|
||||
#define R_AARCH64_TLSLD_MOVW_G0_NC 521 /* G(LDM(S)) - GOT */
|
||||
#define R_AARCH64_TLSLD_LD_PREL19 522 /* G(LDM(S)) - P */
|
||||
#define R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 527 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 /* DTPREL(S+A) */
|
||||
/* Initial Exec TLS relocations */
|
||||
#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 /* G(TPREL(S+A)) - GOT */
|
||||
#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 /* G(TPREL(S+A)) - GOT */
|
||||
#define R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 /* Page(G(TPREL(S+A))) - Page(P) */
|
||||
#define R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 /* G(TPREL(S+A)) */
|
||||
#define R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 /* G(TPREL(S+A)) - P */
|
||||
/* Local Exec TLS relocations */
|
||||
#define R_AARCH64_TLSLE_MOVW_TPREL_G2 544 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_MOVW_TPREL_G1 545 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_MOVW_TPREL_G1_NC 546 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_MOVW_TPREL_G0 547 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_MOVW_TPREL_G0_NC 548 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_ADD_TPREL_HI12 549 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_ADD_TPREL_LO12 550 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_ADD_TPREL_LO12_NC 551 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_LDST8_TPREL_LO12 552 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 553 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_LDST16_TPREL_LO12 554 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 555 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_LDST32_TPREL_LO12 556 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 557 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_LDST64_TPREL_LO12 558 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 559 /* TPREL(S+A) */
|
||||
/* Dynamic relocations */
|
||||
/* Dynamic relocations */
|
||||
#define R_AARCH64_COPY 1024
|
||||
#define R_AARCH64_GLOB_DAT 1025 /* S + A */
|
||||
#define R_AARCH64_JUMP_SLOT 1026 /* S + A */
|
||||
#define R_AARCH64_RELATIVE 1027 /* Delta(S) + A , Delta(P) + A */
|
||||
#define R_AARCH64_TLS_DTPREL64 1028 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLS_DTPMOD64 1029 /* LDM(S) */
|
||||
#define R_AARCH64_TLS_TPREL64 1030 /* TPREL(S+A) */
|
||||
#define R_AARCH64_TLS_DTPREL32 1031 /* DTPREL(S+A) */
|
||||
#define R_AARCH64_TLS_DTPMOD32 1032 /* LDM(S) */
|
||||
#define R_AARCH64_TLS_TPREL32 1033 /* DTPREL(S+A) */
|
||||
|
||||
#define R_ALPHA_NONE 0 /* No reloc */
|
||||
#define R_ALPHA_REFLONG 1 /* Direct 32 bit */
|
||||
#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */
|
||||
|
||||
Reference in New Issue
Block a user