sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

IntelFsp2Pkg: Adopt FSP 2.3 specification.

Browse Source 
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3674

Add ExtendedImageRevision in FSP_INFO_HEADER structure, also add
FSP_NON_VOLATILE_STORAGE_HOB2 header.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Chasel Chiu
2021-10-01 15:34:39 +08:00
committed by mergify[bot]
parent 22873f58c4
commit 4cc1458dbe
3 changed files with 57 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
View File

@@ -2,7 +2,7 @@
Intel FSP Header File definition from Intel Firmware Support Package External
Architecture Specification v2.0 and above.
Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -44,14 +44,28 @@ typedef struct {
UINT8 Reserved1[2];
///
/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
/// For revision v2.3 the value will be 0x23.
///
UINT8 SpecVersion;
///
/// Byte 0x0B: Revision of the FSP Information Header.
/// The Current value for this field is 0x6.
///
UINT8 HeaderRevision;
///
/// Byte 0x0C: Revision of the FSP binary.
/// Major.Minor.Revision.Build
/// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:
/// 7 : 0 - Build Number
/// 15 : 8 - Revision
/// 23 : 16 - Minor Version
/// 31 : 24 - Major Version
/// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision
/// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.
/// 7 : 0 - Low Byte of Build Number
/// 15 : 8 - Low Byte of Revision
/// 23 : 16 - Minor Version
/// 31 : 24 - Major Version
///
UINT32 ImageRevision;
///
@@ -116,6 +130,23 @@ typedef struct {
/// If the value is set to 0x00000000, then this API is not available in this component.
///
UINT32 FspMultiPhaseSiInitEntryOffset;
///
/// Byte 0x4C: Extended revision of the FSP binary.
/// This value is only valid if FSP HeaderRevision is >= 6.
/// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.
/// 7 : 0 - High Byte of Build Number
/// 15 : 8 - High Byte of Revision
/// The FSP binary build number can be decoded as follows:
/// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]
/// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]
/// Minor Version = ImageRevision[23:16]
/// Major Version = ImageRevision[31:24]
///
UINT16 ExtendedImageRevision;
///
/// Byte 0x4E: Reserved4.
///
UINT16 Reserved4;
} FSP_INFO_HEADER;
///

24
IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h Normal file
View File

@@ -0,0 +1,24 @@
/** @file
Intel FSP Non-Volatile Storage (NVS) HOB version 2 definition from
Intel Firmware Support Package External Architecture Specification v2.3.
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FSP_NON_VOLATILE_STORAGE_HOB2_H__
#define __FSP_NON_VOLATILE_STORAGE_HOB2_H__
///
/// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support.
///
typedef struct {
EFI_HOB_GUID_TYPE GuidHob;
EFI_PHYSICAL_ADDRESS NvsDataPtr;
UINT64 NvsDataLength;
} FSP_NON_VOLATILE_STORAGE_HOB2;
extern EFI_GUID gFspNonVolatileStorageHob2Guid;
#endif