ArmPlatformPkg/Sec: Replaced hardcode SCR and NSACR values by PCDs to enable CPU and Platform Specific settings

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12637 6f19259b-4bc3-4df7-8a09-765794883524
2011-11-01 23:41:20 +00:00
parent 504d14603d
commit 513aa3497a
6 changed files with 76 additions and 9 deletions
--- a/ArmPlatformPkg/Sec/Helper.asm
+++ b/ArmPlatformPkg/Sec/Helper.asm
@@ -15,6 +15,7 @@
    EXPORT  return_from_exception
    EXPORT  enter_monitor_mode
    EXPORT  copy_cpsr_into_spsr
+    EXPORT  set_non_secure_mode
    
    AREA   Helper, CODE, READONLY

@@ -60,6 +61,18 @@ copy_cpsr_into_spsr
    msr     spsr_cxsf, r0
    bx      lr

+// Set the Non Secure Mode
+set_non_secure_mode
+    push    { r1 }
+    and	r0, r0, #0x1f     // Keep only the mode bits
+    mrs     r1, spsr          // Read the spsr
+    bic     r1, r1, #0x1f     // Clear all mode bits
+    orr	    r1, r1, r0
+    msr     spsr_cxsf, r1     // write back spsr (may have caused a mode switch)
+    isb
+    pop     { r1 }
+    bx      lr                // return (hopefully thumb-safe!)
+
 dead
    B       dead