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ArmPlatformPkg/Sec: Replaced hardcode SCR and NSACR values by PCDs to enable CPU and Platform Specific settings

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12637 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-11-01 23:41:20 +00:00
parent 504d14603d
commit 513aa3497a
6 changed files with 76 additions and 9 deletions
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19
ArmPlatformPkg/Sec/Sec.c
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@@ -133,16 +133,11 @@ CEntryPoint (
// Transfer the interrupt to Non-secure World
ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World
// - Enable Access to Preload Engine in NS World
// - Enable lockable TLB entries allocation in NS world
// - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
ArmWriteNsacr (NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
// Write to CP15 Non-secure Access Control Register
ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
// CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
// security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
ArmWriteScr (SCR_NS | SCR_FW | SCR_AW);
// CP15 Secure Configuration Register
ArmWriteScr (PcdGet32 (PcdArmScr));
} else {
if (IS_PRIMARY_CORE(MpId)) {
SerialPrint ("Trust Zone Configuration is disabled\n\r");
@@ -157,6 +152,12 @@ CEntryPoint (
JumpAddress = PcdGet32 (PcdFvBaseAddress);
ArmPlatformSecExtraAction (MpId, &JumpAddress);
// If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
// By not set, the mode for Non Secure World is SVC
if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
}
return_from_exception (JumpAddress);
//-------------------- Non Secure Mode ---------------------